FinFETs And 3D ICs
Semiconductor Manufacturing and Design talks with Soitec’s Steve Longoria about the role of FD-SOI in advanced semiconductor design and 3D stacks.
Tags: FD-SOI, fully-depleted SOI, SOI, Soitec
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Deep Insights for Chip Builders
The move to 450mm wafers is under way, but nagging questions about ROI remain.…
Let's All Meet At The Via Bar!
Complex requirements for selecting and placing multiple via types are challenging router LEF/tech files at advanced node…
Where do I know that guy from? And why is he here?…
Planar FD-SOI, FinFET, RF, memory and more—highlights of some great papers…
Overcoming Shallow Trench Isolation
Significant challenges emerge for sub-20nm STI etch step.…
The latest milestones and future trends for making MEMS a mainstream technology.…
Unanswered questions loom over silicon suppliers prior to the 450mm wafer conversion. …
Low-e Windows Built Using The Design Rules
How to create low e windows using design rules for the four energy bands.…
Fab Equipment Spending To Rise
Strong 2nd half pulls 2013 finally into positive territory, 2014 growth in double digits.…
SPIE Advanced Lithography 2013 - day 4
The last day of the conference gave the tool updates. So how is EUV progressing?…
Lessons From Past Architecture Wars
Why was Intel so successful when its very capable rivals were not? And can it maintain its lead?…
There's More To EUV Than Source Power
With a more powerful source, lithographers can use less-sensitive resists that are less prone to pattern collapse.…
Semiconductor Manufacturing and Design talks with Soitec’s Steve Longoria about the role of FD-SOI in advanced semiconductor design and 3D stacks.
Tags: FD-SOI, fully-depleted SOI, SOI, Soitec
This entry was posted on Monday, May 28th, 2012 at 11:16 am and is filed under Podcasts Videos Webcasts, Technology Features. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.
FinFETs On SOI
What's changing at the leading edge of Moore's Law and why those changes are so important.
Year-to-year comparisons look dire everywhere but Taiwan, but sequential numbers look much better.
Following a disappointing period in the first quarter of this year, IHS plans to lower its chip forecast to 4.8% for 2013, down from 5.6% in the previous forecast.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.
Enabling 12 technology nodes in 12 years.
Best practices for tackling electrical, physical and manufacturing challenges.
Decreasing time to yield requires planning for what patterns to generate, what data to archive and hot to optimize your test program.
A look at how to reduce custom/AMS design cycle time while improving design quality with on-demand, in-design signoff-quality verification.
Double patterning marks a turning point in terms of lithography, variability and complexity.
A look at the challenges and various solutions using LELE at 20nm, including place and route effects, OPC and mask misalignment and image rounding.