Soitec Touts FD-2D and FD-3D on SOI Wafers
By David Lammers
In an effort to gain a stronger foothold in the coming fully depleted CMOS era, Soitec (Bernin, France) said it is ready to provide silicon-on-insulator (SOI) wafers to both planar (FD-2D) and finFET (FD-3D) customers.
SOI wafers command a price premium over the polished epitaxial silicon wafers used by many microprocessor and SoC vendors. However, Soitec has argued that by using the buried oxide layer intelligently, the number of process steps can be sharply reduced, with about 90 fewer total steps. Shallow trench isolation steps can be largely eliminated, for example. With process simplicity offsetting the approximately $500 cost (less in high volumes) of the SOI wafer, semiconductor companies can actually save 3-10 percent compared with bulk technologies, said Steve Longoria, senior vice president of strategic business development at Soitec.
For finFETs, SOI’s buried oxide layer provides a “thicker BOX, with a pre-defined fin height and isolation at the wafer level,” as well as less leakage, he said. By closely controlling the sub-10nm active top silicon layer to tolerances of 0.5 Angstrom, the FD-2D and FD-3D wafers provide a means of fully depleting the extremely thin channel of carriers.
“Companies are running out of tricks,” Longoria said, noting reports of poor yields at the 28nm bulk CMOS generation and “a widespread feeling that at the 20nm node, bulk may not be worth doing.”
AMD, IBM, and Freescale have been among the largest-volume users of SOI wafers, with STMicroelectronics and ST-Ericsson recently announcing that they will pursue FD-SOI for the 28nm smartphone processors which ST-E sells. However, AMD executives have said publicly that they do not plan to use SOI technology for any 28nm products. The forthcoming AMD Trinity processor is based on the same 32nm SOI process which the current-selling Llano processors is manufactured on.
Longoria said Soitec continues to work closely with AMD on its technology roadmap. Some foundries beyond STMicro are considering a move to a fully depleted planar SOI process rather than moving quickly to 20nm, the FD-2D path, while other companies are considering an FD-3D process with “an accelerated roadmap,” he said.
April 16th, 2012 at 12:55 pm
Is this a SOITEC and ST effort only, is the rest of the support infrastructure involved. (IBM, foudry, EDA guys etc?)
April 27th, 2012 at 10:58 am
ST says there’s no particular impact to design flow/EDA, beyond extraction deck and SPICE models, which are available. They summarized their 28nm FD-SOI for ASN — see http://www.advancedsubstratenews.com/2012/04/st-white-paper-excerpts-planar-fully-depleted-silicon-technology-to-design-competitive-soc-at-28nm-and-beyond/. Or you can get the whole white paper from the SOI Consortium website: http://www.soiconsortium.org/link-812.php. ST’s fabbing for STE’s 28nm FD-SOI NovaThor, which tapes out in Q3. Also recommend ST-E’s blog on all this — see http://blog.stericsson.com/blog/2012/04/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-part-1/
April 30th, 2012 at 10:37 am
To answer the question directly: This is absolutely NOT a SOITEC and ST only effort.
• At the Fully Depleted substrate level, there are multiple suppliers, SOITEC, MEMC and SEH with the technical capability, experience and scale to supply the volume requirements in the low power markets.
• The design portability bar for Fully Depleted SOI is much lower than Bulk and finFETs. This is because of the very well behaved transistor characteristics at low voltages and nearly ideal analog performance. There are no EDA or restrictive DFM rules on the design migration. Bottom line, the EDA support is inherent.
• From the very key mobile IP suppler, ARM , I would suggest you take a look at the earning reports interview from Warren East, CEO of ARM, when asked:
- How does ARM see FD-SOI?
– “We think it’s pretty good,” replies East, “we think SOI and fully depleted SOI are great approaches. We take note of it. They seem to be getting some excellent numbers.”
http://www.electronicsweekly.com/Articles/25/04/2012/53509/arm-expects-strong-q3.htm
— I would like to also note that ARM has done key benchmarking of FD SOI.
• While we are not in position to make announcements for any of the foundries, the foundry partners in the JDA have full access to Fully Depleted SOI and I personally believe that as the business demands increase (first product introduction has already been announced by STE), the foundry support is well positioned to respond rapidly.
• Finally, the R&D pipeline is very active within the JDA and Leti focused on effectively scaling Fully Depleted SOI to 14 nm and beyond.
The key point and upshot is that this is a comprehensive multi- company effort representing the entire Consortium ecosystem.
Horacio Mendez
Executive Director
SOI Industry Consortium