Panel: Let’s Rally Around 3D Chip Standards
By Mark LaPedus
The IC industry must embrace — and become more active — in the standards process to help jumpstart the 2.5D/3D chip era, according to a panel at the recent Mentor Graphics User Group Meeting in Santa Clara, Calif.
One of the members of the panel also challenged conventional wisdom, saying that 2.5D devices based on interposers could be more difficult to develop than true stacked 3D chips. If anything, 2.5D chips might be more difficult to devise and commercialize, according to one panelist.
Clearly, it’s taking longer than expected for 2.5D/3D chips based on through-silicon vias (TSVs) to enter mass production. Supply chain and technology issues are among the challenges. The temporary bonding/debonding steps and test are among the stumbling blocks on the manufacturing front.
The bottom line is cost. Before the technology is viable, “3D must hit a certain price point,” said Riko Radojcic, director of engineering for Qualcomm Inc., during the panel at the event. “We will start seeing products at the high-end,” Radojcic said, but the devices “will trickle down” to more mainstream applications once the costs drop.
So, the market will evolve in steps, in which 2.5D chips will appear first, followed by stacked 3D devices, said Matthew Hogan, Calibre marketing engineer at Mentor. “2.5D will go on for a long time as a placeholder,” Hogan said during the panel.
Qualcomm’s Radojcic believes the development of 2.5D chips could be more challenging than previously thought, saying the technology “has more difficult problems to solve.” For example, these devices include the silicon interposer. “How do you test it?” he asked.
“Interposers are very large,” said Ruben Fuentes, senior director in the Technology and Platform Development group at Amkor Technology Inc., during the panel. “They are very complex.”
Not all is lost and there are solutions to the 2.5D/3D chip era. For example, researchers are working on the design and thermal issues in the arena. Fab tool vendors are working on the bonding/debonding, test and related manufacturing issues. On the EDA side, there is also progress. For example, Qualcomm and Mentor are working on the necessary tools in the arena, such as a stress checker, chip-level stress simulation, package-level simulation and a stress hot-spot checker.
Still, there is yet another missing and overlooked piece of the puzzle: standards. “We need more participation” on the standards front, Radojcic said. “It’s a must or (the 2.5D/3D chip era) isn’t going to happen.”
In fact, there are a multitude of standards being hammered out for 2.5D/3D chip designs. Some have already been ratified. Several more are still on the drawing board. Here’s a look at five key 3D standards — and commentary based on recent interviews:
3D Test and IEEE 1838
In some circles, test is the biggest challenge to enable 2.5D/3D chips. There is no silver bullet. Chip makers will require a range of technologies and strategies, such as boundary scan, built-in-self-test (BIST), test compression and others, said Walden Rhines, chairman and CEO of Mentor, during a keynote at the user event.
To enable test in 3D designs, the 3D Test Working Group within the IEEE is hammering out a proposed standard called IEEE 1838. The proposed standard hopes to define the architecture and description language for the “test access” architecture within a 3D device. The test access architecture is critical, because it can be used to test and ensure the quality of a 3D device during the IC flow.
IEEE 1838 is expected to be based on one of two technologies. The group may standardize the technology based on the IEEE 1149.1 boundary scan standard or the IEEE 1500 embedded core architecture scheme. It is unlikely that the group will endorse both technologies.
Besides 1838, there are other key test technologies. For example, IEEE P1687 is also a major enabler for 3D designs, said Geir Eide, product marketing manager for Silicon Test Solutions at Mentor. IEEE P1687 aims at providing a standardized interface between the 1149.1 test access port (TAP) and on-chip embedded test, debug and monitoring logic, such as scan-chains and temperature sensors.
The three standards can be used in a “mix and match” format to test a 2.5D/3D device. Now, the real trick is the ability to develop a standard to support heterogeneous die from multiple vendors. That’s where 1838 comes into play.
Design and Exchange Formats
Qualcomm’s Radojcic is seeking more participation in standards, including one critical area: design and exchange formats. Chartered by the Si2, the Open3D Technical Advisory Board (TAB) hopes to define flows for the design of 3D chips. The Open3D TAB will define standard interfaces to enable the transfer and storage of design and model data throughout interoperable 3D design flows.
The group hopes to devise standards for a list of issues: thermal design, power design, physical design, electrical design and stress design. It hopes to define standards for model formats. The eventual goal is to “select an expert to propose and champion a given exchange format,” he said at last year’s Design Automation Conference.
Wide I/O
In December, standards body JEDEC passed and ratified the Wide I/O memory standard, dubbed “JESD229: WIDE I/O SINGLE DATA RATE (WIDE I/O SDR).” This standard defines the Wide I/O specification, including features, functionality, packages and micropillar signal assignments. It covers 1- through 32-Gbit SDRAM devices, with 4 x 128 wide channels using direct chip-to-chip attach methods.
Diagram of Wide I/O device (Source: JEDEC)
Many agree that there is a need for Wide I/O DRAM technology on the mobile front. Current mobile DRAMs require more bandwidth for current and future smartphones and tablets. But Wide I/O DRAMs for mobile applications could appear later than sooner.
Today, portable systems are using mobile DRAMs based on two interfaces. This includes the LPDDR2 interface technology and a low-power version of desktop DDR3. Following those schemes, the next mobile DRAM technology on the roadmap is called LPDDR3.
Elpida, Hynix, Micron and Samsung have all announced LPDDR3-based mobile DRAMs. But right now, there is only one application processor/baseband vendor that supports LPDDR3, said Mueez Deen, director of mobile DRAM marketing at Samsung Semiconductor Inc.
Others will support LPDDR3 in the future. So, mobile DRAMs based on LPDDR3 are not expected to move into mass production until 2013, Deen said. “There is a lot of design activity going on now,” he said, “but a lot of our partners are not ready.”
Source: JEDEC
After LPDDR3, the industry was immediately expected to make a jump to Wide I/O, according to a roadmap from JEDEC. Using stacking techniques and TSVs, Wide I/O mobile DRAM is expected to improve the bandwidth, latency and power over today’s LPDDR technology.
However, there are some fears that Wide I/O technology could be too expensive — or too costly to make — at least in the short term. The proposed chip-to-chip attach methods are slow and expensive. This is prompting the industry to talk about the need for a new, evolutionary interface: LPDDR4. In other words, the industry could adopt mobile DRAMs based on LPDDR4 after LPDDR3, thereby pushing out Wide I/O.
Low-Power Wide I/O and 3D-based DDR3/DDR4
JEDEC is also quietly devising another standard, entitled “3D Memory Stack for DDR3 and DDR4 using TSV.” This standard, which is on the drawing board, defines a scheme for stacking current and future DRAMs based on conventional DDR3 and DDR4 interface technology. This, in turn, could also delay the need for Wide I/O, especially in high-end servers.
Wide I/O, however, could also find a home in high-end servers as well. Within JEDEC, there is another standard is entitled, “Wide I/O DRAM Memory Specification – Low Power DRAM: Generation 2.” This low-power technology is a follow-on to JESD229. The standards debate has just started for this scheme.
This Wide I/O effort could be targeted for mobile and server applications. Like mobile systems, servers are in need of a new technology. Today’s DRAMs are power hungry devices that are becoming harder to scale and are running out of bandwidth. Wide I/O addresses some of those problems, but there are cost issues with the technology. And chip-to-chip attach methods are slow and expensive — the industry has been begging for a cheaper wafer-to-wafer attach technique.
For this reason and others, Micron Technology Inc. is lukewarm about Wide I/O. Instead, Micron is developing the Hybrid Memory Cube (HMC), a rival 3D DRAM technology. Rival Samsung Electronics Co. Ltd., has Wide I/O and HMC on its roadmap. Samsung and others are also looking to develop DRAMs based on the evolutionary DDR4 interface, which is due out in 2014.
DDR4, HMC and Wide I/O address several needs, including a power crisis in today’s datacenters. Datacenter energy is doubling every five years, according to Samsung. In total, datacenters consume 195 terawatt hours (TWh) of power, which is more power than the nations of Austria and Argentina combined, according to analysts.
Before the market jumps on these newfangled memory technologies to help solve the datacenter power crisis, server vendors must still use today’s DRAMs based on DDR3 and DDR2 for some time to come. And DRAM vendors are working hard to address the power concerns.
Today, the mainstream server DRAMs are 30nm-class, 1.35V products based on DDR3, which have a 67 percent power savings over 50nm-class, 1.5V products, said Sylvie Kadivar, director of DRAM strategic marketing at Samsung. Expanding its DDR3 lines, Samsung recently rolled out a 20nm-class, 1.25V DRAM, which should save more power. “The market is hungry for higher-density, lower-power devices,” she said.
