IBM, GlobalFoundries, Samsung Tip finFETs at 14nm
By Mark LaPedus
IBM’s technology alliance members — IBM Corp., GlobalFoundries Inc. and Samsung Electronics Co. Ltd. — have officially planted their stakes in the ground. The companies have announced their process roadmaps following the 20nm node, saying that they will move to finFET technology at 14nm.
The moves were somewhat expected, as the three companies for some time have dropped hints about implementing finFETs at 14nm. The announcement also follows rival Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), which recently stated that it will move to finFETs at 14nm. Intel Corp. has already migrated to finFETs at 22nm, it was noted.
During a presentation at the Common Platform Technology Forum 2012 in Santa Clara, Calif. on Wednesday (March 14), IBM said it has demonstrated a finFET SRAM cell at 0.04-square-mm. At 14nm, IBM said it will focus on two technologies: fully depleted finFETs and fully depleted silicon on insulator (FD-SOI), of which it refers to as extremely thin SOI, or ETSOI.
In contrast, GlobalFoundries and Samsung will implement finFETs based on bulk technology at 14nm. Initial parts or test chips from those companies are not expected to appear until late 2014, meaning IBM and its partners are roughly two to three years behind Intel in the finFET race.
IBM, GlobalFoundries and Samsung did not provide the exact details or specifications for their finFET structure, but they emphasized the importance of the technology. “The next decade is 3D,” said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, during a keynote presentation at the event. “We believe 3D will take us through the next decade.”
By 3D, Patton was referring to two technologies. Technically, finFETs are based on a 3D transistor structure. And hedging their bets in the industry, chip makers are also working on 3D stacked devices based on through-silicon via (TSV) technology.
Next-generation transistor race heats up
For decades, the industry has been making use of a two-dimensional planar transistor structure for mainstream chips. But as a device scales, planar transistors begin to experience undesirable short-channel effects, such as off-state leakage current.
There are other problems with the planar transistor in scaling, meaning the industry must embrace a new transistor structure. The candidates include finFETs, fully depleted SOI, multi-gate transistors and others. In a finFET, the channel is surrounded by several gates. This allows for a more effective way to suppress off-state leakage current.
Last year, Intel rolled out a finFET structure, of which it calls tri-gate. The chip giant, which first disclosed the technology in 2002, has put tri-gate transistor into production for its processor designs at the 22nm node. Intel claims that its tri-gate transistors provide up to 37 percent performance increase at low voltage versus Intel’s 32nm planar transistors.
In Intel’s tri-gate structure, the traditional “flat” two-dimensional planar gate is replaced with a thin 3D silicon fin that rises up vertically from the silicon substrate. Control of current is accomplished by implementing a gate on each of the three sides of the fin — two on each side and one across the top — rather than just one on top, as is the case with the 2D planar transistor, according to Intel.
The additional control enables as much transistor current flowing as possible when the transistor is in the “on” state (for performance), and as close to zero as possible when it is in the “off” state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance), according to Intel.
The finFET structures from Intel and the IBM camp “look very similar,” said Nathan Brookwood, principal of Insight64. Intel’s tri-gate has “prismatic gate structures,” while IBM has made a point of “how they rounded the corners” for their rival finFET structures, Brookwood said.
IBM camp talks finFETs
GlobalFoundries outlines finFET structure at IEDM (Source: Company)
GlobalFoundries tips bulk finFETs at IEDM (Source: Company)
During presentations at this week’s Common Platform Technology Forum, IBM, GlobalFoundries and Samsung made it official. The companies also attempted to ease the angst among potential customers in terms of moving from conventional planar transistors to complex finFET structures at 14nm.
Many observers worry that the foundries could struggle to ramp up finFETs in a cost-effective and timely fashion. Even in the planar era, the foundries have struggled to move from one node to another. In the latest example, foundries are still wrestling with the shift to high-k at 28nm.
The foundries are still in the early stages of the 28nm node, which has proved to be more challenging than previously thought. “They also still have (to face the challenges) at 20nm before they go to finFETs,” said Joanne Itow, an analyst with Semico Research Corp.
So, in many ways, IBM, GlobalFoundries and Samsung have jumped the gun and pre-announced their finFET plans. But Itow said that the trio wanted to get the finFET news out and let customers know “they are in it for the long haul.”
Firms tip process roadmaps
Meanwhile, during the Common Platform event, the three entities provided a glimpse of their process roadmaps. IBM will continue to use SOI technology as it moves to finFETs at the 14nm node, said IBM’s Patton. The Fishkill Alliance will pursue bulk finFETs at the 14nm node, but IBM sees advantages to SOI for its server processors and ASICs, Patton said.
For its part, GlobalFoundries is ramping up its 32nm and 28nm processes, based on a gate-first high-k approach. At 20nm, the foundry vendor will move to a gate-last high-k scheme. The company is expected to move into risk production for the 20nm node in the second half of 2012, followed by volume production in 2013.
Then, at 14nm, the company will move away from the planar structure and embrace finFETs. “Planar is dead,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries, during a presentation. “Gate oxide has reached its limits.”
GlobalFoundries plans to have test chips at 14nm in late 2014, said Michael Noonen, senior vice president of worldwide sales and marketing for the foundry vendor. The devices will be built within its new 300mm fab in New York, he said.
Samsung will make a similar shift to finFETs at 14nm. Jong Shik Yoon, senior vice president of semiconductor R&D at Samsung, said the company was looking at bringing up finFETs in late 2014. He explained that finFETs provide various benefits at 14nm. FinFETs provide “better mobility” and improves “short channel effects,” as compared to planar structures, he said.
Jung Yun Choi, principal engineer within Samsung’s Systems LSI Business, listed the various challenges with finFETs, such as the ability to control the transistor widths and an increase in process variations. Another stumbling block is to provide multiple threshold voltage options. Samsung would like to develop a multi-threshold cell library, which offers similar options as its 28nm and 20nm processes. But, Choi said, “this is a challenge.”
Tags: GlobalFoundries, IBM, Intel, Samsung, TSMC