By Mark LaPedus, SemiMD senior editor

Samsung Electronics Co. Ltd. wants extreme ultraviolet (EUV) lithography to scale DRAM and NAND flash, although the company has reset its roadmap for the patterning technology.

The company hoped to obtain an EUV tool with a 250 Watt power source by the end of last year, said U-In Chung, senior vice president of the Materials and Device Research Center for Samsung.

Now, the South Korean memory giant has revamped its roadmap amid delays with the power sources and other issues. In its latest roadmap, Samsung wants an EUV tool with a 166 Watt source by the first half of 2013 and a 250 Watt source by the second half of next year, Chung said. “The sooner the better,” he said at the SPIE Advanced Lithography conference in San Jose, Calif.

Because of the lack of adequate power sources, EUV throughputs are running about 4 wafers an hour right now. The industry requires around 100 wafer an hour throughputs to make EUV economically viable in production fabs.

To get their respective feet wet for EUV, Intel, Samsung, TSMC and others procured ASML’s NXE:3100, a pre-production EUV tool. In the second half of 2012 and into 2013, GlobalFoundries, Intel, TSMC, Samsung and others are expected to receive ASML’s NXE:3300B, a full-blown production EUV tool.

With EUV — paired with a double-patterning technique or directed self-assembly (DSA) technology — Samsung believes it can scale DRAM and NAND to 10nm and beyond, he said.

At present, Elpida, Hynix and Samsung are shipping 20nm-class DRAMs. Some believe that DRAM will hit the scaling wall at the 1xnm. In DRAMs, there are several scaling challenges, namely shrinking the capacitor. “To solve the capacitor challenges, we need a breakthrough in a cell array transistor (CAT),” he said.

For years, DRAM makers used a planar structure. In 40nm-class DRAMs, Samsung moved to what it called a recess-channel CAT. Then, at 20nm, the company is said to have embraced a buried-gate CAT. Below 20nm, it is talking about using a vertical CAT.

Today, Samsung is using 193nm immersion to make its 20nm-class DRAMs. To move beyond the 1xnm node — in 2015 or sooner — “EUV is the first option,” Chung said. Over time, Samsung envisions using EUV plus a double-patterning. This could be conventional double-patterning or DSA.

In NAND, some predict the floating gate architecture will hit the wall at 14nm. Samsung, Toshiba and others are looking at vertical NAND flash. Samsung calls its technology TCAT or terabit cell array transistor.

When will 3D NAND appear in the market? “It really depends on how far floating gate NAND can scale, but 3D NAND is two to three years away with most implementations using charge trapping technology,” said Greg Wong, an analyst with Forward Insights.

Jim Handy, an analyst with Objective-Analysis, said: “Toshiba is talking about producing its BiCS next year, but I haven’t heard anything from Samsung, who’s the only other company making a BiCS look-alike.  SanDisk will probably be doing something with its Matrix technology. SanDisk acquired Matrix in maybe 2004.  That’s vertical as well.  They call it 3D.”

Tags: Elpida, Samsung, Toshiba

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