By Mark LaPedus, SemiMD senior editor

During the LithoVision 2012 technology conference in San Jose, Calif. on Sunday (Feb. 12), Intel Corp. reiterated its plans to insert extreme ultraviolet (EUV) lithography as its first choice for the 10nm node, but the company is keeping its options open.

The chip giant is devising a back-up plan. If EUV remains late to the party, Intel said it could shift gears and implement 193nm immersion — bolstered by complex multi-pattering schemes at its 10nm node. In addition, Intel also disclosed it will install an EUV pilot line by the end of 2012, which was previously announced by the company.

“Right now, we’re proceeding in parallel” with both EUV and multi-patterning, said Sam Sivakumar, director of lithography in Intel’s Portland Technology Development Group in Oregon. “When the time comes, we will make a decision.”

Intel is still counting on inserting EUV at its 10nm node, but there are still several major issues with the power sources, mask infrastructure and other technologies. Other challenges include edge-placement accuracy and control of edge placement error.

“EUV has a lot of promise,” Sivakumar said. But the power sources “have a long ways to go,”  and the EUV mask infrastructure faces “a big challenge.”

“Our focus is to bring EUV into production.  A lot of (the technical issues) are not under Intel’s control,” he told SemiMD after his presentation at the event, which was sponsored by Nikon Corp. The annual event kicks off this week’s SPIE Advanced Lithography conference in San Jose.

Intel’s roadmap

Sivakumar outlined Intel’s lithography roadmap during his presentation, noting that Intel inserted its initial 193nm immersion scanners at its 32nm node. Nikon Corp. was the sole supplier of 193nm immersion scanners for the “critical layers” at Intel’s 32nm node.

At 22nm, Intel rolled out its finFET transistor technology, which has just moved into production. The company is still using 193nm immersion scanners for the “critical layers” at that node. The critical layers are reportedly being split between ASML Holding NV and Nikon.

Then, at 14nm, Intel will continue to use 193nm immersion for the critical layers, Sivakumar said.  And it will implement an undisclosed type of “pitch-halving” — or double patterning — technology at that node, he said.  Intel’s 14nm process is expected to be ready by 2013.

Like 20nm, Intel will use both ASML and Nikon for the critical layers, sources said. Nikon recently announced that its new NSR-S621D 193nm immersion scanner began shipping to IC manufacturers in January “for the most demanding immersion double patterning layers.” Nikon shipped the tools to its largest customer, reportedly for Intel’s 14nm node, sources said. Intel did not comment.

The S621D makes use of Nikon’s Streamlign Platform. The combination of Stream Alignment and Five-Eye FIA systems enables a throughput of 200 wafers per hour (125 exposure shots/wafer). In addition, the Bird’s Eye Control system uses interferometers in conjunction with encoders to deliver overlay accuracy ≤ 2 nm with optimal stability.

Intel does not plan to use EUV for the 14nm node. But to get the ball rolling, the company plans to install an EUV pilot line by the end of 2012 and into 2013, he said. In that line, the company is expected to install ASML’s  NXE:3100, a pre-production, 13.5nm EUV tool.

Then, at 10nm, the company reiterated its previous roadmap. At that node, which is due out in 2015, Intel is looking at two options. The first option is EUV for the critical layers. It is still unclear if EUV will be ready for insertion at that node.  “We are not in a position to make a decision today with great detail,” Sivakumar said. Much of this depends upon the cost, power sources, reticle infrastructure, and other challenges, he said.

Intel has already obtained ASML’s NXE:3100, and is working with the tool in its R&D lab. Intel is also a customer for ASML’s NXE:3300B, its first full-blown, production EUV tool.  ASML is expected to ship the tool to undisclosed customers in the second half of 2012. Asked if EUV will be ready at least by 2013, Sivakumar said: “It’s hard to say. We will have to see.”

If EUV is not ready, the second option is to use 193nm immersion with multi-patterning, which includes double-patterning, quadruple patterning and complementary patterning. No decision has been made.

In one scenario, Intel could use pitch quartering — or quadruple  patterning. In another option, Intel could implement what it calls “complementary patterning.”

IC vendors have traditionally used two-dimensional layouts, but there are scaling and related issues with this technology. Instead, the industry is looking at one-dimensional layouts based on gridded design rules. Intel uses unidirectional, gridded layouts at 45-nm. In this approach, there are two lithography steps — grating and line cut — to pattern designs. At 20nm and above, 193nm immersion tools can handle both steps.

In this approach at 14nm, a 193nm immersion tool can perform the traditional grating step. Then, to perform the next step — the finer-line cut scheme — the industry is looking at EUV, maskless e-beam, and even 193nm immersion.

In one possible scenario, Intel could implement 10nm with an expensive “five mask solution.” In the grating step, one mask would make use of 193nm immersion. For the line cut step, the other four masks would also use 193nm immersion. However, in a less expensive scenario, Intel could implement a two-mask solution. The first mask would implement a grating process using 193nm immersion. The cut step for the second mask would be implemented using EUV.

There is also an option to use multi-beam e-beam tools at the cut process as well. “That is an option,” he said. “As the tools mature, that will be in the mix.”

Tags: ASML, Intel, Nikon

This entry was posted on Sunday, February 12th, 2012 at 8:04 pm and is filed under News Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.