By Mark LaPedus, SemiMD senior editor

For years, electron-beam tools have been used to write the critical layers for a photomask, but these machines have been considered too slow and a bottleneck in mask production.

And as the IC industry reluctantly moves into the double – or multiple – patterning era, the e-beam could fall further behind the curve, possibly causing a spike in photomask costs and product delays.

The new e-beams are running at the same speeds – or slightly faster – than before, but they must now process more photomask layers. In multiple patterning, mask makers could see their capital costs soar, as they may end up buying “more mask writers” – perhaps twice as many than before – to maintain the curve and keep up in photomask production, warned G. Dan Hutcheson, CEO of VLSI Research.

“The e-beams are getting faster,” Hutcheson said. “But historically, e-beams have not been able to keep up.”

Not long ago, an e-beam sold for about $10 million per unit. Now, they range somewhere from $20 million to below $50 million each, depending on the configuration.

Tired of getting the brunt of the criticism in mask shops, the two major e-beam vendors – JEOL Ltd. and NuFlare Technology Inc. – are fighting back. They have separately begun shipping their latest e-beams for developing next-generation photomasks, especially for the multiple patterning era.

Japan’s JEOL is shipping the JBX-3200MB, a 50-KeV tool that is faster than previous versions. Rival and market leader NuFlare is delivering the EBM-8000. NuFlare said it is scrambling to keep up with soaring demand for the EBM-8000, causing longer than expected lead times despite a downturn in the equipment business.

Meanwhile, the industry is rolling out various design-for-manufacturing (DFM) tools to speed up the e-beam. And thankfully, mask costs are not soaring out of control.

At one time, there were fears that a mask-set would run a whopping $10 million at the 22nm node, said Walden Rhines, chairman and chief executive of Mentor Graphics Corp. The reality is that photomask costs are moving more at a “linear” path, Rhines said at a recent event.

The early 45nm “mask sets” hit the dreaded $1 million barrier, but ASPs have fallen as these reticles moved into volume production, according to experts. The initial 28nm “mask sets” are expected to be around $2 million, but ASPs will drop over time. And a 22/20nm mask could be around $4 million in the beginning.

No mask holiday

Up until the mid-1990s, chip feature sizes were larger than lithography wavelengths, thereby making photomask production a relatively straightforward process. Then, in the late 1990s, delays with 193nm wavelength lithography forced the industry to extend 248nm technology beyond what was once considered possible, prompting the need for complex resolution enhancements techniques (RETs).

At 45nm, chip makers began to implement some double pattering techniques, such as line cutting and spacer. Beyond 45nm, chip makers may be forced to use more complex double-patterning methods, such litho-etch-litho-etch, litho-freeze-litho-etch, sidewall spacer, among others.

Today, the problems are even more acute. Extreme ultraviolet (EUV) lithography is late, forcing the industry to extend 193nm lithography, thereby adding more complexity to the mask. For example, Toshiba Corp. is pushing 193nm immersion down to 19nm for NAND, thanks to self-aligned double patterning (SADP). In logic, Intel Corp. has said it plans to extend 193nm immersion down to 14nm, with the help of multiple patterning. Intel hopes EUV will be ready at 10nm.

As a result, photomask makers must develop more complex masks. The average write time per mask layer is around 3.3 hours right now, a decrease from those in 2010, according to a survey from Sematech. But the average maximum write time per layer for a mask is 33.2 hours right now, up 15 percent over 2010, according to the survey.

A mask-set for microprocessor has about 40 to 60 layers. Some 20 to 30 percent or so of those layers are critical, and must be processed via e-beam. The other layers are processed via laser pattern generators.

In any case, e-beams continue to remain one step behind Moore’s Law. Average e-beam write times have leveled off for many devices, although they are soaring for complex chips. And tool cost-of-ownership (COO) is also expected to rise.

“I don’t think that we have a crisis situation,” said Christopher Progler, vice president and chief technology officer at Photronics Inc., a photomask maker. “On the other hand, the trends are not going in the right direction.”

Current single-beam, reticle writing e-beams are “sufficient for 22nm,” Progler said. Beyond 22nm, “you can make a photomask (using today’s e-beams), but it “gets shaky” in terms of write times.

There is a silver lining. In multi-pattering, photomask makers are processing more mask layers than before, thereby boosting their bottom lines and average selling prices (ASPs).

On the other hand, there are issues looming on the horizon. In traditional single exposure processing, an IC maker uses one mask. In doubling patterning, an IC maker uses two separate masks to design a device, which boosts production costs. (Triple-pattering will require three masks and so on.)

In double patterning (two separate mask sets), for example, photomask makers could process a mask in two basic ways: They could write the layers in sequential steps or could simply buy more mask writers.

(In one possible scenario, let’s say a mask writer takes 10 hours to process one layer in the first mask set. Then, after that step is completed, the same mask writer is moved to the second mask set. Then, the e-beam takes 10 more hours to process one layer in the second mask set – for an aggregate total of 20 hours in terms of write times.

To speed up the process, a mask maker can simultaneously utilize two e-beams to process each layer. In this scenario, the total write times have been reduced from 20 hours to 10 hours.)

Progler said it’s more complex in triple-, quadruple- and quintuple-pattering. The ideal scenario is to process the reticles at the same time. But in some cases, “you must stagger” the reticle flow and process the wafers using various double-patterning schemes, he said.

The bottom line is that photomask shops “will need more mask writers to produce a mask,” Progler said. “This will change how mask lines are managed.”

The problem within the mask shop is resources. In some cases, a mask shop will have two e-beams available to process the layers simultaneously. In other cases, two e-beams are not available, which slows production and time to market.

“The concern is cost,” said Steffen Schulze, a photomask veteran and director of marketing for Calibre MDP and platform applications at Mentor. “The question is can I afford two mask writers? And can I (produce the required masks) in time?”

Wanted: EUV

To attack this problem, the industry is begging for EUV. “EUV will give (photomask makers) some relief because it will bring everything back” to single exposure, Schulze said. In EUV, “OPC looks less complex.”

But EUV is late to the party. On another front, KLA-Tencor and Mapper have been developing multi-beam tools for maskless lithography. Sematech has been looking to fund the development of a fast multi-beam tool for reticle writing.

But for now, mask makers must resort to the e-beam. In multi-pattering, “the requirements are challenging,” said Hirokazu Yamada, U.S. national account manager for electron beam lithography at JEOL. One of the “issues is throughput,” Yamada said.

JEOL is shipping the JBX-3200MB, which is geared for photomask production down to 14nm. Rival NuFlare has recently begun shipping the EBM-8000, a 50-KeV tool said to have a current density of 400A/cm2. The maximum shot size is 350nm square.

The EBM-8000 is targeted for the 22nm half-pitch memory and 16nm logic. It is a “vector scan, variable shaped beam tool with a continuously moving stage,’’ according to an official at NuFlare.

There are various design-for-manufacturing (DFM) efforts to boost e-beam throughputs by reducing shot counts. For example, Mentor’s One Calibre MaskOPT is said to reduce mask costs and mask writing times by lowering the total shot count through advanced pre-processing of the fractured data.

Another tool vendor, D2S Inc., recently introduced a mask-wafer double simulation tool. Deploying hardware acceleration, TrueMask DS can produce a double simulation of the mask and wafer for 5×5 micron on wafer areas at interactive speeds, said Aki Fujimura, CEO of D2S.

At the recent Bacus photomask conference, DS2 and GlobalFoundries Inc. presented a paper on a model based mask data preparation (MB-MDP) technique. Conventional mask data preparation attempts to “Manhattanize” the shapes using only rectangular variable shaped-beam (VSB) shots.

In contrast, MB-MDP simulates e-beam blur and mask processing effects generating VSB shots which print the desired mask shapes. The effectiveness of MB-MDP is verified on 20nm via SRAM, according to D2S and GlobalFoundries.

“Overlapping shots created by MB-MDP enable lowered shot count (and therefore faster write-times) while simultaneously maintaining or improving lithography process window on the wafer. In addition, MB-MDP can simulate the effects of shots to produce the OPC-desired contour on the mask plane,” according to the paper from D2S and GlobalFoundries.

Tags: E-beam, Multi-Patterning Era

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