Planar versus FinFET Debate Continues at GTC 2011
Technologists at the GlobalFoundries Technology Conference said planar, rather than finFET, transistors are the best fit for foundry customers at the 20nm technology generation.
Since early May, when Intel announced its decision to adopt a vertical tri-gate transistor at the 20nm generation, analysts have said that leading SoC vendors are pushing their foundry partners to come up with a finFET technology as soon as possible to match the performance and power claims made by Intel. Some have speculated that TSMC, which has announced that finFETs are on its roadmap for the 14nm node, might offer a finFET technology at the 20nm node to certain customers. And the tensions between Apple and Samsung Electronics have added fuel to speculation that Apple might turn to Intel and its tri-gate technology for SoC foundry services.
Gregg Bartlett
At the GlobalFoundries event Tuesday morning (Aug. 30), Gregg Bartlett, senior vice president of technology and research and development, said GlobalFoundries has plans to adopt finFETs at the 14nm node. As part of the Fishkill Joint Development Alliance, the GlobalFoundries technology team has been developing finFETs “for many years,” he said. “I am very confident that we are moving to finFETs at 14 nanometers, but at 20nm we will use a planar device. However, we are not blind to the advantages of a multi-gate device,” Bartlett said.
For low-power SoCs “3D is not the only way to go,” Bartlett said, acknowledging that Soitec and its SOI technology development partners have developed a fully depleted thin body SOI technology that “deserves due consideration at 14 nanometers.”
At a luncheon for press and analysts, the FinFET versus planar debate continued. Bartlett said the nominal operating voltage for the company’s 20nm bulk planar transistor is 0.9V, which he said can be adjusted for certain applications, and which meets the needs of the foundry’s customer base. The 28nm technology has a nominal operating voltage (Vnom) of 1.0 Volt. Intel, as well as the SOI Consortium, have said their approaches can support operating voltages in the 0.7V – 0.8V range, though they have not been specific on the topic.
Bartlett said a 0.9V 20nm bulk planar transistor would be 35 percent faster at the same leakage current. “Given our schedule, we decided it was better to stay with a planar transistor.”
Bartlett cited two challenges with fielding a 3D transistor at the 20nm node. He said “our understanding” is that the Intel tri-gate technology is a single threshold voltage approach, suitable for a microprocessor but not practical for the SoCs that GlobalFoundries must build for multiple customers. Bartlett was challenged on that point by Nathan Brookwood, a microprocessor analyst at Insight 64, who said that Intel’s MPUs in recent years closely resemble SoCs, requiring multiple threshold voltages. Bartlett, who spent 25 years at Motorola and Freescale before joining GlobalFoundries, said the CPU design style and technology approach of Intel is far different than the leading-edge SoC customers which GlobalFoundries is targeting.
Asked to comment on whether Intel’s tri-gate technology is limited in terms of the number of threshold voltage levels, Mark Bohr, director of process architecture, responded: “Intel’s 22nm Tri-Gate transistor technology offers multiple threshold voltages and provides a range of transistors from high performance to ultra-low leakage. Intel has both CPU and SoC versions of our 22nm technology to support a wide range of products.”
Mojy Chian, in charge of the GlobalFoundries design enablement operation, concurred with Bartlett, saying that comparisons between Intel, which he described as a single-product company, and GlobalFoundries is “not an apples to apples comparison,” raising laughter by the press corps about how Apple Inc. might factor into Chian’s point.
Bartlett also said finFETs require very precise manufacturing control of both the fin height and the fin width, which at the 20nm node will go beyond the maturity of the tools, particularly the exposure tools, used by the semiconductor industry. He argued that the cost of manufacturing a finFET-based device during the 20nm generation will not support the needs of the foundry customer base.
“Fin height control is critical. FinFETs are pretty far away from being an SoC technology for low-power applications,” Bartlett said, adding that it “has to do with the immaturity of the (finFET) technology, the lack of control, combined with the needs of the markets we are serving.”
For GlobalFoundries, the “the risk profile versus the benefits calculation make it quite clear” that a bulk planar technology is the way to go.
Chian said GlobalFoundries has developed an early version of its 20nm PDK, as well as the early design flow and test silicon. At 20nm, the foundry will switch from a gate-first high-k/metal gate module to a replacement gate (gate last) approach. The foundry plans its first 20nm multi-project wafer (MPW) shuttle in the fourth quarter of this year, with initial commercial production beginning late in 2012.
“We are ready for early engagements at 20nm now,” Chian said.
