Cleaning Getting Tougher as Transistors Shrink
By David Lammers
Wafer cleaning faces tough technical and environmental challenges, particularly as the size of the gate shrinks and post-etch residues must be removed without material loss, said Soichi Nadahara, a vice president at Dai Nippon Screen (DNS) Semiconductor Equipment Company.
In a keynote speech at the recent Sematech Surface Preparation and Cleaning Conference (SPCC), Nadahara said 6-7 percent of wafer front-end equipment (WFE) spending goes for cleaning equipment. With the introduction of high-k dielectrics, more companies are turning to single-wafer cleaning with a lower thermal budget. “Most of the concern is post-etch cleaning of the gate structure. The very small size of the gate requires selective etching, and there are lots of post-etch materials that have to be cleaned.”
NAND memories have increasingly deep structures, and the tall FinFETs present another set of challenges. “Our industry asks for damage-free cleaning, and that is the toughest thing, to limit the material loss,” Nadahara said.
Particles can be detected down to about 25-28 nm, he said, adding that such small particles often have a surface tension which requires a relatively high capillary force to achieve a high particle removal efficiency (PRE).
Drying presents an ecological challenge. DNS is studying systems which avoid isopropanol (IPA) smog by removing 85 percent of the IPA before it is released into the atmosphere.
Other speakers at SPCC described a variety of cleaning challenges, including ways to reduce cross contamination from Front Opening Unified Pods (FOUPs) to wafers.
Thi-Quynh Nguyen, a researcher STMicroelectronics/CEA-Leti, presented a study of cross-contamination between wafers and FOUPs. Airborne molecular contamination (AMC) is able to cause defects by corroding the copper and aluminum interconnects, and causing a polysilicon crystal growth on the metal surfaces.
FOUPs can serve as a reservoir for contamination, the STMicro/Leti group said.
“Contamination can be outgassed from the wafer, and then from the FOUP to the wafer,” she said. Plastic FOUPs and PODs can trap the contaminants, acting as a reservoir, releasing the contaminants to new wafers.
The STMicro/Leti study found that cross contamination is time dependent. HF contamination in the FOUP does not depend primarily on the storage time after cleaning, but on the wafer storage time of wafers after line etching, she said. Etching steps are ionic contaminant sources.
The group studied the sources of contamination, including volatile acids, bases, and organics. They characterized the molecular contaminants in the FOUPs along the various process flows after the wafers were removed, using several different analytical techniques ranging from IMS (Adixenpod Analyser-APA), bubbling and ionic chromatography, and DIW leaching of the FOUP surfaces.
Nguyen said solutions include storing FOUPs in an N2 atmosphere, dry stripping without CF4, and vacuum purge steps.
Srini Raghavan, a professor at the University of Arizona, presented a study by colleagues at the Department of Materials Science and Engineering of cleaning formulations based on deep eutectic solvents (DES), which could replace traditional organic solvents in BEOL cleaning. The group studied residue removal with a variety of formulations, including choline chloride/urea (CC/U) and choline chloride/malonic acid (CC/MA).
DES formulations are low cost, operate at low vapor pressures, have low toxicity, are water soluble, and readily dissolve metal oxides. “The post-etch residue removal rate is slightly lower in DES than in conventional formulations, but DES systems are more environmentally benign,” Raghavan said.
Martin Knotter, representing a group of researchers at the Regional Quality Center of NXP Semiconductors (Nijmegen, Netherlands), described how fluoride contamination on wafers moves to bond pads, leading to corrosion and wire bond quality issues. Because NXP supplies automotive components, it must adhere to higher quality standards and lower PPM failure rates, he said.
The NXP group set out to determine the maximum allowable surface concentration for fluoride. The team used several analytical techniques, including auger electron spectroscopy (AES), as well as liquid phase extraction ion chromatography (LPE-IC) to examine the whole wafer for fluoride content.
“All fluoride on a patterned wafer will migrate to the bond pads,” Knotter concluded, recommending certain cleaning procedures and a first fluoride specification limit of 2.71016 at/cm².
Tags: DNS, Sematech, Wafer cleaning