EUV Mask Cleaning Presents Economic Challenges
By David Lammers
EUV lithography is forcing the metrology and mask cleaning sectors to investigate new techniques for dealing with particles on the EUV mask blanks and patterned EUV masks, speakers said at the Sematech-organized Surface Preparation and Cleaning Conference (SPCC), held in Austin this week.
Beyond the daunting technical challenges, vendors are raising return-on-investment questions. Because so few semiconductor vendors are likely to use EUV masks, the capital required to develop the cleaning methods and equipment may not pay off, several participants said during the SPCC meeting, attended by about 150 people over two days.
Source: Sematech's David Chan at 2011 SPCC.
Just getting an EUV substrate is expensive. “On the cleaning side, it can cost $100,000 to get one substrate in for testing,” one participant said, adding that “we are struggling with the investment issues.”
Aron Cepler, a Sematech mask cleaning engineer, said the Sematech EUV mask cleaning R&D group acquires “leftover” mask blanks for testing from various sources, including Sematech’s member companies. But getting more than a few of them is difficult and they are used quickly.
The relatively small number of mask vendors, and the high cost of EUV inspection equipment, requires funding from the semiconductor industry in a consortial manner. Sematech manager David Chan gave a brief progress report on the Sematech-led EUV Mask Infrastructure (EMI) consortium, formed to develop EUV mask inspection tools. Sematech in general is moving to 15nm half pitch (HP) and 8 nm HP process technology R&D. “We need defect-free EUV masks, but if you can’t see the defects then you can’t do process development,” Chan said.
One goal is to develop an AIMS mask review tool. “AIMS has a lot of traction, and the collaboration agreement is being finalized,” Chan said, adding that “no production-worthy EUV solution is possible without an AIMS tool, and the long development time (~3 years) makes it a very high priority.”
The EMI consortium also will develop inspection tools for both blank substrates and patterned EUV masks, which will likely require actinic (13.5nm wavelength) solutions at the 16nm node and beyond, beginning in 2013.
Development of advanced pattern inspection “must start ASAP,” Chan said, adding that it could be an actinic solution “or some other capable technology, such as e-beam.”
In addition, Sematech is working on a separate multi-beam mask writer consortium, which he said “is being discussed and getting a lot of traction.”
“The DRAM vendors want to start pilot lines using EUV patterning in 2011,” he said.
EUV mask cleaning and particle removal tools need to remove 18nm particles, in order to satisfy the International Technology Roadmap for Semiconductors (ITRS) contamination goals in support of EUV lithography. However, today’s large-field inspection tools cannot detect particles smaller than 30nm in size, leading the Sematech mask cleaning group to turn to scanning electron microscopy inspection with a small field of view.
Cepler detailed how the Sematech group adjusted the e-beam dose to achieve the best particle removal efficiency (PRE). At a critical e-beam exposure dose, particles become non-removable, depending on particle size and compositions.
Before and after particle removal
He discussed the correlations between carbon contamination and particle adhesion for SiO2 and polystyrene latex (PSL) particles.
Masks were allowed to age for eight days, and the Sematech group found no change over time in the adhesion of SiO2 contaminants, the “PSL mechanism is different,” Cepler said. Also, the group studied EUV masks with a thin 2.5nm ruthenium capping layer and others with a TaNO capping layer. The TaNO absorber required a higher removal force, he said.
The issue was discussed by the SPCC panelists, which included Soichi Nadahara – DNS; Jeff Butterbaugh - FSI; International; Laura Mauer – SSEC; Ian Brown – TEL; Kevin McLaughlin – ATMI; William Gemmill – Avantor; Craig Allen – SACHEM; and Simon Kirk – DuPont/EKC Technology. Joel Barnett, chairman of the SPCC and the Sematech clean technology program manager, moderated the panel.
