By Ed Korczynski

UPDATED

To know what’s happening in lithography for high-volume manufacturing (HVM) the SPIE Advanced Lithography conference and exhibit is the place to be. Presentations at the Nikon Precision and KLA-Tencor customer events the day before provide vital context. On Day 0 of the conference, Intel fellow Sam Sivakumar said EUV is too late for Intel’s 14nm node, and may be too late for the development of 10nm generation design-rules (DR). EUV could still be on time for single-exposure work in 16/14nm nodes at foundries and memory fabs, and many companies may use EUV to cut grid-lines made using 193i tools.

Before the industry can get to high-volume manufacturing (HVM) of commercial ICs in a fab, companies need to lock-in processes in pilot production. Before that, they must have design-rules (DR) set. Intel leads the world in the race to the smallest features, with the 32nm node in HVM, 22nm node now in pilot production, and 14nm node design rules already set for HVM in 2013. An Intel 10nm node in HVM would follow in 2015.

At Nikon’s LithoVision workshop, Sam Sivakumar, Intel fellow (figure), explained that the DR set for 14nm used 193nm-immersion double-patterning (193i-DP), and that for the 10nm node—featuring 20nm actual line width, and 40nm pitch—design rules will be frozen early in 2013. “So production EUV tools will be delivered too late to meet the need to develop DR for the 10nm node, though Intel remains committed to going into production with EUV” said Sivakumar. Regarding the possibility of re-insertion, it is possible but only after surmounting a barrier. “We’d need to reset the DR for EUV,” elaborated Sivakumar, “because it doesn’t make sense to use DR developed for 193i with EUV. The key point is that DR flexibility needs to be built in, so that we can smoothly insert EUV and derive maximum benefit.”

[UPDATE 3/1: In an evening panel session, Sivakumar asserted Intel's official position as, “Our primary plan is to use EUV for 10nm, but we need ArF double-patterning as a backup.” Intel will have a pre-production 3100 tool this year, and likely will want a production 3300 whenever available. “When going to immersion, it took us well over a year to be able to get the defectivity levels down to that of dry. I'm hoping that all the learnings that will come from the 3100 will map to the 3300.”]

[UPDATE 3/2: In an exclusive followup meeting with SemiMD, Sivakumar explained that Intel has long planned to do 14nm node pilot using EUV, and should be on schedule with the shipment of the 3100 to meet plans. Many of the learnings to be found during pilot, such as SMO-dependencies, should map to HVM so there is confidence that the technology will be capable of ramping into 10nm node production.]

Discussing lithographic CoO for 22nm node patterning, Hidetami Yaegashi of TEL showed data that 193i double-patterning (193i-DP) should be less than EUV running at 150 wph and perhaps only 50% of EUV running at 60 wph.

Any delays in EUV seem to be due to the tough science and engineering challenges associated with sources and resists, while stepper OEMs have been meeting their development commitments.

Leading off Day 1, Luc Van den hove, IMEC president and CEO, announced in his plenary keynote that ASML started shipping the new NXE: 3100 “pre-production” EUV stepper/scanner to IEC last week, using 20 trucks. “The body is being installed even as we speak here,” (figure) announced Van den hove. Source and resist improvements could get us to 6o wph in another year, but all bets are off the table for when ASML could double that. He also said that flare in the new tool is only ~4% compared to 8-10% for the “alpha-demo-tool” first installed.

Next in the morning was the plenary keynote by Shang-yi Chiang, senior vice president of R&D at TSMC, who said “most people believe that Moore’s Law is nearing the end…whether we can extend Moore’s Law into the next decade is in your hands.” The eventual limit will be economic, not technical. “Within transistor and interconnect technology developments we do not see any roadblocks,” he explained. “So the lithography cost is the single greatest factor which may limit our ability to extend Moore’s Law into the next decade.” TSMC’s CoO modeling indicates that 100-150wph EUV should cost less than 193i-DP for 14nm nodes and beyond.

Franklin Kalk, Toppan Photomasks VP, met this afternoon with SemiMD to discuss the many known challenges with lithography for the 22nm node and beyond. Kalk sees pragmatic evolution of optical technologies continuing. Metaphorically speaking, we’re not about to crash into the ground. “I feel like we’re going to land and everything will be OK,” reassured Kalk. “But we may need reverse thrusters to not run off the runway, and we may land on one wheel and bounce a bit.”

Tags: 10nm, 14nm, 193i, 22nm, ASML, CoO, DP, DR, EUV, HVM, IC, Intel, KLA-Tencor, Nikon, QP, TSMC

This entry was posted on Tuesday, March 1st, 2011 at 6:08 am and is filed under News Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.