Chenming Hu Welcomes FinFET vs. UTB-SOI Race
By David Lammers
A dozen years ago, Professor Chenming Hu led a study at the University of California at Berkeley, funded by DARPA, to figure out how CMOS technology could be extended to 25nm gate lengths. The result was two proposed paths: FinFETs, and ultra-thin-body silicon-on-insulator technology (UTB-SOI).
“Since that time, most people have focused on FinFETs, and not as much attention has been paid to UTB-SOI,” Hu said, even though both structures give the gate more control and suppress the influence of the drain voltage on the channel.
For UTB-SOI to work, the silicon thickness should be held to one-fourth the gate length. For a 25nm gate length technology, Hu said the thickness of the silicon layer should be in the range of 5nm.
After Hu and colleagues published seminal papers on FinFETs (1999) and UTB-SOI (2000), most of the industry’s development work turned to FinFETs due to expectations that it would be too difficult to get an SOI wafer with such a thin critical silicon layer.
“I felt we would not be able to get an SOI substrate, that no company would be able to supply SOI wafers with a 5nm silicon thickness. That is only 50 Angstroms, which is 12-15 silicon atoms. I felt that would not be possible, or could not be done until FinFETs were well established. This changed two years ago, when Soitec started giving out samples of 300 mm SOI wafers. These wafers had a silicon thickness of only 12nm to begin with, and after processing, seven nanometers are used up, taking it down to 5nm. That indeed is what is needed to get the technology to work,” he said.
Hu believes that FinFETs and UTB-SOI will co-exist, but that each will “try to dominate the other” in the coming years. Intel is likely to pursue FinFETs, Hu said, because that technology may be able to achieve a higher performance level for microprocessors.
“I feel both technologies will have a place, at least initially. FinFET technology is on a trajectory to go into mass production. I think it is going to happen. For Intel, UTB-SOI is probably not fast enough, so we can assume Intel will use FinFETs. For TSMC, FinFETs may be the first thing they do, because they have invested so much in developing it. And TSMC has a wide range of applications they can meet, one being high-performance applications,” Hu said.
But UTB-SOI has the advantage of being less complicated to develop. “I think UTB-SOI is going to have a future because it is a simpler technology than FinFETs. Companies simply need to buy a different substrate. For low-power applications that don’t need bleeding-edge speed, UTB-SOI is an interesting new option,” Hu said.
TSMC may start out with a FinFET technology platform at the 14 nm node, and then later add a UTB-SOI process for low-power customers. And UMC may delay investing in a FinFET development program and go directly to UTB-SOI, Hu said.
“For the next few generations (after 22/20nm) there may be room for both. But the race will be for one to try to dominate the other. UTB-SOI may not be able to replace FinFETs unless it has the required highest performance. For many companies, though, I think they may use UTB-SOI for many applications.
“Both are real. Both will have a market. For the long-term future, both will be offered, and that is good news, I think. It is exciting to see that there is going to be a choice.”
