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Design Impacts of Fully Depleted SOI

Xavier Cauchy, digital applications manager at Soitec, considers the design implications of fully depleted SOI technology, including models, low-power techniques for SoCs, and other issues at the 22nm node. “Compelling simulation and silicon data for nanometer scale transistors is becoming available. However, as potential users realize the many interests of this technology, the next question is: what about design?” he writes in the introduction.

In the section on low power design techniques, he considers Dynamic Clock Gating, Micro-architectural RTL optimizations, Multi- VT libraries, Static and Dynamic Power Switching, Retention Modes, Adaptive Voltage Scaling (AVS), Dynamic Voltage and Frequency Scaling (DVFS), Static and Adaptive Body Bias, Critical Dimension (CD) Biasing or Gate Length Biasing, and Split Supplies.

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