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3D NAND Goes Mainstream

By Brad Howard

Earlier this month, I participated in a panel discussion with colleagues from Cypress, Micron, Samsung and SK Hynix at the Flash Memory Summit 2015 in Santa Clara, California.

Over the past year, the industry has made great strides in bringing 3D NAND closer to becoming a mainstream technology. For example, at the summit, Samsung unveiled the world’s largest SSD – a 16TB drive, which is also larger than any conventional hard disk drive on the market today. This is a strong indication that SSDs using 3D NAND flash are well on the way to becoming the price and capacity leader in the expanding enterprise storage market.

However, there is still much work to be done if 3D NAND applications like Samsung’s 16TB drive are to make their way into the cost-sensitive consumer market. This became apparent during the audience Q&A, when the panel was asked how 3D NAND can continue to cost-effectively scale, particularly with a complex production process.

In my view, many of the scaling challenges are being met thanks to innovations in 3D NAND manufacturing.

For example, we’ve learned that at very high aspect ratios (more than 48 device layers), the ability to maintain etch performance from the top of the feature down to the bottom is getting much harder when using wet etch processes. Wet processing these very high aspect ratio features can actually damage them, causing them to topple or get pulled toward one another.

There is also the challenge of making the device within the feature that requires selectively removing one material with respect to the other to create a three-dimensional structure as shown in the image below. These combined challenges can be solved by using isotropic dry etching solutions that achieve high selectivity, low damage to the materials, and provide much more precise top-to-bottom uniformity.

During my opening remarks on the panel, I also presented the image below to highlight how increasing aspect ratios that result from adding more and more layers to 3D structures, like those used in 3D NAND, create issues for atomic layer deposition (ALD) saturation.

While ALD provides precise conformal and uniform layers, it is still challenging to saturate all the surfaces of the structures on the chip. And, as device layers and feature complexity increase, more surface area is created, which exacerbates the issues for saturated coverage. Advances in high-performance ALD technology can address the industry’s need for complete film coverage without compromising productivity.

Despite the increasing complexities of 3D NAND scaling, I foresee a long future for this technology if the etch control and deposition steps can be broken down into manageable chunks. This is part of technology development that, as an industry, we’re used to and can address. Our ability to keep innovating and pushing process technologies will help drive the scaling roadmap.

One Response to “3D NAND Goes Mainstream”

  1. Amit Nanda Says:

    Thanks for the discussion on the technology challenges for 3DNAND. Equipment manufacturers have successfully solved some issues (including “bowing”, “bending”, “uneven steps” etc.) encountered during HAR etching of 3D multi-layer structures. However, they cannot provide generic recipes for all materials, layouts, layer combinations etc. Therefore, 3D NAND technology designers still have to perform expensive and time consuming DOEs to achieve desired device characteristics and reasonable yield.

    A good way to decrease DOE expenses is to use TCAD simulations. Silvaco’s Victory Process is capable of accurately simulating 3D etch and deposition processes used in 3DNAND. It provides a variety of models for plasma etching, IECE, IBE, as well as capability to introduce user-defined models. Silvaco is collaborating with several industry and research partners to calibrate the models and speed-up simulations which will allow users to perform accurate DOEs and optimize complex etch/deposition processes in a few days of simulation.

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