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Archive for November, 2013

IEDM’s special focus session highlights diverse challenge

Friday, November 22nd, 2013

As part of the technical program at the annual IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013 at the Washington Hilton Hotel, a special focus session has been planned to highlight advanced processing and platforms for semiconductor manufacturing technology, including ‘more-than-Moore’ applications.

The technical session, scheduled for Tuesday, December 10 from 9am – 12pm, will feature presentations on many of today’s hot topics: memory, LEDs, silicon photonics, interposers, SOI finFETS and 450mm.

Memory industry transition from planar to 3D scaling and the introduction of emerging memory devices into manufacturing over the next decade will drive several unique challenges. The inflection point faced by the semiconductor memory industry is a new paradigm where advancements in materials science, equipment technology, and control methodologies are critical for scaling cadence. This will be the focus of “Challenges in 3D Memory Manufacturing and Process Integration,” an invited paper given by N. Chandrasekaran, Micron Technology

The output power at high temperature required for LEDs applied in solid-state lighting can be obtained by reducing threading dislocation density (TDD) on silicon substrates using a new technology, SiN multiple-modulation interlayers, to realize highly efficient blue LEDs grown on high-crystalline-quality GaN templates on 8-inch silicon wafers. This will be presented in “LED Manufacturing Issues Concerning Gallium Nitride-on-Silicon (GaN-on-Si) Technology and Wafer Scale up Challenges,” an invited paper given by S. Nunoue, et.al., Toshiba Corporation

Recently, silicon photonics has generated a renewed interest in integrated optical communications.  A paper titled “A Multi-Wavelength 3D-Compatible Silicon Photonics Platform on 300mm SOI Wafers for 25Gb/s Applications,” presented by F. Boeuf, et. al., STMicroelectronics will describe the main process features and device results for a 300mm silicon photonics platform designed for 25Gb/s and above applications, at the three typical communication wavelengths that are compatible with 3D integration.

A paper from TSMC will present the details of the first fabrication of a 300mm, 50μm ultra-thin glass interposer – a promising technology for future high frequency mobile RF applications.  The merits of on-glass inductors and transmission lines are compared to their on-silicon counterparts in Q-factor, power dissipation, and power/signal integrity. “300mm Size Ultra-Thin Glass Interposer Technology and High-Q Embedded Helical Inductor for Mobile Applications,” will be presented by W.-C. Lai, et. al., TSMC.

The first rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable 14nm SOI FINFETs, will be presented by A. Paul of GLOBALFOUNDRIES. The study identifies, threshold voltage (Vtlin), external resistance (Rext), and channel transconductance (gm) as three independent sources of variation. The variability in gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit (indicating local variations), along with non-zero intercept (which suggests global variations at the wafer level). Both n- and p-FINFETs show the above-mentioned trends. The paper is titled “Comprehensive Study of Effective Current Variability and MOSFET Parameter Correlations in 14nm Multi-Fin SOI FINFETs.”

The 450mm transition represents an opportunity to reduce die cost and stimulate another wave of innovations and greener manufacturing. Key challenges ahead, including tool productivity, uniformity, precision, cost-of-ownership reduction, and green concept design-in tool and manufacturing systems, are presented. “Opportunities and Challenges of the 450mm Transition,” is an invited presentation by J. Lin and P. Lin, TSMC.

Progress in Intrachip Optical Interconnects and Silicon Photonics

Friday, November 15th, 2013

In a keynote talk at The ConFab earlier this year, Samsung exec Yoon Woo (Y.W.) Lee. predicted that optical interconnects would soon be required. “Exascale computing will require optical interconnection to communicate between the CPU and memory chip,” he said. This appears to be moving closer to reality with last week’s demonstration by Fujitsu and Intel of the world’s first Optical PCIe Express (OPCIe) based server. 

Intel’s 50Gbps silicon photonics link was demonstrated in 2010, and it has now been put into practice. Just last week, Fujitsu said it has demonstrated the world’s first Intel Optical PCIe Express (OPCIe) based server.  In a blog, Intel’s Victor Krutul said that Fujitsu took two standard Primergy RX200 servers and added an Intel Silicon Photonics module into each along with an Intel designed FPGA.  The FPGA did the necessary signal conditioning to make PCI Express “optical friendly”.  Using Intel Silicon Photonics they were able to send PCI Express protocol optically through an MXC connector to an expansion box.  In this expansion box was several solid state disks (SSD) and Xeon Phi co-processors.

It’s commonly known that silicon is not a good material for generating or detecting light (although silicon dioxide is quite good at channeling light). Optical interconnects will require III-V lasers to convert electrical signals into pulses of light and, on the receiving end, photodetectors, typically germanium-based, to convert that light back into electrical signals. Intel has demonstrated that it’s feasible to directly integrate photonics with silicon CMOS in an impressive prototype, but most solutions will require some type of some type of advanced packaging, such as flip-chipped lasers.

During a discussion with Ludo Deferm, executive vice president at imec on interconnects – imec had recently released details about the benefits of manganese as a diffusion barrier and some work on low-temperature low-k etch – I asked him about optical interconnects.

For intrachip applications – such as between microprocessor and memory — Deferm said that will depend on the data rates required. “If you have 1000, 5000 parts to be connected over a distance of a couple of millimeters and you want to transfer a Gb of data, just copper lines can have some limitations,” he said.  “If you have the space — and it takes space — you can do it. But you will do that where you need the high transmission rates. There is no need to change the intrachip interconnects with photonics. But the interchip, between the different chips, we are working on that because we are even now providing photonics technology to startup companies and other companies who want to design in it.“

Part of the challenge is that various optical components are required – waveguides, detectors, modulators and polarizers, for example – and those are not available at standard foundries. Imec has a design kit and a library and IME in Singapore has capabilities as well.  

Deferm said these components are not so easily integrated. “Most of the problems are related to losses. Optical kinds of interconnects have the advantage – they’re good at data speed – but you have to be careful because you can create losses because you need wide ideal structures. Not because they have to be so small in dimension, but they have to be controlled very well over the edges: it is light and light scatters. You also have losses because of coupling,” he said. On a silicon substrate, a high frequency signal in Gb/seconds also creates coupling towards the substrate and that creates losses as well.

SST’s Editorial Calendar for 2014 is Out

Friday, November 8th, 2013

The new Solid State Technology Editorial calendar for 2014 – the whole media planner actually – is out and live on our site: http://electroiq.com/advertise-docs/2014mediakit.pdf

The editorial mission remains that same: we’re dedicated to covering mainstream semiconductor manufacturing technology, with a strong focus on transistors, interconnects and packaging. We also cover other types of advanced electronics, including MEMs, LEDs, displays, bioelectronics, photonics and power electronics. In 2014, we’ll be looking at CMOS imagers, thin film batteries, OLEDs, smart sensors, and plastic electronics, among others.

We also delve into the process technologies – lithography, etch, deposition, implant, planarization – and materials. We will also be addressing over-arching topics such as metrology, contamination control, defect detection, thermal management, automation and supply chain issues. And, of course, the 450mm transition.

We’ll be covering these in the magazine (8X in 2014), on the website (www.solid-state.com and www.semimd.com), and through regular webcasts, newsletters, video reports and at our live event, The ConFab in June (www.theconfab.com).

If you’re interested in contributing material on these or other topics, just shoot me a line at psinger@extensionmedia.com, or give me a call at 978-470-1806 I look forward to hearing from you!

SST

Should lifetime of EUV optics be a concern?

Thursday, November 7th, 2013

It’s well known that EUV adoption is running later than hoped, mostly due to inadequate source power (although ASML and Cymer say they are on track to provide workable solutions and imec says it’s on track for the 10nm node). After that, the main challenge could be those associated with EUV mask blanks, which are essentially sophisticated mirrors. The dual challenge there is that they are not only difficult to produce without defects, but they are difficult to inspect. Presently, the only way to really test them is to fabricate them and see what kind of pattern results after they’re used.

But another challenge recently came to my attention: the optics in the EUV system, which are also sophisticated mirrors made of multi-layer structure, get contaminated during operation. This degrades their quality over time, and eventually the system must be disassembled and the optics recoated or replaced.

EUV optics F1

I recently talked to Dr. Harro Hagedorn, head of R&D at Leybold Optics in Alzenau, Germany. Located about 20 minutes outside of Frankfurt, the company supplies evaporation and magnetron sputtering systems used to fabricate the multi-layer coatings used for EUV collector optics and or many other applications such as synchrotron labs and X-ray devices. And they work with ASML and Zeiss, and the Fraunhofer Institute.

Speaking on EUV, Dr. Hagedron, said the output of the light source is still not high enough, and also the lifetime of the optics was a concern. “This light source is normally an awful thing for the optics because you have a metal droplet that is heated up by a laser and then it creates a plasma. These metal droplets are also contaminating the optics,” he said. To correct, this “they have to disassemble the system and recoat these optics. They are very expensive. Also, the life throughput that comes from this light source and through the optics goes down. They have to also manage this,” he said.

Part of the complexity and expense of the optics is that they rely on interference coatings that require stacks of layers. “The challenge is that these layer stacks are incredibly thin, 3-4nm, with coating uniformities in the range of 0.1%,” Hagedron said. “It’s not any more than a diameter of an atom.” The goal for these optics is a reflectivity of nearly 70%.

Investigating a bit further, I found that there has been a significant amount of research into the lifetime of EUV optics. In fact, earlier this year in April, a session at SPIE was dedicated to damage to VUV, EUV, and X-ray Optics. One of the papers by Laser-Lab in Germany, KLA-Tencor and Fraunhofer, described work that characterized EUV damage thresholds and imaging performance of Mo/Si multilayer mirrors. Here’s a summary:

Currently, more and more powerful EUV sources for next generation semiconductor microlithography are being developed, for which novel optical elements like multilayer or grazing-incidence mirrors are required. Consisting of very thin alternating layers, especially molybdenum and silicon for the wavelength of 13.5 nm, multilayer mirrors are typically employed for near-normal reflection angles. These mirrors are presently being optimized with respect to thermal resistivity and reflectivity. However, only very few ablation and damage threshold studies at a wavelength of 13.5 nm are available up to now for these optical elements.

We studied 1-on-1 and 10-on-1 damage thresholds of Mo/Si multilayers with EUV radiation of 13.5 nm wavelength, using a table-top laser produced plasma source based on solid gold as target material. The experiments were performed on different types of Mo/Si mirror, showing no significant difference in single pulse damage thresholds. However, the damage threshold for ten pulses is ≈60 % lower than the single pulse threshold, implying a defect dominated damage process.

Using Nomarski (DIC) and atomic force microscopy (AFM) we analysed the damage morphologies, indicating a primarily thermally induced damage mechanism for higher fluences. Additionally, we characterised transmission and reflection properties of novel Mo/Si multilayer beam splitters performing wavefront measurements with a Hartmann sensor at 13.5 nm wavelength. Such wavefront measurements allow also actinic investigations of thermal lens effects on EUV optics.

My main takeaway from all of this is that even if the technical challenges of EUV make it ready for production for the 10nm device generation, there still must be lots of questions about the ultimate cost of ownership and how that will compare to double and triple patterning approaches with 193nm immersion.