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A Reality Check with Intel

The 55th International Electron Devices Meeting (IEDM) will be held next month, from December 7-9, at the Hilton Baltimore. One of the highlights of the year for us tech editors is when we receive the set of abstracts from the conference organizers, provided in advance so we can write our previews and plan our week at the conference.

The conference is well known as the place where all the major semiconductor manufacturers officially unveil the latest technology advances, where speed records are announced, and where some of the emerging, research-level types of devices are reported for the first time. This year’s emerging technology session will showcase graphene nanoelectronics, including how to integrate graphene into field-effect transistors, interconnects and other IC applications; graphene-based heterojunction devices that exhibit full quantum transport; spin transport valves that may lead to spintronics-based graphene devices; and nano-electro-mechanical devices.

Spintronics-based MOSFETs will also be reported, seen as one of the alternatives once CMOS technology has outlived its usefulness. Toshiba researchers integrated ferromagnetic tunnel barriers with silicon for the first time ever and will report on it at the IEDM. The researchers will discuss fabrication techniques and observations of spin transport.

Also very much in the “cool” category is work from UC-Berkeley. At IEDM, researchers will describe a wetting-based technique used to build self-aligned organic transistors and circuits with a minimum overlap of just 0.78µm. Everything was inkjetted — the semiconducting layers, metallization and dielectrics. The researchers say the process is simple enough that inexpensive all-printed circuits may be realized in the near future.

While it’s very easy to get excited about these and other promising advances that could potentially transform the semiconductor and related industries, a little reality check might be in order. For me, that came through an interview with Intel’s Mark Bohr, who described the company’s CPU and SoC technologies that will be presented at this year’s IEDM.

The company’s official description (provided in the tip-sheet) is this: Intel researchers will discuss a flexible, modular, mix-and-match 32-nm technology platform for advanced systems-on-a-chip (SOC) for diverse applications, including high-performance computing, low-power operation, and integrated RF/analog functions. The technology has a high-k/metal-gate architecture with three different transistor types (two with the same gate stack but different junction implants). It can support up to 11 interconnect layers, offers RF/analog passive elements, RF noise-mitigation features, and embedded memory with options for high-density (0.148µm2 cell size) or low-voltage (0.171µm). The technology demonstrated excellent reliability and enables ultra-low-power, high-performance and high-voltage-tolerant devices to be combined on the same silicon, in order to span a wide range of power, performance and feature requirements.

What’s interesting to me here is that Intel is not talking much about new process technologies, but rather the evolution of SoC. Intel first unveiled an SoC chip with the 45 nm (internally a “dot” version, the p1266.8.). With the 32 nm version and moving forward, Bohr said there are enough significant differences between the SoC and the CPU version to give its own number to the SoC version. 1268 is the CPU version, the 1269 is the SoC version of 32 nm.

Intel’s 32 nm, and most likely the 28 nm, transistors for both CPUs and SoCs use high-k metal gates (HKMG), strained silicon and employ immersion lithography. What’s interesting to me is what they do not employ: no tri-gate designs and no III-Vs in the channel region, for example. “Those types of more exotic solutions are not needed at this generation although we are continuing to explore them in our research group for future generations,” Bohr said. “Keep in mind though that high-k metal gate is still relatively new. Intel is the only company shipping high k metal gate and we did that successfully at 45 and this is the second generation so there’s still more to squeeze our of high k metal gate technology.”

Ditto for next-generation lithography solutions. “We think immersion lithography will be with us for a few more generations. We’d like to have EUV but it looks like it just won’t be ready in time for 22 nm and maybe not even for 15 nm. In the meantime, we’ll have to make do with immersion lithography and we think a greater use of double patterning techniques will be the way to do that – to extend immersion before EUV is ready. The nanoimprinting idea has been out there but I’m skeptical about whether it is going to be very viable for manufacturing applications,” Bohr said.

Instead of the exotic, Intel is instead emphasizing SoC products, which tend to require a broader range of device types. “In addition to the normal logic transistors, you need to include analog device elements such as inductors and precision capacitors. You also need to provide a wider range of transistor types from the high performance transistors used on CPUs to some very low leakage, low power transistors needed where long battery life is important. Also system on a chip products need to support a wider range of legacy I/O voltages, thus we have to add some special transistors that are tolerant to higher voltage conditions,” Bohr said.

SoC chip also have different interconnect requirements. “For the metal interconnect system for CPUs, those interconnects tend to be optimized for higher performance meaning some of the upper layers tend to use thicker and wider copper lines than the lower layers. That’s to provide higher speed interconnects across the surface of the chip. But for SoC products that run on lower frequencies, they don’t need the same higher performance interconnects. They may prefer a high density interconnect so we offer a different interconnect system for the SoC products providing fewer metal layers if low cost is important or more metal layers if increased interconnect density is important,” Bohr said. “Next we provide a range of advanced passive device elements such as precision resistors, capacitors and high-Q inductors, and a range of embedded memory from the very smallest, dense SRAM cells to low voltage SRAM to high speed SRAM. For our SoC product design, we offer this rich mix and match feature set. They can choose which features best meet the needs of their individual SoC products.”

In general, Intel plans to stay on its well established two year cadence, but moving to a dual platform approach, introducing both a CPU-specific and SoC-specific version of each technology. Production of 32 nm products is just starting this year: the end of 2011 should see 22 nm products, with 15 nm introduced at the end of 2013. How soon will we see some of the more exotic technologies such as graphene and spintronics in volume production? Not soon, given the conservative nature of the industry. Instead, it’s going to be all about integration.

Here’s what Mark Bohr told me, with a few slides to illustrate his points:

"We have two papers describing our 32 nm technology that were accepted for the IEDM. The first of those two papers describes in more detail the transistors used on our high performance CPUs for 32 nm. The second paper, Intel will be disclosing for the first time the technology that we’ve developed for 32 nm SoC products. Those two technologies are very similar, they share a lot of steps, but we’ve done some extra things, added features specifically for 32 nm SoC products. Both of these technologies use our second generation high k metal gate transistors which provide the highest drive current, the lowest leakage current and the tightest transistor gate pitches of any reported 32 nm or 28 nm technology.

The third key message is our 32 nm CPU process is certified. We have Westmere CPU wafers moving through the factory in support of a plan to keep with our revenue projection.

We reached a milestone on our 45 nm technology. We’ve shipped more than 200 million CPUs on that technology using high k plus metal gate transistors. That successful experience at 45 nm will help lead to a successful ramp of 32 nm products.

Regarding Intel’s naming system for the various logic technologies we’re developing or have in manufacturing: Not only are we continuing a 2 year cadence between technology generations but we’re now developing both CPU and SoC versions of each of these generations. The 45 nm generation, the CPU version is named p1266, the SoC is what we call the 1266.8. But now with the 32 nm generation, not only do we have these two versions but we’ve recognized that there are enough significant differences between the SoC and the CPU version to give its own number to the SoC version. 1268 is the CPU version, the 1269 is the SoC version of 32 nm. We’ll continue this going forward. At the 22 nm generation we’ll have both the P1270 and the 1271 for SoC products.

At 45 nm we were the first to introduce high k plus metal gate transistors, started shipping in volume in November of 2007 and so far we’re the only company shipping high k metal gate. It’s now down to very low defect levels and it is Intel’s highest yielding process ever. Even with the introduction of these revolutionary high k plus metal gate transistors, we have also achieved the highest yielding process ever.

Intel’s CPUs range from a single core up to eight cores. A back of the envelope calculation: 200 million CPUs adds up to more than 50 quadrillion transistors. That’s a five with 15 zeros after it. That’s enough for every 7 million transistors for every man, woman and child on our planet!

This is the second generation of high k metal gate transistor technology. We use 9 copper plus low k interconnect layers. This generation we’re introducing immersion lithography and that provides about a 0.79% scaling of the minimum pitches. This technology is also lead-free and halogen free packages.

The following graphic illustrates Intel’s trend in scaling the transistor gate pitch which is probably the most important design rule on a logic technology. It’s an indication of how closely you can pack transistors together. We’ve been scaling that design rule by about .7X every generation and now with the 32 nm generation, it’s been scaled down to a pitch of 112.5 nm. That is the tightest gate pitch of any reported 32 nm or 28 nm technology.

Some may have the impression that a 28 nm technology might be denser to what Intel has at 32, that’s not the case at least in the case of transistor gate pitch.

Intel’s trend for increasing transistor drive currents is certainly an important factor in performance. While we’ve been scaling gate pitch, we’ve also been able to continually increase drive current through the introduction of things like strained silicon technology at the 90 nm generation, then high k metal gates at 45. The driver currents on our 32 nm process are the highest reported drive currents for any reported 32 nm or 28 nm technology.

Here we illustrate Intel’s tick tock development model showing how every year we alternate between introducing a new micro architecture or introducing a new generation of process technology. Westmere is the name of the first product on our 32 nm technology. This is referred to as a tick product in the tick-tock scheme because it is the first product on our new process generation while retaining or extending the micro-architecture that was introduced on the 45 nm Nehalem product. If you recall, Intel did our first public demonstration of our Westmere CPU chips working in systems back in January of this year. Now we’re about to enter the fourth quarter and we’ve begun our production ramp for Westmere.

Defects have come down rapidly. Yields are now high. They are up to the level needed to begin a production ramp. The defect trend is offset by less than two years compared to our various successful 45 nm technology. Our process is certified and CPU wafers are now moving through the factory in support of planned Q4 revenue projections.

As we announced in February. Intel has four factories coming up on the 32 nm technology. D1D in Oregon is the first followed by D1C in Oregon, Fab32 in Arizona and Fab11X in New Mexico. Intel is investing about $7B in these factories to install the equipment and get them ready for manufacturing 32 nm products. D1D the equipment has been installed for some time now. We’ve already begun the production of the Westmere chips. D1C is just finishing the installation of that equipment. Fab32 and Fab 11X are in the process of installing equipment.

All for now.. stay tuned for my compelling Q&A!

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