University Research Award recipient; SEMI World Fab Forecast; Resesarchers develop Source-Gated Transistor; Global failure analysis equipment market increase; Industry revenues reach record high
News Stories Archive
New blogs take a look at design challenges associated with re-filling an engineering change orders (ECOs), this year’s ISS meeting, and the pervasiveness of cheap silicon.
MIT research; Renesas unveils MCUs, EVG and Brisbane Materials introduce a new AR coating for LEDs; International Rectifier opens ultra-thin wafer processing facility in Singapore; EU launches PLACYD; JILA physicists discover “quantum droplet” in semiconductor
New blogs take a look at recent reports from G450C showing good results for major process steps and inspection (although cost benefits remain to be proven), new FD-SOI results demonstrating a 10X faster DSP, the need for high sigma yield brought on by the move to 28/20nm and 16nm, Obama’s policy impact on the semiconductor industry, the recent IEEE 3D IC and GaTech Interposer meetings, and the latest nanotechnology-use survey from NCMS.
Worldwide silicon wafer revenues declined in 2013; Rudolph Technologies announces shipments for 3D metrology of TSV; Honeywell introduces RadLo low alpha plating anodes; imec and Holst demonstrate ECG chip; SPTS opens new office in Korea;
New blogs discuss why Intel’s embedded DRAMs have a very different structure than other e-DRAMs, the expected future of interposers (mostly silicon!), the hottest devices and trends in evidence at the Consumer Electronics Show, thoughts on how we got to where we are and answers to other life questions, the upcoming MEMS Executive Congress in Munich, and a look back at Solid State Technology in 1964.
IBM looking to sell semi business; Graphene nanoribbon research; Entegris to acquire ATMI; SEMI ISS wraps up; Intel elects five new corporate VPs
New blogs take a look at last month’s ISS meeting, where the focus was squarely on economics, the design challenges posed by new FinFET transistors, recently announced news from STMicroelectronics on FD-SOI, and a final wrap-up of the IMAPS 2013 meeting, with an analysis of work by Xilinx/SPIL, Nanyang/IME, Canon, and AT&S.
Next Generation Power Electronics Institute; SMIC demonstrates 28nm readiness; Cooling microprocessors with carbon nanotubes; SEMICON Korea focuses on mobile innovations; Achievements in solid-state laser engineering; Ultra-low loss and high temperature thermoset materials
New blogs examine why 20nm high volume production could be delayed, thoughts on a new paradigm shift as viewed in the light of semiconductor equipment booking, and the difference between monolithic 3D ICs and back end 3D with TSVs.
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.