“By 2020, we are all going to work for the same company,” Wally Rhines, chairman and chief executive officer of Mentor Graphics, said Tuesday morning (April 26) in his keynote presentation at Mentor’s U2U user conference in Santa Clara, Calif.
News Stories Archive
Intel reported net income of $2.0 billion in the first quarter, up 3 percent from a year earlier, while revenue rose 7 percent to $13.7 billion, compared with $12.8 billion one year ago.
Manufacturing flexible electronics and coatings for a variety of products has some similarities to semiconductor manufacturing and some substantial differences, principally roll-to-roll fabrication, as opposed to making chips on silicon wafers and other rigid substrates. This interview is with Neil Morrison, senior manager, Roll-to-Roll Coating Products Division, Applied Materials.
To understand the state of technology preparedness to meet the anticipated needs of the different application spaces, experts from GLOBALFOUNDRIES, Cadence, Mentor Graphics and Presto Engineering gave detailed answers to questions about IoT chip needs in EDA and fab nodes.
To meet the anticipated needs of the different IoT application spaces, SemiMD asked leading companies within critical industry segments about the state of technology preparedness.
Presto Engineering Inc., a world leader in semiconductor product engineering and supply chain management, and Peraso Technologies, a leading wireless chipset manufacturer, today jointly announced their successful collaboration in developing a comprehensive test solution for Peraso’s recently-launched 60 GHz semiconductor products.
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has entered into a definitive agreement to acquire Rocketick Technologies Ltd.
Mentor Graphics’ User2User meeting will be held in Santa Clara on April 26, 2016. The meeting is a highly interactive, in-depth technical conference focused on real world experiences using Mentor tools to design leading-edge products.
The “big trends” in the electronics industry are social, mobility, the Internet of Things, and security, Lip-Bu Tan, the president and chief executive officer of Cadence Design Systems, said Tuesday (April 5) in his keynote address at the CDNLive Cadence User Conference in Santa Clara, Calif.
Cadence Design Systems, Inc. and the University of Oxford today announced a move to foster the advancement of formal verification innovation with the appointment of Dr. Ziyad Hanna, Cadence vice president of R&D, as a visiting professor in Oxford’s Department of Computer Science for the next three years.
You are currently browsing the archives for the News Stories category.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.