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Samsung to put 10nm chips into mass production by end of 2016

Samsung Semiconductor on Thursday announced that it will have 10-nanometer FinFET chips in volume production by the end of next year.

New Applied PVD system targets TiN hardmasks for 10nm, 7nm chips

Applied Materials introduced the Applied Endura Cirrus HTX PVD, a physical vapor deposition system for creating titanium nitride hardmask films that could be used in fabricating 10-nanometer and 7nm chips.

Danaher to buy Pall in $13.8B deal

Danaher Corporation announced that it will acquire Pall Corporation for $13.8 billion. Once the transaction is completed, the merged company plans to split into two publicly traded corporations.

It’s blue skies for Jabil and its customers

While making printed circuit boards is still a big business for the St. Petersburg, Fla.-based Jabil, which boasts 90 plants in 24 countries around the world, the Blue Sky Center emphasizes that Jabil has progressed from being a board manufacturer to a full-service supply chain management firm.

Safe CMP slurries for future IC materials

New CMP processes for new materials planned to be used in building future IC devices are now in R&D. Early data on process trade-offs as well as on EHS aspects were presented at the CMP Users Group meeting.

Silicon Summit speakers look at the future of chip technology

GSA’s Silicon Summit at the Computer History Museum in Mountain View, Calif., not far from Google’s headquarters, was dominated by talk of IoT, AR, VR, and (to a lesser extent) wearable devices.

Monolithic 3D processing using non-equilibrium RTP

Qualcomm endorses CEA-Leti’s “CoolCube” transistor stacking approach.

TSMC Certifies Mentor Graphics Tools for Early Design Start in TSMC’s 10nm FinFET Technology

Mentor Graphics Corp. (NASDAQ: MENT) announced that TSMC and Mentor Graphics have reached the first milestone of their collaboration on 10nm EDA certification

Deeper Dive: Xpedition Enables Co-Design of Chips, Packages, Boards

A new product from Mentor Graphics called Xpedition® Package Integrator provides a new methodology and platform in addition to a new suite of EDA tools. The platform enables chip, package and board designers to easily see how changing various design elements impact adjacent designs, an industry first.

Synopsys founder has plenty of work to do, isn’t interested in politics

Aart de Geus is not running for governor of California.