Nanium launches industry’s largest WLCSP in volume; Pixelligent wins DOE award; EUV at SPIE Photomask; SiTime closes new round of financing, Silicon Motion elects new board member
News Stories Archive
Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.
New blogs report on the recipients of Tech Awards from The Tech Museum of Innovation, why RF-SOI is good for more than integrating RF switches, the use of TSVs in Samsung’s 64 GB DDR4, MEMS in Shanghai at MIG’s event, the Revitalize American Manufacturing and Innovation (RAMI) Act, the growing complexity of fill in IC design, and a potential game-changer for 3D ICs.
EUV available at 10nm; SEMI releases August book-to-bill; Rudolph’s new SONUS technology; Samsung mass produces 6Gb mobile DRAM, ProPlus Designs expands sales operations to Europe; Mentor Graphics appoints new VP of Embedded Systems
Photomasks that take two-and-a-half days to write. Mask data preparation that enters into Big Data territory. And what happens when extreme-ultraviolet lithography really, truly arrives?
Front end fab equipment spending to increase in 2015; GLOBALFOUNDRIES announces scholarship program; SEMI wins request for etch equipment export control review; New deposition equipment supplier, RF power semiconductor spending on the rise
New blogs report on a “perfect storm” when it comes to the growing complexity of fill in IC design; the disruptive nature of 3D NAND for flash storage; fan out packaging papers presented at ECTC by STATSChipPAC, SPIL, Nanium and Google/Novartis; a look inside and outside Leti in France; FD-SOI’s role in mobile platforms; and how EDA is fostering education.
New non-volatile memory technology; President and CEO of FSA announced; Samsung to use ProPlus 14nm finFET SPICE modeling platform; MEMS gyroscope from Analog Devices; SEMICON Taiwan held this week
Intel releases new packaging technologies; Fairchild Semiconductor to close two facilities; KLA-Tencor introduces new metrology tools; UMC joins Fujitsu’s new foundry company; Thinnest-possible semiconductor; SEMI announces keynotes for Vietnam Semiconductor Strategy Summit
Collaboration for next-generation smart glasses; Book-to-bill ratio holds steady in July; Intel and Unity to collaborate; MediaTek launches new R&D facility; Amkor appoints new member to board of directors; STATS ChipPAC achieves shipping milestone
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.