GlobalFoundries acquires IBM’s semi business; Mergers and acquisitions shake up automotive semi supplier landscape; Adlyte achieves performance benchmark for EUV light source; Gigaphoton achieves 3-hours of continuous operation of its EUV light source; Book-to-bill ratio declines in September
News Stories Archive
New blogs delve in the challenges of IC verification for automotive electronics, the need for higher purity and better-characterized electronic materials, SEMI’s recent Strategic Materials Conference, the IoT and need for security, IBM’s work on graphene, the polymer dielectric market, a recent IMAPS workshop, the Nobel Prize in physics and FD-SOI at Semicon Europa.
Wearable sensors market expanding; Intermolecular appoints new president and CEO; Qualcomm to acquire CSR, Texas Instruments ships more than 22 billion units of copper wire bonding tech; Element Six develops new thermal grade diamond substrate
There has been a great deal of handwringing and naysaying about the industry’s progress to the 14/16-nanometer process node, along with wailing and gnashing of teeth about the slow progress of extreme-ultraviolet lithography, which was supposed to ease the production of 14nm or 16nm chips. Joseph Sawicki, vice president and general manager of Mentor’s Design-to-Silicon Division, is having none of it.
Samsung invests in new fab; Soraa founder wins Nobel Prize in Physics; SIA announces Robert N. Noyce Award recipient; UMC announces joint venture, SiC and GaN technology adoption
SEMI’s Strategic Materials Conference was held September 30-October 1, 2014, in Santa Clara, CA at the Biltmore hotel. Karey Holland of the Techcet Group provides a wrap-up blog.
Nanium launches industry’s largest WLCSP in volume; Pixelligent wins DOE award; EUV at SPIE Photomask; SiTime closes new round of financing, Silicon Motion elects new board member
Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.
New blogs report on the recipients of Tech Awards from The Tech Museum of Innovation, why RF-SOI is good for more than integrating RF switches, the use of TSVs in Samsung’s 64 GB DDR4, MEMS in Shanghai at MIG’s event, the Revitalize American Manufacturing and Innovation (RAMI) Act, the growing complexity of fill in IC design, and a potential game-changer for 3D ICs.
EUV available at 10nm; SEMI releases August book-to-bill; Rudolph’s new SONUS technology; Samsung mass produces 6Gb mobile DRAM, ProPlus Designs expands sales operations to Europe; Mentor Graphics appoints new VP of Embedded Systems
You are currently browsing the archives for the News Stories category.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.