Exposures, and reducing their cost, were a theme running through the 2015 SPIE Advanced Lithography Symposium this week in San Jose, Calif., the center of Silicon Valley.
News Stories Archive
In lithography for manufacturing semiconductors, a negative tone can be a positive attribute.
At this week’s SPIE Advanced Lithography Symposium in San Jose, Calif., the hottest three-letter acronym is less EUV and more DSA, as in directed self-assembly.
The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium. EUVt lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and TSMC. On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.
Speakers at the plenary session of the SPIE Advanced Lithography conference covered a wide variety of topics, from photonics to 3D chips to the Internet of Things, on Monday morning, February 23, in San Jose, Calif.
Nikon and KLA-Tencor put on separate conferences in San Jose, Calif., on Sunday, February 22, tackling issues in advanced optical lithography. The overarching theme in both sessions was the increased complexity of lithography as it approaches the 10-nanometer and 7nm process nodes.
News blogs report on Scott McGregor’s talk at ISS (where he said exponentially rising costs will bring major changes), robust design with IP, FinFET day at IEDM, multiferroic switches, the RAMI act, IEEE 3DIC conference, SOI at IEDM, and the CES show.
News blogs delve into TSMC’s announcement of EUV production orders, the International Electron Devices Meeting (IEDM), The 4th Annual Global Interposer Technology Workshop, new MRS awards, electronic materials challenges, FD-SOI, ESD and the recent IMAPS conference.
Mentor Graphics Corp. announced the immediate availability of its new Mentor EZ-VIP PCI Express Verification IP, which reduces testbench assembly time for ASIC and FPGA design verification by a factor of up to 10X.
A new hardmask material, called Saphira, and accompanying processes was introduced Applied Materials. The material, which is transparent and offers high selectivity and good mechanical strength, could reduce manufacturing costs by 35% per module.
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.