New blogs provide a preview of The ConFab’s keynote talk by Qualcomm’s Roawen Chen, a review by CEA-Leti researchers on 3D integration with SOI, an analysis of the IMAPS Device Packaging Conference, and an overview of the issues surrounding sustainable manufacturing.
News Stories Archive
SIA reports sales of semiconductors in February 2014 increased 11.4 percent from February 2013; GSA celebrates 20 years; SEMI expanding Innovation Village at SEMICON Europa
New blogs reveal the lineup of speakers for The ConFab’s Session 1, which will provide an excellent overview of the semiconductor industry’s major drivers and challenges; thought about Altera’s sometimes confusing deals with Intel and TSMC; cost-related issues of FinFETs compared to standard CMOS processes; ASE and Inotera’s join development program aimed at 3D IC packaging.
New AFM for 300mm bare wafers that improves throughput; ON Semiconductor to acquire Trusense Imaging; SureCore reveals results of early testing for new low power SRAM designs; Researchers develop new material able to conduct heat 20 times better than original polymer
New blogs discuss metrology in the age of 3D memory, the many benefits of FDSOI, this year’s IMAPS Device Packaging Conference, the recent MEMS Industry Group meeting in Europe, and the upcoming R&D panel session at The ConFab in June.
Altera and Intel extend partnership; Samsung introduces new flip chip LED packages; eInfochips to offer design services based on 16nm geometry; Particle Measuring Systems joins SEMATECH; CEA-Leti to demonstrate new prototype for wireless high data rate Li-Fi
New blogs take a look at a new IBS analysis of FDSOI, an upcoming webcast on 3D Integration and lithography, and a long angry speech of scorn and criticism on packaging nomenclature, condensed and articulated.
UC Berkley research in on-chip inductors; Equipment bookings and billings continue along a steady trend; SMIC CEO awarded SEMI Outstanding EHS Achievement Award; EVG opens HQ in China; ChaoLogix offers security for semi chips; Applied Materials named a World’s Most Ethical Company
New blogs take a look the keynote lineup for The ConFab, to be held June 22-25 in Las Vegas, the recent SEMI 2.5/3D IC Summit held in Grenoble, and wearable electronics in the IoT era and the role that equipment and materials suppliers need to play.
Toshiba, SanDisk file suit against SK Hynix; imec achieves a record conversion efficiency of 8.4 percent with fullerene-free OPV; STATS ChipPAC unveils new manufacturing method for wafer level packaging; Leti fabricates ultra-scaled split-gate memories with gate length of 16nm; EVG unveils NanoSpray for 2.5D/3D IC/TSV performance
You are currently browsing the archives for the News Stories category.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.