New blogs examine the future of NAND flash memory, a preview of the International Electron Devices Meeting (IEDM) – is it time to think about the end of silcon? – Skyworks’ use of SOI, the Sony ISX014 8MP sensor, MEMS and the Internet of Things, and The ConFab, which will be held June 22-25, 2014 in Las Vegas.
News Stories Archive
Worldwide semiconductor sales; Soitec announces high-volume manufacturing of eSI substrates; SEMI releases World Fab Forecast; Micron announces new VP of Quality; Industry on track for highest-ever annual sales in 2013
New blogs examine packaging news from Semicon Taiwan, how dynamic resource allocation during post-tapeout flow can increase turnaround time, the role of hardware in sensor fusion, and the Internet’s progress since its birth 44 years ago.
Soitec and SunEdison enter patent agreement; SIA announces ACTF 2013 Distinguished Service Award; Berkeley chooses IO Semiconductor’s Analog FastSPICE; CEA-Leti announced research agreement with OMRON; PPG expands OLED production
New blogs examine Intel’s expanded push into the foundry business, the status of EUV sources, substrates for 3D integration, IEDM sessions, and the challenges of giga-scale circuit design with nano-scale technologies.
SoC solution on a 2.5D silicon interposer exhibited; SEMI reports October 2013 book-to-bill ratio above parity; Soraa to open new semi fab in NY; Dow Corning introduces new silicone for LEDs; SUSS installs excimer laser; EVG introduces non-contact lithography system
New blogs cover the possibility of GLOBALFOUNDRIES producing Apple’s A7 chip in New York, silicon photonics and optical interconnects, a new Pattern Aware Memory IP technology from Memoir Systems, and several advancements in 3D integration related to RDL interconnects, thin wafer handling and a new low temp via reveal passivation process with stress compensation.
SEMI releases 450mm Standards update; Xilinx ships industry’s first 20nm product; SEMI extends deadline for submissions for ASMC; FlipChip acquires MMS; Tosoh to expand operations for the new 450mm wafer market.
New blogs delve into the impact of pervasive computing on the semiconductor industry, the opportunities in MEMS, flipchip market research, bump-on-polymer reliability, chip embedding, lifetime concerns of EUV optics, a curious take on Moore’s Law and SST’s new editorial calendar for 2014.
SOI news from Peregrine and GLOBALFOUNDRIES, Rubicon’s new large diameter pattern sapphire substrates, Research news from SRC and Northeastern University, imec demonstrates III-V finFETs
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.