The second day of the InvenSense Developers Conference saw presenters get down to cases – use cases for sensors.
News Stories Archive
InvenSense president and chief executive officer Behrooz Abdi sees the Internet of Things as an Internet of Sensors, a theme he explored Tuesday afternoon (November 17) at the opening of the fourth annual InvenSense Developers Conference.
The Phil Kaufman Award is presented by the Electronic Design Automation Consortium (EDAC) and the IEEE Council on Electronic Design Automation (CEDA). It honors the memory of Philip A. Kaufman, the EDA industry pioneer, electronics engineer, and entrepreneur, who died in 1992.
Many people are aware of the Internet of Things concept. What they want to know now is how to secure the IoT and how to develop code for it.
In his ARM TechCon keynote address on Wednesday morning (November 11), which was entitled “Building Trust in a Connected World,” ARM Holdings CEO Simon Segars reviewed the history of significant products in the 20th century and noted how their pricing was reduced through “optimizing supply chains.”
ARM Holdings today is introducing the ARMv8-M architecture for embedded devices and the ARM Cortex-A35 64-bit processor as the company opens the annual ARM TechCon conference and exposition in Santa Clara, Calif.
“Innovation is still thriving in semiconductors,” said Mark Muller, chief technology officer of ARM Holdings, in a keynote address Tuesday morning (November 10) at the ARM TechCon conference and exposition in Santa Clara, Calif.
A wide variety of microelectromechanical system (MEMS) devices, sensors, and MEMS sensors were described and introduced at the MEMS Executive Congress US in Napa, Calif.
Not all segments in MEMS and sensors are enjoying hockey-stick growth forecasts, as commoditization and pricing pressures take hold. This was just one of the insights gleaned at last week’s MEMS Executive Congress US 2015.
On the second day of the MEMS Executive Congress US in Napa, Calif., Wouter Leibbrandt of NXP Semiconductors gave the keynote address on “Secure Connections for the Internet of Things.”
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.