News blogs delve into TSMC’s announcement of EUV production orders, the International Electron Devices Meeting (IEDM), The 4th Annual Global Interposer Technology Workshop, new MRS awards, electronic materials challenges, FD-SOI, ESD and the recent IMAPS conference.
News Stories Archive
Mentor Graphics Corp. announced the immediate availability of its new Mentor EZ-VIP PCI Express Verification IP, which reduces testbench assembly time for ASIC and FPGA design verification by a factor of up to 10X.
A new hardmask material, called Saphira, and accompanying processes was introduced Applied Materials. The material, which is transparent and offers high selectivity and good mechanical strength, could reduce manufacturing costs by 35% per module.
China and US boost industrial semiconductor market growth; Global notebook PC market grows; Book-to-bill report shows another month below parity; Holst Center and Cartamundi develop NFC IGZO TFT for gaming; Combo MEMS sensors continue their growth; SEMI announces keynote speakers
Holst Centre, imec, and Cartamundi work on flexible Near Field Communication tags embedded in paper cards.
Applied Materials reported today that its long-pending merger with Tokyo Electron Ltd. may not close until the first quarter of 2015.
New blogs address the challenge of ensuring that manually-designed interconnects will survive ESD events, Nanium’s eWLB fan out technology, The Lanza challenge, Moore’s Law 2.0, Mike Splinter’s pioneer business leader award, and the FD-SOI forum in Shanghai.
GlobalFoundries acquires IBM’s semi business; Mergers and acquisitions shake up automotive semi supplier landscape; Adlyte achieves performance benchmark for EUV light source; Gigaphoton achieves 3-hours of continuous operation of its EUV light source; Book-to-bill ratio declines in September
New blogs delve in the challenges of IC verification for automotive electronics, the need for higher purity and better-characterized electronic materials, SEMI’s recent Strategic Materials Conference, the IoT and need for security, IBM’s work on graphene, the polymer dielectric market, a recent IMAPS workshop, the Nobel Prize in physics and FD-SOI at Semicon Europa.
Wearable sensors market expanding; Intermolecular appoints new president and CEO; Qualcomm to acquire CSR, Texas Instruments ships more than 22 billion units of copper wire bonding tech; Element Six develops new thermal grade diamond substrate
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.