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SPIE Advanced Lithography conference concludes

Exposures, and reducing their cost, were a theme running through the 2015 SPIE Advanced Lithography Symposium this week in San Jose, Calif., the center of Silicon Valley.

Learning to live with negative tone

In lithography for manufacturing semiconductors, a negative tone can be a positive attribute.

Directed Self Assembly Hot Topic at SPIE

At this week’s SPIE Advanced Lithography Symposium in San Jose, Calif., the hottest three-letter acronym is less EUV and more DSA, as in directed self-assembly.

Proponents of EUV, immersion lithography face off at SPIE

The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium. EUVt lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and TSMC. On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.

SPIE plenary takes in photonics, 3DICs, connected devices

Speakers at the plenary session of the SPIE Advanced Lithography conference covered a wide variety of topics, from photonics to 3D chips to the Internet of Things, on Monday morning, February 23, in San Jose, Calif.

Complexity is the Theme at Lithography Conference

Nikon and KLA-Tencor put on separate conferences in San Jose, Calif., on Sunday, February 22, tackling issues in advanced optical lithography. The overarching theme in both sessions was the increased complexity of lithography as it approaches the 10-nanometer and 7nm process nodes.

Blog review January 26, 2015

News blogs report on Scott McGregor’s talk at ISS (where he said exponentially rising costs will bring major changes), robust design with IP, FinFET day at IEDM, multiferroic switches, the RAMI act, IEEE 3DIC conference, SOI at IEDM, and the CES show.

Blog review December 16, 2014

News blogs delve into TSMC’s announcement of EUV production orders, the International Electron Devices Meeting (IEDM), The 4th Annual Global Interposer Technology Workshop, new MRS awards, electronic materials challenges, FD-SOI, ESD and the recent IMAPS conference.

Mentor Graphics Announces New Verification IP for PCIe 4.0

Mentor Graphics Corp. announced the immediate availability of its new Mentor EZ-VIP PCI Express Verification IP, which reduces testbench assembly time for ASIC and FPGA design verification by a factor of up to 10X.

Applied Materials Introduces New Hardmask Process, Saphira

A new hardmask material, called Saphira, and accompanying processes was introduced Applied Materials. The material, which is transparent and offers high selectivity and good mechanical strength, could reduce manufacturing costs by 35% per module.