Marie Semeria, chief executive officer of CEA-Leti (http://www.leti.fr/en), sat down with SemiMD during SEMICON West to discuss how the French R&D and pilot manufacturing campus—located at the foot of the beautiful French alps near Grenoble—is expanding the scope of it’s activities to develop systems solutions for the Internet-of-Things (IoT).
News Stories Archive
Linde Electronics and Specialty Gases has made yet another investment to support its vertically integrated neon supply chain, by adding neon production capability to the company’s largest US based atmospheric gases unit (ASU) in La Porte, Texas, which produces oxygen, nitrogen and argon for the petroleum and petrochemical markets in the Houston area.
The Internet-of-Things (IoT) will require components that can sense the world, process and store data, and communicate autonomously within a secured environment.
Applied Materials, Inc. introduced its next-generation e-beam inspection system, PROVision, that offers resolution down to 1nm.
Selectra chamber uses downstream plasma on Producer platform.
Mentor Graphics Offers Tanner Calibre One Verification Suite for the Tanner Analog/Mixed-Signal IC Design Environment
The Tanner Calibre One IC verification suite is now an integral part of the Tanner analog/mixed-signal (AMS) physical design environment
Mentor Graphics Corporation announced that customers and ecosystem partners are expanding their use of Calibre Pattern Matching solution to overcome previously intractable IC verification and manufacturing problems.
Mentor Graphics Corp. announced that Samsung Foundry’s Closed-Loop DFM solution uses production Mentor Calibre and Tessent platforms to accelerate customer yield ramps
Applied Materials recently launched two new products aimed at reducing contact resistance and improving yield in tungsten contacts.
Amkor and Cadence to Develop Packaging Assembly Design Kits for Amkor’s SLIM and SWIFT Packaging Technologies
Amkor Technology, Inc., a outsourced semiconductor packaging and test service provider, today announced the expansion of its collaboration with Cadence Design Systems, Inc. to streamline semiconductor package verification with the joint development of a package assembly design kit (PADK) for Amkor’s SLIM and SWIFT advanced fan-out package technologies.
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.