Expert panel discussion at Critical Materials Council (CMC) Conference
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Expert panel discussion at Critical Materials Council (CMC) conference.
EUV, cobalt contacts, are expected to be introduced at the 7nm node by several semiconductor manufacturers.
Mentor Graphics Corp. today announced that it has joined GLOBALFOUNDRIES’ FDXcelerator Partner Program.
Linde Korea acquires Air Liquide Korea’s industrial merchant and electronics on-site and liquid bulk air gases business
Linde Korea, a member of The Linde Group, today announced that it has completed the takeover of Air Liquide Korea’s industrial merchant and electronics on-site and liquid bulk air gases business in South Korea.
With good data retention and speed, and medium density, MRAM may have advantages for systems which have large amounts of on-chip SRAM.
ASML funds Zeiss for anamorphic >0.5 NA.
“Engineers are busy, and so you only tell them something they need to know.” Intel’s Steve Chadwick
Mentor Graphics Corporation (NASDAQ: MENT) has signed a multiyear license agreement with ARM to gain early access to a broad range of ARM Fast Models, Cycle Models and related technologies.
Analysts see another chance for Silicon-on-Insulator technology, as proponents claim technical and cost advantages for fully-depleted SOI.
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.