A*STAR and industry partners launch joint labs; Peregrine and RF Micro Devices settle outstanding claims; Micron wins award for 16nm NAND flash memory; Analog Devices completes acquisition of Hittite; Reviews of SIF from SEMICON West 2014
News Stories Archive
New blogs discuss the best way to verify multi-IP, multiple power domain SoCs, contemplate what TSMC may have changed in 20nm devices from the 28nm generation, what happens when we run out of room “at the bottom” around 4nm, the recent EUV lithography workshop, presentations from The ConFab last month, and Qualcomm’s perspective on 3D integration.
New blogs give several different perspectives on Moore’s Law and the potential for continued scaling, the persistent uncertainty of EUV lithography, the VLSI Symposia and FD-SOI, and the recent Suss Technology Forum.
New blogs review positive comments at The ConFab last week by IBM’s Gary Patton; next week’s Silicon Innovation Forum to held in conjunction with SEMICON West; an interview with Laurent Malier, CEO of CEA-Leti, and news of Intel’s debut of the Xenon Phil processor “Knights Landing” in 2015.
Book-to-bill remains consistent; Inpria receives additional investments; Entegris inaugurates new i2M Center; memsstar relocates to new facility; GS Nanotech announces plan to launch mass assembly of 3D stacked TSVs; Cadence completes acquisition of Jasper Design
New blogs give a preview of an upcoming MEMS webcast; look at the Synopsys Galaxy Design platform’s support of FD-SOI; presentations from the recent Symposium on Polymers; SEMI’s role in supporting legislation in the U.S., Qualcomm’s call for monolithic 3D; and why some companies still struggle with predicting financial operational performance.
2014 and 2015 to be growth years; Flat-panel display shipments increase; News from the 2014 Symposium on VLSI Technology; Release of new UVC LEDs; Dow Corning’s new grading structure for power electronics industry
Fab equipment spending set for historic increase; SID unveils award winners; SIA shows semi sales for April; Imec to collaborate with Samsung; Synopsys and Intel collaborate on SoC design enablement
New blogs address the Internet of Things, which TSMC’s John Lin sees as the next big thing after mobile devices; Applied Materials’ new Volta system design around cobalt liners and capping layers; Soitec’s Christophe Maleville’s view on FDSOI; the recent SEMI 2.5/3D IC forum in Singapore; questions surrounding EUV lithography’s insertion into volume manufacturing, and the MEMS Industry Group’s Conference in Japan.
Applied Materials enables cost-effective vertical integration of 3D chips; STATS ChipPAC introduces robust encapsulated wafer level packaging technology; Global semiconductor leaders develop plan to promote worldwide industry growth; IEDM announces 2014 Call for Papers; Strategic investors to connect with startups at SEMICON West event; Bob Metcalfe to keynote
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.