As you might guess from the company’s name, memsstar is involved in microelectromechanical system (MEMS) devices. The company offers manufacturing equipment for “MEMS-specific production,” says CEO Tony McKie.
News Stories Archive
Optimal+ has been in business since 2005. The Israel-based company, which has offices around the world, has something else to celebrate this year: Frost & Sullivan gave Optimal+ its 2015 Global Semiconductor Test Visionary Innovation Leadership Award.
Tanaka Precious Metals, a company dating back to 1885, is a leading supplier of gold bonding wire and other types of bonding wire for semiconductor packaging. It also specializes in electroplating equipment, unveiling a new system for research and development applications at SEMICON West 2015.
A metropolitan area in the center of the state is putting together a public-private partnership to attract high-tech companies, convincing them to set up shop and create jobs. Part of the attraction is a big public university, engaging in advanced research.
FlexTech Alliance updates on substrates, processes, and devices.
Silicon wafers. Semiconductor packaging. These are commonly known products in materials for manufacturing and assembling microchips. Process gases? Not as familiar a commodity, yet they are just as critical to semiconductor manufacturing.
CoorsTek made one of the biggest acquisitions of its century-long history late last year in purchasing Covalent Materials, formerly known as Toshiba Ceramics.
Mentor Graphics Corp. released the Veloce® Power Application software that enables accurate, timely and efficient power analysis at the system, RTL and gate level for complex SoC designs.
There are four reasons why parasitic parameter extraction is getting a lot harder for 16nm and below technology nodes: 1) 3D device geometries, such as the finFET, which result in more complex electrical fields around the device 2) multi-patterning, which causes increased variability; 3) a demand for 10X tighter levels of accuracy, and 4) increased levels of secrecy from foundries and designers.
At Display Week 2015, bigger is better. Smaller is better. And flexible may be best of all, for the era of wearable electronics.
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.