Intel releases new packaging technologies; Fairchild Semiconductor to close two facilities; KLA-Tencor introduces new metrology tools; UMC joins Fujitsu’s new foundry company; Thinnest-possible semiconductor; SEMI announces keynotes for Vietnam Semiconductor Strategy Summit
News Stories Archive
Collaboration for next-generation smart glasses; Book-to-bill ratio holds steady in July; Intel and Unity to collaborate; MediaTek launches new R&D facility; Amkor appoints new member to board of directors; STATS ChipPAC achieves shipping milestone
New blogs give a deeper look at the ASML/IBM announcement on EUV, Samsung’s V-NAND vertical flash, warpage in packaging as discussed at ECTC, embedded software, an IoT infographic and the puzzle of chip design.
The growing semiconductor market in India; MEMSIC’s monolithic, wafer-level packaged accelerometer; Si2 adds new director of 3DIC Programs; Worldwide silicon wafer area shipments increased during the second quarter 2014; LightFair announces Call for Speakers
New blogs report on the silicon innovation forum held at Semicon West, and the Entegris-sponsored yield forum also at Semicon West, , Apple’s acquisition of LuxVue, SOI papers presented at the VLSI Symposia and the controversial results that IBM reported using ASML’s EUV tool (hint: read the comments).
Wireless connectivity semiconductors set for double-digit growth; New benchmark established for EUVL; Cambridge Nanotherm appoints new CEO; Smart cities on the rise; TriQuint Semiconductor is first GaN RF chip manufacturer to achieve MRL 9
A*STAR and industry partners launch joint labs; Peregrine and RF Micro Devices settle outstanding claims; Micron wins award for 16nm NAND flash memory; Analog Devices completes acquisition of Hittite; Reviews of SIF from SEMICON West 2014
New blogs discuss the best way to verify multi-IP, multiple power domain SoCs, contemplate what TSMC may have changed in 20nm devices from the 28nm generation, what happens when we run out of room “at the bottom” around 4nm, the recent EUV lithography workshop, presentations from The ConFab last month, and Qualcomm’s perspective on 3D integration.
New blogs give several different perspectives on Moore’s Law and the potential for continued scaling, the persistent uncertainty of EUV lithography, the VLSI Symposia and FD-SOI, and the recent Suss Technology Forum.
New blogs review positive comments at The ConFab last week by IBM’s Gary Patton; next week’s Silicon Innovation Forum to held in conjunction with SEMICON West; an interview with Laurent Malier, CEO of CEA-Leti, and news of Intel’s debut of the Xenon Phil processor “Knights Landing” in 2015.
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.