System-on-a-chip designs are complex endeavors, and they are growing more complicated by the day. Mentor Graphics is cognizant of the many challenges in SoC design and is working to ease the troubles of chip designers.
News Stories Archive
The company, founded in 1967, has a Silicon Systems Group which last year accounted for 66 percent of Applied’s revenue. The SSG includes a number of other wafer fab equipment categories, such as epitaxy, ion implantation, metrology and wafer inspection, rapid thermal processing, and wet cleaning.
“Money (That’s What I Want)” could have been the theme song for playing off the EUV Mask Readiness panel discussion on Thursday morning (October 1) at the SPIE Photomask Technology conference in Monterey, California.
Intel has been working on photomasks for extreme-ultraviolet lithography for more than a decade, and has recently logged significant progress.
Harry J. Levinson, senior director of technology research at GlobalFoundries, took “Lithography and Mask Challenges at the Leading Edge” as the theme for his keynote presentation Tuesday morning, opening the SPIE Photomask Technology 2015 conference in Monterey, California.
New devices, materials, and substrates challenge atomic-scale integration.
The overall theme for the conference was “Materials for a Smart and Interconnected World.” It featured sessions on “Material Enabling Silicon Everywhere”, “New Emerging Materials Technology & Opportunities at the Edge,” sustainable manufacturing, and a panel of executives from semiconductor manufacturers providing “A View from the Fabs.”
Electronic Fluorocarbons LLC and Albemarle Corporation recognized for quality, safety, service and technology performance.
Gary Patton, chief technology officer of GlobalFoundries and head of the company’s worldwide research and development, called for innovation in chip materials in his keynote address on Tuesday at SEMI’s Strategic Materials Conference in Mountain View, Calif.
Mentor Graphics had a hand in presenting two of the 30 papers offered Thursday at Taiwan Semiconductor Manufacturing’s Open Innovation Platform Ecosystem Forum in Santa Clara, Calif.
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.