IFTLE 187 More IBM rumors; Altera FPGAs, IBS Addresses Transistor Costs, ASE / Inotera 3DIC JV
According to the Wall Street Journal GlobalFoundries (GF) “…has emerged as the leading candidate to buy IBMs semiconductor operations.” [link] According to these reports IBM who initially asked for $2B has met with TSMC, Intel and GF. The reports continues that and that TSMC has dropped out of the bidding which exceeded $1B but appears contingent on how much intellectual property IBM includes.
IFTLE readers already knew that GF was the lead candidate [ see “IBM Continues to evolve: Semi business up for sale, moving into the clouds”]. Maybe the WSJ is reading IFTLE ??
Intel / Altera / TSMC
Recent reports indicate that Altera had expanded their foundry deal with Intel to include “multi-die” devices that combine Altera’s Stratix 10 FPGAs and SoCs with DRAM, SRAM, ASICs, processors, and analog chips in a single package.” [link]
This announcement left some in the industry confused.
Let’s review some background…
Recall in March 2012 Altera announced that they were working with TSMC on 2.5D FPGA program (much like their already commercial competitor Xilinx). [“Altera and TSMC Jointly Develop World’s First Heterogeneous 3D IC Test Vehicle Using CoWoSTM Process”]
Then in Feb 2013 Altera announced a foundry agreement with Intel to access their 14nm technology for FPGA production, probably meaning no need for 2.5D.
[see IFTLE 170, “GIT Workshop Debates Substrate Impact on 2.5/3DIC Costs; Altera 2.5D” ]
…but then, in Feb 2014, Intel announced the 14nm technology program was being postponed to 4Q2014/1Q215 [“Intel postponed Broadwell availability to 4Q14”].
…and then there were reports March 5th 2014 that Altera was “… expected to have TSMC fabricate its next-generation FPGA chips using TSMC’s 16nm FinFET+ process, instead of producing the chips using Intel’s 14nm tri-gate transistor technology”
So, I hope that is now clear (tongue-in-cheek) …
Those of you that stay linked to IFTLE know that I have been quoting Handel Jones of IBS for years (literally since 2009) since his analysis of what is happening to the economic infrastructure Re: Moore’s Law makes the most sense of anyone out there. The article he just wrote for EE Times, “FinFETs Not the Best Silicon Road” should be of interest to us all.
His premise is that semiconductor industry growth has historically depended on a reduction in cost per transistor but next-generation chips will not deliver this cost reduction. While next-generation 20nm bulk CMOS and 14nm FinFET process will deliver smaller transistors they will have a higher cost per gate than today’s 28nm bulk CMOS.
Cost will remain higher even as the processes mature. IBS predicts that the traditional cross-over point for the newer generation technology will not happen (point at which newer not becomes cheaper, per transistor, than older node. The cost per gate for 28nm bulk CMOS will be much lower than FinFETs even in the fourth quarter of 2017. A similar pattern will occur for 20nm bulk CMOS in 2018 or 2019 when depreciation costs decline.
Jones indicates that the 20nm node issues include:
- difficulty achieving low leakage due to challenges in controlling doping uniformity
- line edge roughness
- the need for double patterning
The 16/14nm FinFET node:
- uses the same interconnect structure as 20nm, so the chip area is only 8-10% smaller than 20nm
- faces yield issues related to stress control, overlay, and factors related to the step coverage and process uniformity of 3D structures.
Jones concludes that “..FinFETs can be used for high-performance or ultra-dense designs but are not cost effective in mainstream semiconductors “
ASE, Inotera reportedly to set up 3D IC packaging joint venture
Digitimes has reported that ASE and Inotera are reportedly setting up 3D IC packaging joint venture for handling TSV 3D IC packaging. ASE and Inotera are expected to finalize the deal soon, said the sources, adding that the joint venture is likely to be set up either at a Inotera’s idle plant or at a ASE plant in Chungli, Taiwan.
Initial production goals are reportedly 10,000 3D IC chips a month, and should include Aps (application processors) and mobile RAM chips.
DIgitimes sources add that they expect the JV to compete with TSMC in the 3DIC packaging sector.
Inotera, incorporated in 2003, is a joint venture between Nanya Tech (an affiliate of the Formosa Plastics Group) and Micron.
Inotera has two 300mm fabs with a combined capacity of approximately 120 thousand wafer starts per month providing 300mm DRAM foundry services. According to the supply agreement between Inotera and Micron Technology, Inotera sells substantially all of its manufacturing output to Micron.
For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…