Terry Hook of IBM recently contributed an article to ASN about FinFET isolation issues on bulk vs. SOI.  It generated immense interest, and created lots of discussion on various LinkedIn groups.  In case you missed it, here it is again.

(This article is based on an in-depth presentation Terry gave at the SOI Consortium’s Fully-Depleted Tech Workshop, held during VLSI-TSA in Taiwan, April 2013.  The complete presentation is freely available on the SOI Consortium website.)

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FinFET Isolation Considerations and Ramifications — Bulk vs. SOI

By Terence Hook, Senior Technical Staff Member, IBM Semiconductor Research and Development Center

Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, reliability, and product performance.

BULK VS. SOI BASICS

In bulk wafers, isolation is formed in a manner similar to planar devices, with implanted wells and shallow-trench-isolation oxide separating fins from one another.

With an SOI (silicon-on-insulator) wafer, however, the fins are formed in the silicon layer, the isolating dielectric is already extant, and no well implants are required.

Figure 1: Schematic representation of bulk junction and dielectric-isolated FinFETs

The most important differences in the devices formed in these two manifestations lie in the shape of the fin, the processes that determine the effective fin height, and the presence of doping, which consequently affects the device in many adverse ways such as the variability and the reliability.

The final realization of the full potential of fully-depleted FinFETs is dependent on optimally addressing the issues enumerated herein. Dielectric isolation is shown to provide superior characteristics in all of the above-named aspects. Figure 1 shows a schematic representation of FinFETs for the two isolation architectures, with the various critical points of distinction noted as are discussed below.

FIN SHAPE

Definition of the fins on an SOI wafer is relatively straightforward; vertical fin sidewalls may easily be obtained.

In a bulk-based process, as the spaces between the lower, electrically inactive portions of the fins must be filled with an insulator, some angling of the fin is required to prevent the formation of voids.

Figure 2: Typical bulk junction and dielectric-isolated FinFET fin profiles

Bulk and SOI fin profiles are pictured in Figure 2.  As tapering the fin compromises the subthreshold slope and degrades the effective drive current as well as the output conductance, minimization of the taper is important to the electrical integrity of the device.

BULK: DOPING IN THE FIN

Whereas in an SOI design the transistor-transistor and subfin source-drain current paths are inherently interrupted by the dielectric layer, in a bulk-based process adequate doping for electrical isolation and latchup immunity needs to be established.  This requires additional masking levels and connections for electrical bias.

Conventional design criteria of doping, depth, and overlay tolerances apply to the deep interdevice isolation wells, but suppression of undesired current in the drain-source region has unique features in the FinFET configuration.

Suppression of punchthrough current requires some level of doping at least in the bottom portion of the fin. The adverse effects of doping on mobility and random-dopant-fluctuation have been reported; non-uniform doping is particularly egregious as it increases capacitance without a concomitant increase in drive current.

However, the level of doping required depends on the alignment of the gate and the source junction depth. An optimum choice for the conjunction seeks to minimize the dopant required while respecting physical process window constraints (see Figure 3).

Figure 3: Short-channel effects as a function of doping and gate recess depth relative to the source junction depth in bulk FinFETs

Another adverse effect of doping in the fin is the implication for the gate work function. For junction-isolated FinFETs, the gate metal work function is established so as to provide the desired threshold voltage in the presence of doping; for undoped dielectric-isolated FinFETs the appropriate work function is closer to midgap, which reduces gate leakage and improves reliability.

Figure 4: Voltage operating range as a function of fin doping

Between RDF-driven Vmin and work function-driven Vmax, the operating window of bulk FinFETs is more limited than that of undoped SOI FinFETs (see Figure 4).

PRODUCT AND CIRCUIT DESIGN CONSIDERATIONS

Designing with planar bulk technology has historically differed from planar SOI technology in three aspects: well contacts, self-heating, and floating body effects.

At the expense of area, planar bulk technology has enjoyed the advantages of controlling the threshold voltage through the well potential.  No such benefit exists in bulk FinFET devices, as it is not possible to influence the transistor through the well bias except in the spurious and undesirable region below the active fin.

In fully-depleted devices the concept of a floating body (charge storage in an isolated neutral region) is not applicable, so SOI and bulk FinFETs behave the same way for all switching scenarios.

Self-heating effects, while not important for fast switching operation, can be relevant for DC circuits. While large-area planar structures will continue to enjoy the advantage in thermal conduction relative to SOI traditionally observed, bulk and SOI FinFETs have very similar self-heating characteristics, as the only difference in thermal conductance is a tall, thin sliver of silicon, which provides only a small increase in thermal conductance.

While bulk FinFET technology has lower soft error rates than planar bulk technology, SOI FinFETs are better yet.

VARIATIONS

Fin height variation has a much more serious impact than the planar analog of transistor width variation. Wide transistors (i.e., many fins) have the same variation as narrow (i.e., few fins).

Figure 5: Calculated dependence of SOI and bulk transistors on key process variations, and relative variations in the two architectures

Whereas in the SOI-based version the electrical fin height is determined by the starting silicon thickness, in the bulk-based FinFET process the fin height is determined by several processes, and the distinction between “active” and “inactive” fin is blurred by the conjunction of the gate alignment with the source junction.

The sensitivities to various key variables have been calculated with hardware-calibrated 3D simulations, and the variation of those key parameters determined with respect to state-of-the-art processes (see Figure 5).

The fin variation-driven performance tolerance of a bulk FinFET is larger than that of an SOI FinFET.   That benefit of SOI is not only found in sort yield and worst-case design corners, but smaller variation within a chip enables a faster chip for any given level of leakage.

CONCLUSION

Complete realization of the benefits of fully-depleted transistor architecture is affected by the choice of isolation. Increased range of operating voltage, process simplification, reduced variation, lower soft error rate, and higher circuit density are all features of a dielectric-isolated architecture.

For these reasons the ability of an SOI-based FinFET to reap the full benefits of fully depleted transistors is demonstrably superior to a doped, bulk-based implementation.

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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The 2013 Common Platform Technology Forum showcased “the latest technological advances being delivered to the world’s leading electronics companies,” so of course SOI-based topics were well-represented. Happily, those of us who weren’t able to get over to Silicon Valley were able to attend “virtually” via a live stream (which is now reposted – click here to register and watch it yourself).

The Common Platform Alliance is IBM, Samsung and GlobalFoundries, operating, as IBM’s Dr. Gary Patton points out, as a “virtual IDM”.

Here’s a round-up of the SOI-based highlights.

DR. GARY PATTON, VICE PRESIDENT OF SEMICONDUCTOR RESEARCH & DEVELOPMENT CENTER, IBM

In his keynote address, Gary covered the following SOI-based innovations:

Flexible computing with FD-SOI. (Courtesy: IBM, Common Platform Technology Forum 2013)

• FinFETs: As ASN readers know, IBM is driving FinFETs very hard. With ARM & Cadence, they taped out their first 14nm FinFET processor last fall (on SOI). Gary’s talk gave an overview of the evolution of device structures, including PD-SOI (the basis for IBM’s Watson supercomputer), FD-SOI, FinFETs and future structures and materials.

• Wearable electronics & folding displays – IBM has developed a new, low-cost technique that starts with the FD-SOI technology developed with ST and Leti, for manufacturing silicon-based electronics on a flexible, plastic substrate. Gary showed a sample, and said that “research suggests that flexible, affordable electronics can be made with conventional processes at room temperature.”

• Silicon nanophotonics – most all of the industry’s nanophotonics work is on SOI, and IBM is no exception here.  As Gary notes, “…the key innovation isn’t just the technology…it’s the fact that it’s commercial and scalable…”.
• Carbon nanotubes breakthrough – IBM has attained 10,000 working nanotube transistors on a single device using standard semiconductor processes.  As we noted in ASN when this news broke last fall, IBM researchers fabricated trenches made of hafnium oxide onto SOI wafers, which allows the self-assembly by the carbon nanotubes into neat rows rather than a spaghetti-like tangle.

As seen here, carbon nanotubes start on an SOI wafer. (Courtesy:IBM, Common Platform Technology Platform 2013)

MIKE NOONEN, EXECUTIVE VP, GLOBAL SALES, MARKETING, QUALITY & DESIGN, GLOBALFOUNDRIES.

In Mike’s keynote on particularly innovative customers, he covered ST’s FD-SOI technology.  Here are the main points he made about it:

• STMicroelectronics has been a partner in the Common Platform.
• FD-SOI leverages 80% FEOL of the 28nm SLP; the BEOL is identical to 28nm LP.
• “You can really dial-in optimal transistor performance,” he said.  The thin silicon channel introduces “interesting and exciting capabilities”, including:
  - lower leakage, lower capacitance, enhanced latch-up immunity, electrostatic control;
  - speed boost through back biasing;
• This technology is a simpler planar process:
  - reduced masks offsets cost;
  - considerable IP reuse.
• With a nod to Soitec, the world-leader in SOI wafers, he said, “Soitec has been a really enthusiastic evangelist of this technology, and I really want to acknowledge their efforts in making Fully-Depleted over SOI something that the industry has become very excited about.”  He added that they’re joined by MEMC and SEH as SOI substrate suppliers.
• Regarding the roll-out, he concluded, “A PDK of this technology is available this quarter, and GlobalFoundries has partnered with ST for volume manufacturing and will be entering risk production in the 4th quarter of 2013, with volume production in the first half of 2014.”

GlobalFoundries’ keynote highlights FD-SOI. (Courtesy: GlobalFoundries, STMicroelectronics, Common Platform Technology Forum 2013)

HANDEL JONES, OWNER & CEO, INTERNATIONAL BUSINESS STRATEGIES

In a “fireside chat” with Brian Fuller, Silicon Valley Bureau Chief, EETimes, Handel Jones touched on a number of SOI-related topics.  (In case you missed it, Handel recently wrote an excellent article for ASN on FD-SOI vs. Bulk & FinFET economics.) In addition to his general discourse on the impact of design & process issues on cost/gate, the importance of the ecosystem, and general industry outlook, here are some of Handel’s SOI-related observations during the forum chat:

• RF: he is particularly impressed with IBM’s work on RF, which he says is “…doing extremely well.”  As you may have seen previously in ASN, IBM’s CMOS 7RF SOI technology, which the company says offers significant cost advantages to designers of mobile handsets, has been on SOI for over five years.
• FD-SOI: When asked about any single, major disruption on the horizon, he noted that designing with FinFETs for mixed signal is tough, so there may be a delay there.  However, FD-SOI looks very positive, he says. He sees FD-SOI offering lower power, lower cost/gate, re-usable IP and scalability to 14nm.

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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What a great start to 2013: at CES in Las Vegas, ST-Ericsson announced the NovaThor™ L8580 ModAp, “the world’s fastest and lowest-power integrated LTE smartphone platform.” This is the one that’s on STMicroelectronics’ 28nm FD-SOI, with sampling set for Q1 2013.

And it’s a game changer – for users, for designers, for foundries, and for bean counters.  Here’s why.

The NovaThor L8580 integrates an eQuad 2.5GHz processor based on the ARM Cortex-A9, an Imagination PowerVR™ SGX544 GPU running at 600Mhz and an advanced multimode LTE modem on a single 28nm FD-SOI die.

ST-Ericsson’s NovaThor(TM) L8580 on ST’s 28nm FD-SOI features a 2.5Ghz eQuad(TM) app processor with ultra-low power consumption. (Courtesy: ST-Ericsson)

In the eQuad CPU architecture, each processor core can operate as a high-performance core or a very-low-power core, depending on what’s needed at the moment. Since all the eQuad cores can adapt to the needs of the user at any given time, there’s no need for the dedicated low-power cores found in other multi-core CPU architectures. Remember, the 2.5GHz cores in the L8580 are the mobile industry’s fastest, or conversely, at 0.6V in low-power mode, the industry’s most battery-friendly. With all 2.5GHz cores working together, expect blazing high-performance when you’re doing something like browsing the web. But when phone’s your pocket, those cores will take barely a sip of power.

The NovaThor L8580 is essentially a straight port from 28nm bulk to 28nm FD-SOI of the (very successful) NovaThor L8540, with just a bit of tweaking to fully leverage cool things you can do with FD-SOI, like biasing to increase performance and conserve power.

For the folks designing smartphones and tablets (and ultimately for the end-user), that port to FD-SOI gets the NovaThor L8580:

• CPUs running 35% faster and GPU and multimedia accelerators running 20% faster. In terms of multimedia performance, they’re supporting 1080p video encoding and playback at up to 60 frames per second, 1080p 3D camcorder functionality, displays up to WUXGA (1920×1200) at 60 frames per second and cameras up to 20 megapixels. (Hence their use of the descriptive “extraordinary”.)
• 25% less power consumption than rival architectures when running at high-performance  levels – think Cooler Operation.
• A low-power mode can deliver up to 5000 DMIPS at 0.6V – more than enough computing power for the majority of applications in everyday use. A key point here is that it enables stable SRAM operation at 0.6V – have you heard of anyone matching this? The result is that this low-power mode consumes 50% less power to deliver the same performance compared with alternative solutions in bulk CMOS.

It all adds up to big battery savings – this is the extra day CEO Didier Lamouche promised us in Barcelona last year when they announced this chip.

ST-Ericsson has posted an amazing video, filmed live at CES 13. In the first part of the demo (re: high-perf), on a Samsung Galaxy S3, they’ve got the Sky Castle 3D Graphics Demo launching twice as fast on FD-SOI as the bulk equivalent, and hitting 2.8GHz! And in the second demo (re: low power), they’re hitting 1GHz using just 0.636V, which would take 1.1V on bulk.

Design Highlights

For the ST-E designers, most of the IP blocks were directly re-used from the bulk design, so the porting to FD-SOI was extremely simple and fast.

For the manufacturing folks over at STMicroelectronics (and starting this year, at GloFo), FD-SOI is a planar technology that re-uses 90% of the process steps used in 28nm bulk. The overall manufacturing process in FD-SOI is 12% less complex, so they’ve got lower cycle time and reduced manufacturing costs (bean counters take note, please). They also point out that the manufacturing tools for FD-SOI are much simpler than those required for FinFETs.

Wondering what’s next? The 14nm FD-SOI node is already in development, the ARM Cortex-A15‘s  on the radar, and the FD-SOI roadmap is already defined up the 10nm node.

With FD-SOI, you can do much more with body-biasing (aka back-biasing) than you can in bulk (which suffers from too much leakage). Thanks to the ultra-thin insulator layer in FD-SOI, the biasing creates a buried gate below the channel, so it effectively acts like a vertical double gate transistor. This facilitates the flow of electrons, leading to a higher voltage in the body, and faster switching of the transistor. (Image courtesy ST-Ericsson)

With FD-SOI, you can hit higher speeds with lower operating voltages. This is because the buried oxide layer prevents electrons from leaking away as they travel through the channel from the source to the drain (this sort of leakage is a major source of power consumption in 28nm bulk, which depends on doping to handle leakage). Interestingly, this graph shows ST-E going down to 0.5V – which is incredibly impressive. (Image courtesy of ST-Ericsson)

(Image courtesy ST-Ericsson)

(Image courtesy ST-Ericsson)

As the (now award-winning) folks over at ST and Leti described for us a few years ago, designing a good SOC involves using the right blend of low, standard and high-Vt devices according to the target application and how it’s being used at any given time.  The ST-E designers use this feature to apply different voltages independently to the top and the buried gates of the FD-SOI transistor, which effectively changes its characteristics. By choosing optimal combinations of the voltages, the transistor characteristics can be transformed from those of a very high-performance transistor to those of a very low-power transistor. A processing core built up of such transistors can operate as if it were in fact two cores – one optimized for high performance and the other for low power. (You can’t do this with FinFETs, btw.)

Just Posted: FD-SOI video & white paper

Just as this blog was going online, ST-Ericsson posted an excellent, in-depth white paper; and in partnership with STMicroelectroics, a YouTube video detailing the how’s and why’s of FD-SOI.Here are the links — you really don’t want to miss these:

• Multiprocessing in Mobile Platforms: the Marketing and the Reality
In this white paper, ST-Ericsson’s Marco Cornero and Andreas Anyuru “…illustrate and compare the main technological options available in multiprocessing for mobile platforms, highlighting the synergies between multiprocessing and the disruptive FD-SOI silicon technology used in the upcoming ST-Ericsson products.”

• An Introduction to FD-SOI

STMicroelectronics and ST-Ericsson have teamed up on this excellent video, which garnered 1250 views within the first four days of its posting on YouTube. The animations and comparisons highlight why FD-SOI is so fast, and so cool.

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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If you want to cut through the noise surrounding the choices for 28nm and beyond, an excellent place to start is the SOI Consortium’s Fully Depleted Technology Symposium.

As a member of the design and manufacturing communities, this is your chance to see and hear what industry leaders are actually doing. Planar? FinFET? The Consortium’s been doing these symposia during major conferences for going on four years now, and lively debates always ensue.

(Courtesy: Hilton Hotels & Resorts)

This next FD Tech symposium happens the first day of the IEEE’s IEDM conference in San Francisco – Monday, December 10^th at 8:15pm. Conveniently, it’s also taking place in the same building – at the SF Hilton.

Top technologists from STMicroelectronics, ST-Ericsson, IBM, ARM, Altera, LETI, Soitec, MEMC and others will be debating comprehensive Fully-Depleted Technology solutions.

But perhaps most importantly, we’re going to get the first product-level benchmarking results of 28nm FD-planar for mobile SoC and FPGA applications.  That’s silicon proof straight from the companies who are doing it.

If you’ve been following recent ASN postings from STM, ST-Ericsson, IBM and others, you know these folks are really excited about the results they’re seeing.

Here’s a peak at the presentations planned for the symposium:

• Planar Fully-Depleted Technology at 28nm and below for extremely power-efficient SoCs:  SoC level 28nm Planar Fully-Depleted silicon results
  By Joel Hartmann, Executive VP Front-End Manufacturing & Process R&D, STMicroelectronics
• Evaluation and benchmarking of 14nm planar Fully-Depleted Technology for FPGAs
  By Jeff Watt, Ph.D. Fellow, Technology Development, Altera Corporation
• Challenges and comparisons of designing power-efficient SoCs with planar Fully Depleted transistors and FinFETS
  By Rob Aitken, ARM Fellow
• Second-generation FinFETs and Fin-on-Oxide
  By Ed Nowak, IBM Distinguished Engineer and Device Chief Designer, Semiconductor R&D Center, IBM Systems and Technology Group

The presentations will be followed by a Q&A.

Admission is free, but space is limited, so you must reserve in advance – click here to go to the special registration site.

To recap, it’s the:

Fully-Depleted Transistors Technology Symposium
Hilton San Francisco Union Square Hotel (333 O’Farrell St.)
Monday, December 10^th, 2012
8:15pm to 10:30pm

Food & refreshments will be provided.

We won’t all be in San Francisco, so if you can’t get there, the presentations will be posted on the SOI Consortium website (you can also get the presentations from previous events there, too, as well as excellent white papers).

If you do go and want to share your reactions on Twitter, use #FDchipTech and @soiconsortium.

This will be a great event – don’t miss it!

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation.

SEH is a $12.7 billion company, supplying over 20% of the world’s bulk silicon wafers. SEH’s relationship with Soitec goes way back: they were one of the original corporate investors back in 1997, and the first to license Soitec’s Smart CutTM technology for manufacturing SOI wafers.

With its 300mm SOI wafer production fabs in France and Singapore, Soitec has an expandable installed industrial base of two million wafers per year.

As Horacio Mendez, Executive Direct of the SOI Consortium told ASN, “This is a very significant announcement. The substrate supply chain is fully engaged: we have multiple independent suppliers that can clearly meet the market demands for all key sectors, including mobile devices. As the advanced technology nodes ramp, the wafer production is in place; and very importantly, the capacity is expandable to provide maximum flexibility to customers.”

SEH has been manufacturing standard SOI wafers using Smart Cut technology for years. And last year, the company said it had completed development of its ultra-thin BOX (aka UTB — the wafers used for planar FD-SOI) substrates. Nobuo Katsuoka, director of the SOI program at SEH, recently told Semiconductor Manufacturing & Design, “SEH is delighted to deliver the products on request.”

Wafers for FD-SOI (a “planar” “2D” technology) have Angstrom-level uniformity in their ultra-thin layers – so it’s excellent news that the the industry’s two leaders are both supply sources.

SOI wafers for FinFETs (a “vertical” or “3D” technology, for which the top silicon and insulating BOX layer don’t have to be ultra-ultra-thin) have also long been available from Soitec, SEH and other sources.

With respect to this announcement, SEH’s Katsuoka said, “We are very excited about the business opportunities for SOI products, and we look forward to working with Soitec to extend the global supply chain for new products, such as FD-SOI and SOI for FinFETs, which are showing potential benefits in mobile and embedded applications. Our relationship with Soitec has been a very positive and fruitful one, and we are excited to extend that collaboration. The unique features of Smart Cut will enable our two companies to jointly improve global output for existing and new SOI products.”

As Steve Longoria, SVP of WW Business Development at Soitec, told ASN, “The wafer is the front end of the manufacturing process. This announcement is a proof point of new energy for robust, multi-source supply for impending high-volume demand.”

BEYOND LOGIC

The newly announced Soitec-SEH agreement also extends the companies’ commitment to wafers for a broad-range of areas. For example, there are major market opportunities in SOI for RF devices, power, MEMS/sensors, photonics and more.

The agreement also extends to R&D for technologies of the next wave. We might think of Smart Cut as an SOI technology, but in fact it’s really a manufacturing technology that can be applied to a huge range of wafer materials. As a result of the extended agreement, SEH will continue to use Soitec’s industry-defining Smart Cut technology to manufacture SOI wafers.  What’s more, SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), which will allow SEH to further expand its scope of applications.

So with an abundance of opportunities, a robust multi-source supply chain for the front end of the chip manufacturing process, top-quality wafers that enable savings and efficiencies – in short, better end-user value – it’s all systems go for high-volume demand.

This illustration shows how Smart Cut, Soitec’s proprietary engineered wafer technology, works. The industry standard, this revolutionary wafer bonding and layer splitting processes makes it possible to transfer a thin layer of material from a donor substrate to another substrate, overcoming physical limitations and changing the face of the substrate industry. The Smart Cut technology was originally developed by the CEA-Leti. Soitec holds exclusive exploitation of CEA-Leti rights into the Smart Cut technology, including the right to sublicense to SEH. The technology was made viable for SOI high-volume commercial production by Soitec, and is now protected by more than 3,000 patents owned or controlled by Soitec.

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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The 38th annual SOI Conference is coming right up. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.

Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.

This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.

The 2012 IEEE SOI Conference will be held October 1-4 at the Meritage Resort and Spa in Napa Valley, California. (Photo Credit: Rex Gelert)

The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.

(You can get the pdf of the full program & registration information from the website.)

THE PAPERS

ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.

Here’s a rundown of the sessions:

1. Plenary: talks by Soitec and ARM
2. Fully-Depleted SOI: topics include Ground Plane Optimization for 20nm, strain, process & design considerations. GF will present the foundry’s perspective on the move to 28nm FD-SOI and beyond. Also contributors from ST, Leti, Soitec, IBM, GSS/U.Glasgow and more.
3. FinFET and Fully Depleted SOI: topics include Tri-Gate, SOI-FinFET, Flash Memory, strain solutions, flexible Vth. Contributors include Leti, AMD, Soitec, Synopsys, imec, UCL, AIST and UCBerkeley.
4. Poster session: from universities & research institutes supported by industry (IBM, Samsung, etc.)
5. RF and Circuits: topics include high-performance RF, tunable antennas, TSVs. Contributors include Skyworks, ST, Xilinx and leading universities in China.
6. Memory: contributors from IMEP, ST, TI, R&D institutes and academia
7. Novel Devices and Substrate Engineering: topics include nanowires, strained SOI wafers and III-V devices, with contributions from Tokyo Tech, Toshiba, IBM, Soitec, Leti and more.
8. MEMS and Photonics: includes an invited talk by U. Washington on their Intel-sponsored photonics foundry service and papers from MIT and more.
9. RF and Circuits: covering high-voltage, high-temperature, with contributions from Cissoid, IBM, UCL and more.
10. Hot Topics: Fully-Depleted Technology and Design Platforms: six invited talks by ST, IBM, CMP, GF, UC Berkeley and the SOI Consortium.
11. Late News: tbd, of course…

THE COURSES & PANEL

Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.

The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.

Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively, favorite event. This year’s invited distinguished experts — Scott Luning (GF), Ali Khakifirooz (IBM), Yang Du (Qualcomm). and moderator Sorin Cristoloveanu (Grenoble Institute of Technology) – will share their views on the industry’s FinFET roadmap.

All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage,Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI.

To those of us not deeply involved in the research world, much of this may seem to come out of nowhere.  But there’s a lot of history here, and in this blog we’ll take a look at what it’s all about, and connect a few dots.

THE GSS IEDM ’11 PAPER

GSS is a recent spin-off of Scotland’s University of Glasgow – but there’s nothing new to the research community about these folks.  The core GSS-U.Glasgow team has been presenting important papers on device modeling at IEDM (which is one of the most prestigious of our industry’s conferences) and elsewhere for many years.

At the risk of stating the obvious, accurate simulations are incredibly important. Technologists need to be able to predict what results they can expect from different possible transistor design options before selecting the most promising ones.  Then they also need to provide reliable models to designers who will use them before committing chips to silicon.  One of the biggest challenges is predicting variability, which as we all know is getting worse as transistors scale to ever-smaller dimensions.

At IEDM ’11 last December, GSS-U.Glasgow presented Statistical variability and reliability in nanoscale FinFETs. This covered  “A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping…”.  Essentially they concluded that scaling FinFETs on SOI should be no problem – and in fact the statistical variability of a 10nm FinFET on SOI would be about the same as the industry’s currently seeing in 45nm bulk CMOS.

That paper was based on work that the GSS-U.Glasgow team had done on two major European projects: the EU ENIAC MODERN project, and the EU FP7 TRAMS project.  It’s perhaps worth looking a little more closely at what those projects are about – and who’s involved:

• A key objective of the MODERN (for Modeling and Design of Reliable, process variation-awareNanoelectronic devices, circuits and systems) is to develop “effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance”.  Other partners in the project include ST, Leti, NXP, Infineon, Numonyx (now Micron) and Synopsys.
• The objective of the TRAMS (for ‘Tera-scale Reliable Adaptive Memory Systems’) project is “to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort”. Other partners in the project include Intel, imec, and UPC/BarcelonaTech.

THE BLOGS

A few months later, when Chipworks published pictures of the (bulk silicon) Intel 22nm FinFETs, the folks at GSS started a series of blogs that caught the attention of major tech pubs such as EE Times, Electronics Weekly and EDN.  For reference, here are the blogs and basically what they concluded:

• Simulation analysis of the Intel 22nm FinFET (9 May ’12) – using their TCAD simulator GARAND, GSS found the essentially triangular (rather than a rectangular) shape “contributed to worsening of short-channel effects (SCE)”
• Process-induced variability in the Intel FinFETs (6 June ’12) – continued the analysis by looking at process variability, and concluded that there was “a reduction in the on-current by 12-15% compared to rectangular-gate bulk FinFETs”
• FD SOI FinFETS can offer better performance than bulk FinFETs (27 July ’12) asked:
  “Assuming that you can make ideal rectangular bulk and SOI FinFETs, which one will have better performance?”  The answer: SOI.

Specifically, the July 27^th blog indicated that if FinFETs are rectangular in shape, drive current would be 12-15% better.  Would that be easier to do on an SOI wafer? Soitec has argued that their “fin-first” SOI-based approach to FinFET manufacturing will save both time & money while getting better results (see Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET in Semiconductor Manufacturing & Design).

The GSS blog also reminded readers that the company’s CEO and founder, Asen Asenov (an extremely heavy hitter who’s published over 550 papers), has hinted that “…SOI FinFETs with an almost ideal rectangular shape may be a better solution for future FinFET scaling”.  GSS has noted previously that “FinFETs built on an SOI substrate could have significant advantages terms of simpler processing, better process control and reduced statistical variability”.

Fin shape aside, GSS said that by virtue of the layer of insulation, SOI would give another 5% boost to FinFET drive current.  But perhaps more importantly, that layer of insulation in SOI-based FinFETs would deliver on average 2.5 times less leakage – which would translate into a doubling of battery-life for your cell phone.

NEXT PROJECT

IBM has now entered into an agreement with GSS et al on a project called StatDES, for Statistical Design and Verification of Analogue Systems – see last month’s IBM blog by IBM Research Scientist Dr. Sani Nassif, entitled “Fins on transistors change processor power and performance”.

Dr. Nassif writes, “IBM, University of Glasgow and the Scottish Funding Council are collaborating on a project to simulate 3D microprocessor transistors at a mere 14 nanometer scale (the virus that causes the common cold is more than twice as large at 32 nanometers). Using a silicon-on-insulator (SOI) substrate, the FinFET (fin field-effect transistor) project, called StatDES, promises to keep improving microprocessor performance and energy conservation.”

The steering group also includes folks from ST, Freescale, Wolfson and Cadence, so one would guess we’ll be hearing more from this project – and others like it, to be sure – in the future, wouldn’t you think?

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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SOI in general and FD-SOI in particular were hot topics at this year’s Semicon West in San Francisco. A panel discussion by industry thought-leaders gathered to discuss the current challenges facing the mobile industry was among the highlights.  It featured an impressive line-up of key players from the ecosystem at the forefront of fully-depleted, SOI based technologies, including:

• ARM: Ron Moore – Director of Strategic Accounts Marketing, Physical IP Division
• GlobalFoundries: Subramani Kengeri – Vice President of Design Solutions
• IBM: Gary Patton – Vice President of the Semiconductor Research and Development Center
• SOI Industry Consortium: Horacio Mendez – Executive Director
• Soitec: Steve Longoria – Senior Vice President of World Wide Strategic Business Development
• STMicroelectronics: Philippe Magarshack – Technology Research and Development Group Vice President
• UC Berkeley: Chenming Calvin Hu, Ph.D. – TSMC Distinguished Professor at the University of California at Berkeley

FD-SOI figured prominently in a panel on mobile challenges held during Semicon West '12. Left to right: C. Hu (UCBerkeley); R. Moore (ARM); H. Mendez (SOI Consortium); G. Patton (IBM); P. Magarshack (ST); S. Kengeri (GF); S. Longoria (Soitec)

Setting the scene, Soitec’s Longoria noted that, “Our industry is now driven by SOCs (where in the past it was CPUs) and we are on much shorter product cycles driven by consumer applications.”

As the first to be bringing out products based on ultra-thin layers of both SOI and insulator, ST’s Magarshack spoke extensively about their planar FD-SOI technology, which will be taping out at 28nm this summer.  He said that they were very confident and would be sharing the results at the end of the year.  He also emphasized their full commitment and close work with GF to enable the ecosystem, which was echoed in comments by GF’s Kengari.

With respect to 28nm, said Mendez of the SOI Consortium, “…the analysis says the cost [of FD-SOI] is equivalent to or even lower [than bulk silicon].”

IBM’s  Patton concurred, saying that, “When you’re dealing with an FD-SOI wafer, we see a big key advantage in manufacturability and time to market.”

Asked how FD-SOI would impact end-users, ARM’s Moore responded that mobile is about saving power.   FD-SOI provides a low-power bedrock, and with the headroom, the back-biasing option lets you add incredible performance.  “We see a valuable flow with FD-SOI & FinFET from devices down to servers,” he said.

In conclusion, UCBerkeley’s Hu said, “I’m very confident FD-SOI and FinFET are going to serve the industry quite well.”

The panel was followed by a great party held by leading SOI wafer manufacturer Soitec, to celebrate their 20th anniversary.

Earlier in the day, the show’s TechXpot series lead off with Enabling Sub-22nm with New Materials and Processes.  It was packed – with all the chairs taken, people were sitting on the floor in the aisles and crowded four-deep all around the edges. In his presentation on the  “Convergence of Engineered Substrates and IC Devices for Mobile Applications”,  Soitec CTO Dr. Carlos Mazure reminded us that mobile is really many technologies: in addition to the digital side, there’s RF, imaging, MEMS and memories – all of which can (and many do) benefit from SOI and other advanced engineered substrates. They’re not all on the leading edge, but when it comes to battery life, they all count.

At another presentation, Leti’s FD-SOI Manager with the IBM Alliance Maud Vinet covered their leading-edge research on FD-SOI.  She says that they’ll be presenting exciting results at IEDM in December, so watch this page for that.

All in all, it was a good show for the SOI ecosystem, full of energy and renewed enthusiasm.

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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As I blogged here on SemiMD last week, STMicroelectronics has announced that to supplement in-house production at their fab in Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices.  ST will also open access to its FD-SOI technology to GlobalFoundries’ other customers.  High-volume manufacturing will kick off with ST-Ericsson’s ARM-based 28nm NovaThor.

Prior to the announcement, the STM published a white paper explaining why they were forging ahead on FD-SOI.  It’s an excellent paper, providing benchmarks and design considerations.

As they explained in the Executive Summary: “Planar FD is a promising technology for modern mobile and consumer multimedia chips. It combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolution from conventional planar bulk CMOS – and there is little disruption at the design level, too. At 28nm, we find that planar FD more than matches the peak performance of “G”-type technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors. Looking further, for 20nm and 14nm, we believe planar FD will be extremely competitive with respect to alternative approaches in terms of performance and power, while being both simpler and more suited to low-power design techniques. In short, a better choice for the type of SOC we offer. Planar fully depleted silicon technology will be ready as early as 2012 to compete in the forthcoming superphones era and in many other consumer segments.”

With the ST/GF news that other GF customers will have access to the ST technology, those in the fabless community will no doubt be wanting to learn more about what’s on offer.  If you have time, you can download the entire ST white paper from the SOI Consortium: Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond.

The ST team that wrote it also wrote a summary version, which first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization.  In case you missed it there, here it is again.

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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

By Philippe FLATRESSE, Program Manager for Fully Depleted SOI Technology, STMicroelectronics; Giorgio CESANA, Director of Technology Marketing at STMicroelectronics; and Xavier CAUCHY, Digital Applications and Strategic Marketing Manager at Soitec.

Having identified that conventional planar bulk CMOS would not meet all the requirements of mobile and consumer multimedia System-on-Chip (SOC) ICs in the coming years, STMicroelectronics assessed alternative options. It is possible to propose a 28nm planar FD solution available as a second generation shortly after readiness of traditional 28nm on bulk silicon, with better time-to-market than waiting for availability of the 20nm node. It is also an excellent learning step to prepare a 20nm planar FD process. Our evaluations show that 20nm planar FD has also a very competitive potential performance-wise vs. FinFET for System-on-Chip applications.

Figure 1: ST’s planar FD device structure features (notional perspective, notional cross-section, TEM cross-section)

Technology overview:

• Immunity to Short Channel Effects and variability (no channel doping, so no Random Doping Fluctuations / RDF)

• For the 28nm node, the selected BOX thickness is 25nm.

• Ultra-thin BOX advantages include:

  - further improved electrostatic control and relaxed thinness requirement of the top silicon,

  - enables back-biasing through the BOX,

  - enables the implantation, during the fabrication process, of heavily doped “ground planes” or “back-planes” under the BOX, for improved electrostatics and/or VT adjustment and/or best-efficiency of back-bias,

  - brings the ability, during the fabrication process, to locally remove the top silicon and BOX to reach the base bulk silicon and co-integrate a few (non geometry-critical) devices on Bulk with devices on SOI – with a small step height between an SOI zone and a Bulk zone, compatible with lithography tools.

• BOX offers total dielectric isolation of the very thin active layer and naturally ultra-shallow junctions, leading to lower source/drain capacitance, lower leakage and latch-up immunity.

Planar FD technology allows several methods for setting the threshold voltage VT, including engineering the gate stack work function, trimming the gate length and other process engineering techniques. Thanks to this, STMicroelectronics’ 28FDSOI technology is capable of offering 3 VTs (HVT, RVT, LVT), as in traditional bulk CMOS technologies.

Circuit-Level Benchmarking

To assess how the improved planar FD-SOI transistor characteristics translate at the circuit level, STMicroelectronics has benchmarked a number of representative IP blocks, including an ARM Cortex-A9 CPU core. To that aim, we have extracted logic critical paths with associated RC parasitics from placed-and-routed designs and have re-characterized them by swapping 28nm traditional bulk CMOS transistor SPICE models with 28nm planar FD SPICE models.

With test chips in our 28nm planar FD technology becoming available, we are demonstrating that the models predict well the silicon behavior. We are therefore confident that the benchmarks presented below are reliable and will be matched by SOC implementations.

The benchmarks compare the merits at the 28nm node of ST’s planar FD technology (“28FD”) with a state-of-the-art Low-Power technology (“28LP”) and a more performance-oriented, state-of-art General Purpose technology (“28G”). They are all based on evaluation of an ARM Cortex-A9 core. The analysis focuses on the higher end of the range of operating frequencies found in a SOC, since modern mobile and consumer multimedia demand high performance from their master CPU (for example, a Cortex-A9 or the forthcoming A15).

Performance at nominal Vdd : best speed/leakage trade-off: 28FD consistently outperforms both 28LP and 28G (Figure 2).

Figure 2: Best operating frequency for any class of leakage (TT process, 85C)

Excellent speed/leakage ratio maintained at reduced Vdd : reducing Vdd is a very good way to save dynamic power. It is therefore realistic to envisage building 28FD chips that match 28G or 28LP performance at a fraction of the power consumption.

Leading-edge performance across the full Vdd range: 28FD exhibits outstanding performance at all practical Vdd values. In particular, when maximum circuit speed is sought, only the low- and ultra-low-VT flavors of 28G compare with 28FD LVT; however they are much leakier and more limited in terms of, e.g., Vdd overdrive they can withstand without reliability concerns.

Best Power Efficiency Across Use Cases: the 28FD technology is power-efficient across the full Vdd and target frequency range (Figure 3). Contrary to G-type technology, with 28FD a given logic circuit that is power-efficient with Vdd set to reach a certain operating frequency (say, 2GHz range) remains efficient with Vdd set for a different target frequency range (e.g., sub-1.5GHz).

Figure 3: Power efficiency across all use cases (TT process, WC temp)

Focus on SRAM: The bitcells proposed in 28FD technology have very competitive cell current (Icell) vs. standby current ratio, which is representative of the performance/leakage power trade-off for SRAM arrays (Figure 4). This is true for all bit cells flavors: high-density and low-leakage oriented, or high-speed oriented. The footprint of the 4 bitcells proposed in 28FD is the same as that of the 4 bitcells proposed in 28LP.

Figure 4: SRAM memory bit cells performance/leakage. The power supply of 28FD SRAM arrays can be lowered by 100mV from nominal and still match the performance of 28LP SRAM arrays operated at nominal Vdd, while offering a 2x to 5x reduction in leakage power.

Commonalities with 28nm LP Bulk

STMicroelectronics’ strategy when developing the 28nm planar FD technology has been to reuse as much as possible the 28nm low-power bulk CMOS process.

Overall, the Back-End is 100% identical to the traditional 28nm bulk low-power CMOS process, and the Front-End of Line (FEOL) is 80% common with that same process.

The planar FD process saves about 10% of the steps required to fabricate the chips on the wafers. This approximately offsets the cost overhead of the starting wafers. As a result, the 28nm planar FD technology matches the cost of a conventional low-power technology while delivering extremely competitive performance.

Design Considerations

Designing on planar FD requires specific extraction deck and SPICE models. Apart from that, the design flows, methodologies and tools do not need any adaptation that would be specific to planar FD (Figure 5).

Figure 5: ST’s SOC implementation flow outline

SPICE Models: SPICE compact models have been developed for accurately representing planar FD transistors. The model we use is now integrated in all major commercially available simulators, such as Mentor’s ELDO, Synopsys’ HSPICE and XA or Cadence’ SPECTRE. A model card has been extracted for all transistors and other devices available in our 28nm planar FD technology.

Flow and Design Platform: With adequate SPICE models integrated in the PDK, the design flow is identical to that used with conventional 28nm Bulk CMOS technology. We have developed a full design platform for SOC, re-using work done for 28nm Bulk. It consists of standard cell libraries (multi-channel and multi-VT) with power management elements (power switches, level shifters etc.), embedded memories, analog foundation IP (such as PLLs and the likes) and specialty IP (Antifuse etc.).

A design platform developed for bulk CMOS technology can be ported to planar FD by re-characterization using planar FD SPICE models, which we have done for a variety of back-biasing conditions. Only a limited number of critical IPs need to be tuned or redesigned: Analog IP, IOs, Fuse.

At the SOC level, migrating an existing design from bulk to planar FD represents an effort comparable to half-node migration. It brings very worthwhile benefits at reasonable efforts.

All techniques used in low-power designs are applicable to planar FD. Those that can be enhanced with planar FD include: multi-VT, power switches, reverse and forward body bias, and voltage scaling.

Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied.  Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.

Perspectives

28nm: We expect to sign-off designs breaking the 2GHz barrier under worst-case conditions, in a power-efficient and cost-efficient way. For lower performance targets, there is also the opportunity to design ultra-low-power chips that can fulfill their functional specifications using a very low Vdd, for example in the 0.6-0.8V range. The Process Design Kit (PDK) is available, targeting the technology to be open for risk production by mid-2012.

20nm: We intend to scale our planar FD technology to 20nm, introducing a number of improvements to continue pushing the performance and retain a low power consumption. The objective is to bring up a solution that will improve on what mobile-optimized planar bulk CMOS will achieve, and will be extremely competitive vs. potential FinFET-based approaches for SOC – while keeping a simple and cost-efficient approach. The design rules will be compatible with 20nm bulk CMOS. This technology will bridge the gap to 14nm and provide an interesting alternative to the cost and complexity of introducing Extreme-UV and FinFET structures. Evaluation SPICE models are available, and full PDK is scheduled by end of 2012, with risk production for 13Q3.

14nm: Based on the assessments we have performed, we are confident that the planar FD technology is shrinkable to 14nm. Silicon and buried oxide thickness will need to be reduced to within limits that wafer manufacturers and CMOS process technology can handle.

The following is a special guest post by Dr. Chenming Hu, TSMC Distinguished Professor at UC Berkeley. He and his team published seminal papers on FinFETs (1999) and UTB-SOI (2000). This post first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization. 

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The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations are leading to high leakage (Ioff) and supply voltage (Vdd),  resulting in excessive  power consumption and design costs. While these challenges have been increasing over time, they’ve finally gotten painful enough that the industry is ready to embrace new transistor structures.

The essence of the problem is that the leakage current does not flow along the Si-oxide interface, but nanometers below the interface  when the gate lengths (Lg) becomes very small. That leakage path is physically far from the gate even if the oxide were infinitely thin. The gate cannot shut off the leakage as if the oxide were nanometers thick. Essentially the MOSFET becomes a resistor. Ioff and variations got worse and worse with Lg reductions.

The solution is new MOSFET structures, in which there is no Si far (more than nanometers) from the gate(s). In other words, the transistor body must be ultra thin. Body doping becomes optional.

Both FinFETs and FD-SOI devices are ultra-thin-body transistors. As such, compared to traditional planar bulk CMOS, they both provide:

• Higher speed and lower leakage
• Lower supply voltage (Vdd) and power consumption
• Further scaling and lower cost
• Better sub-threshold swing and scaling
• No random dopant fluctuation (RDF), less variability
• Better mobility, especially for future sub-threshold design

FinFET

The FinFET body is a thin fin and the thin body is controlled from three sides instead of just the top.

FinFET is easy to scale because leakage is well suppressed if the fin thickness is equal to or less than Lg. Thin fins can be made with the same gate patterning/etching tools.

While our original FinFET work was on SOI wafers, a few years later (2003), Samsung presented a way to manufacture them on bulk substrates. There is an advantage to continued use of  bulk substrates; however, FinFET on bulk requires heavy implant below the fin to suppress leakage and that requires tradeoffs with FinFET performance.

When built on SOI, the FinFET does not suffer from leakage below the fin. Building FinFETs on SOI also confers certain advantages in simplifying manufacturing. The choice will be made by performance and comparisons.

Planar FD-SOI

Planar FD-SOI requires SOI wafers with a very, very thin top layer of silicon.  When we first invented the concept in 2000, the availability of such SOI substrates was the major obstacle. The final silicon layer thickness had to be about a quarter to a third of the gate length.

However, Soitec has surmounted the wafer challenge and with that, commercial production can now become a reality.

The FD-SOI approach can save the fabs and designers significant investment. Existing chip designs and associated IP can be ported with minimum effort, starting today at the 28nm node.

While FinFETs have a larger Ion, FD-SOI has a good back-gate bias option, which make it particularly interesting for low-power applications.

Conclusion

This is a very exciting time for the industry. Although it may seem that the industry is splitting into FinFETs and FD-SOI camps, both approaches use body thickness as the new scaling parameter, and can use undoped body for high performance chips without RDF. Both allow MOSFETs to be scaled beyond traditional MOSFET’s limit. And both can derive substantial benefits from SOI wafers. Real choice is good news because competition will bring the best out of both new transistor technologies.

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