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Posts Tagged ‘verification’

Mentor Graphics U2U Meeting April 26 in Santa Clara

Monday, April 11th, 2016

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Mentor Graphics’ User2User meeting will be held in Santa Clara on April 26, 2016. The meeting is a highly interactive, in-depth technical conference focused on real world experiences using Mentor tools to design leading-edge products.

Admission and parking for User2User is free and includes all technical sessions, lunch and a networking reception at the end of the day. Interested parties can register on-line in advance.

Wally Rhines, Chairman and CEO of Mentor Graphics, will kick things off at 9:00am with a keynote talk on “Merger Mania.“ Wally notes that in 2015, the transaction value of semiconductor mergers was at an all-time historic high.  What is much more remarkable is that the average size of the merging companies is five times as large as in the past five years, he said. This major change in the structure of the semiconductor industry suggests that there will be changes that affect everything from how we define and design products to how efficiently we develop and manufacture them. Dr. Rhines will examine the data and provide conclusions and predictions.

He will be followed by another keynote talk at 10:00 by Zach Shelby, VP of Marketing for the Internet of Things at ARM. Zach was co-founder of Sensinode, where he was CEO, CTO and Chief Nerd for the ground-breaking company before its acquisition by ARM. Before starting Sensinode, Zach led wireless networking research at the Centre for Wireless Communications and at the Technical Research Center of Finland.

After user sessions and lunch, a panel will convene at 1:00pm to address the topic “Ripple or Tidal Wave: What’s driving the next wave of innovation and semiconductor growth?” Technology innovation was once fueled by the personal computer, communications, and mobile devices. Large capital investment and startup funding was rewarded with market growth and increased silicon shipments. Things are certainly consolidating, perhaps slowing down in the semiconductor market, so what’s going to drive the next wave of growth?  What types of designs will be staffed and funded? Is it IoT?  Wearables?  Automotive?  Experts will address these and other questions and examine what is driving growth and what innovation is yet to come.

Attendees can pick from nine technical tracks focused on AMS Verification, Calibre I and II, Emulation, Functional Verification, High Speed, IC Digital Implementation, PCB Flow, and Silicon Test & Yield Solutions. You’ll hear cases studies directly from users and also updates from Mentor Graphics experts.

These user sessions will be held at 11:10-12:00am, 2:00-2:50pm and 3:10-5:00pm.

A few of the highlights:

  • Oracle’s use of advanced fill techniques for improving manufacturing yield
  • How Xilinx built a custom ESD verification methodology on the Calibre platform
  • Qualcomm used emulation for better RTL design exploration for power, leading to more accurate power analysis and sign-off at the gate level
  • Micron’s experience with emulation, a full environment for debug of SSD controller designs, plus future plans for emulation
  • Microsoft use of portable stimulus to increase productivity, automate the creation of high-quality stimulus, and increase design quality
  • Formal verification at MicroSemi to create a rigorous, pre-code check-in review process that prevents bugs from infecting the master RTL
  • A methodology for modeling, simulation of highly integrated multi-die package designs at SanDisk
  • How Samsung and nVidia use new Automatic RTL Floorplanning capabilities on their advanced SoC designs
  • Structure test at AMD: traditional ATPG and Cell-Aware ATPG flows, as well as verification flows and enhancements

Other users presenting include experts from Towerjazz, Broadcom, GLOBALFOUNDRIES, Silicon Creations, MaxLinear, Silicon Labs, Marvell, HiSilicon, Qualcomm, Soft Machines, Agilent, Samtec, Honewell, ST Microelectronics, SHLC, ViaSat, Optimum, NXP, ON Semiconductor and MCD.

The day winds up with a closing session and networking reception from 5:00-6:00pm.

Registration is from 8:00-9:00am in the morning.

Rhines Reviews Four Decades of Design and Verification

Wednesday, March 2nd, 2016

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By Jeff Dorsch, Contributing Editor

The electronic design automation industry is progressing from the “Applications Age” to a new era of field-programmable gate array prototyping where security and safety considerations are coming to the fore, according to Wally Rhines, chairman and chief executive officer of Mentor Graphics, giving the keynote address at DVCon U.S. in San Jose, Calif.

The Mentor CEO, who spent 21 years at Texas Instruments before getting into the EDA business, recalled that back in 1972, “there was no verification,” as chip designers were working on small-scale integration and medium-scale integration circuits that weren’t very complex.

Soon after, the CANCER simulator and the SPICE simulation program were developed, ushering in what Rhines called “verification era 0.0.”

This was followed by the register-transfer language design era of VHDL and the Verilog hardware description language, which he dubbed the “verification 1.0 era.”

As computers grew “faster, bigger,” Rhines said, “simulation became very fast, very productive,” leading to testbenches and “verification 2.0,” he added.

The emulation/simulation/verification segment in EDA increased to more than $1 billion in revenue during 2014, Rhines noted. This led to the “systems era” and “verification 3.0,” with multiple domains, he said.

The industry continues to evolve, from the “Pre-ICE Age” and ICE (in-circuit emulation) Age to the current times, with test creation automation and “the goal of portable stimulus,” the Mentor CEO said.

Going “beyond functional verification,” Rhines cited security as an increasing concern in IC design and verification. He pointed to Beckstrom’s Law of Cybersecurity:

  1. Anything attached to a network can be hacked.
  2. Everything is being attached to networks.
  3. Everything is vulnerable.

Semiconductors are now subject to side-channel attacks, Rhines noted. There are also the issues of counterfeit chips and malicious logic inside the chip. For the latter, the industry will resort to static tests and dynamic detection, he said.

In light of these developments, design and verification is moving to “verifying a chip does nothing it is not supposed to do,” Rhines commented.

Safety is the other big issue in chip design and verification. For automotive vehicles, there is the ISO 26262 standard. In medical equipment, it’s the IEC 60601 standard. And in military/aerospace applications, it’s the D0-254 standard, according to Rhines.

Working with such standards, subject to auditing, calls for fault injection and formal-based fault injection/verification, he said.

DVCon, short for Design and Verification Conference and Exhibition, evolved early in the 21st century from the establishment of verification standards and formation of the Accellera Systems Initiative. Annual conferences are held in Europe, India, and the U.S., with plans for a DVCon China in 2017.

Mentor Graphics Veloce VirtuaLAB Adds Next-Generation Protocols for Leading-edge Networking Designs

Monday, October 19th, 2015

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Mentor Graphics Corp. today announced the Veloce® VirtuaLAB Ethernet environment with support for  25G, 50G and 100G Ethernet. This support enables highly efficient, emulation-based verification for the massive Ethernet-based designs being created today.

The huge surge in demand for connectivity has had a profound effect on the size of switch and router designs, making them among the largest IC designs developed today. The sheer size of the designs, the pressure for early release, and the need to verify all paths are creating a methodology shift that moves verification from simulation- to emulation-based flows.

“Providing a highly scalable, high-density network foundation for our customers’ demanding environments is a top priority as we design Juniper Networks’ advanced switches and routers,” said Debashis Basu, senior vice president of Silicon and Systems Engineering at Juniper Networks. “The cutting-edge features in our ASICs make Veloce VirtuaLAB Ethernet and emulation capabilities a key component for achieving verification convergence, helping ensure that we deliver versatile, high-performance switching and routing technology to keep pace with evolving network requirements.”

VirtuaLAB Ethernet transforms emulation for networking chips by replacing the traditional physical devices used in In-circuit Emulation (ICE) with virtual devices. This virtualization moves emulation from the engineering lab to the computing data center for maximum emulation resource utilization. “It’s a solution to Ethernet lab virtualization. That’s a very big pain point for our networking customers. We’re addressing it very efficiently with the VirtualLAB Ethernet,” said Jean-Marie Brunet, Marketing Director for the Emulation Division at Mentor Graphics Corp.

VirtuaLAB components provide a complete software-driven Ethernet stack that runs at up to 15,000 times the speed of traditional simulation. This lets VirtuaLab Ethernet users tackle the complex challenges of Ethernet-based designs with improved throughput, advanced debug, power analysis and performance analysis.

VirtuaLAB is part of Veloce emulation solutions.

“The rapid development and deployment of high-end Ethernet products for the networking market requires access to high quality IP and complete verification solutions,” said Daniel Kohler, CTO of MoreThanIP. “We have collaborated with Mentor over several years to enable the deployment of robust, fully featured Ethernet verification encapsulated in the Ethernet VirtuaLAB product. Most recently we have collaborated to enable forward error correction (FEC) verification for high-speed 25G, 50G, 100G designs.”

According to the 2015 Ethernet Roadmap developed by the Ethernet Alliance Organization, Ethernet could have 12 speeds before 2020 with 6 new speeds introduced in the next 5 years. The progression of speeds is not in chronological order because 40G and 100G were primarily based on multiple lanes of 10Gb/s technology that was available before 25Gb/s serial technology enabled 25G. Lanes running at 25Gb/s are becoming impractical in 2015 and will be used in 25G SFP+ and 4x25Gb/s 100G QSFP28. The next serial lane is expected to be 50 Gb/s and enable 50G SFP28, 200G QSFP28 (4x50G) and 400G CFP2 (8x50G).

“It’s starting to be a little bit all over the place,” said Brunet. “That’s the reason why we had to expand our portfolio and support different protocols of Ethernet speed.”

Ethernet protocols are evolving in a non-chronological way, driven by the different needs of various applications, such as cloud computing, video and even IoT and automotive. Source Data: EthernetAlliance.Org

The need for bandwidth is driven in different ways by data centers, cloud computing, metro area networks, storage area networks, social networking and video applications. “Video (for example) is driving the need for high bandwidth, fast computation (or the exchange of packets of information),” said Brunet.

The accelerated deployment of VirtuaLab solutions in the networking market is the result of significant and repeatable improvements in throughput. For example, in simulation it’s not uncommon to run 1,000 packets of data per day. When compared to emulation, the difference is staggering. Here customers report they are running 11,000,000 packets of data per day.

“We collaborate with leading-edge networking companies to provide solutions that address their verification challenges. The rapid growth of these designs and the need to verify every path creates a huge verification space resulting in a major shift from simulation to emulation,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “We developed VirtuaLAB Ethernet and other solutions that transform emulation, enabling our Veloce customers to meet their complex verification goals.”

The Veloce emulation platform is a core technology in the Mentor® Enterprise Verification Platform (EVP) – a platform that boosts productivity in ASIC and SoC functional verification by combining advanced verification technologies in a comprehensive platform. The Veloce emulation platform’s success is a result of several factors: high design capacity, speed of execution, and exceptional functionality. Now considered among the most versatile and powerful of verification tools, project teams use emulation for hardware debugging, hardware/software co-verification or integration, system-level prototyping, low-power verification and power estimation, and performance characterization.