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Measuring 5nm Particles In-Line

Monday, November 30th, 2015

By Ed Korczynski, Sr. Technical Editor

Industrial Technology Research Institute (ITRI) ( worked with TSMC ( in Taiwan on a clever in-line monitor technology that transforms liquids and automatically-diluted-slurries into aerosols for subsequent airborn measurements. They call this “SuperSizer” technology, and claim that tests have shown resolution over the astounding range of 5nm to 1 micron, and with ability to accurately represent size distributions over that range. Any dissolved gas bubbles in the liquid are lost in the aerosol process, which allows the tool to unambiguously count solid impurities. The Figure shows the compact components within the tool that produce the aerosol.

Aerosol sub-system inside “SuperSizer” in-line particle sizing tool co-developed by ITRI/TSMC. (Source: ITRI)

Semiconductor fabrication (fab) lines require in-line measurement and control of particles in critical liquids and slurries. With the exception of those carefully added to chemical-mechanical planarization (CMP) slurries, most particles in fabs are accidental yield-killers that must be kept to an absolute minimum to ensure proper yield in IC fabs, and ever decreasing IC device feature sizes result in ever smaller particles that can kill a chip. Standard in-line tools to monitor particles rely on laser scattering through the liquid, and such technology allows for resolution of particle sizes as small as 40nm. Since we cannot control what we cannot measure, the IC fab industry needs this new ability to measure particles as small as 5nm for next-generation manufacturing.

There are two actual measurement technologies used downstream of the SuperSizer aerosol module:  a differential mobility analyzer (DMA), and a condensation particle counter (CPC). The aerosol first moves through the DMA column, where particle sizes are measured based on the force balance between air flow speed in the axial direction and an electric field in the radial direction. The subsequent CPC then provides particle concentration data.

Combining both data streams properly allows for automated output of information on particle sizes down to 5nm, size distributions, and impurity concentrations in liquids. Since the tool is intended for monitoring semiconductor high-volume manufacturing (HVM), the measurement data is automatically categorized, analyzed, and reported according to the needs of the fab’s automated yield management system. Users can edit the measurement sequences or recipes to monitor different chemicals or slurries under different conditions and schedules.

When used to control a CMP process, the SuperSizer can be configured to measure not just impurities but also the essential slurry particles themselves. During dilution and homogeneous mixing of the slurry prior to aerosolization, mechanical agitation needs to be avoided so as to prevent particle agglomeration which causes scratch defects. This new tool uses pressured gas as the driving force for solution transporting and mixing, so that any measured agglomeration in the slurry can be assigned to a source somewhere else in the fab.

TSMC has been using this tool since 2014 to measure particles in solutions including slurries, chemicals, and ultra-pure water. ITRI, which owns the technology and related patents, can now take orders to manufacture the product, but the research organization plans to license the technology to a company in Taiwan for volume manufacturing. EETimes reports ( that the current list price for a tool capable of monitoring ultra-pure water is ~US$450k, while a fully-configured tool for CMP monitoring would cost over US$700k.


InvenSense Developers Conference Tackles Sensor Security, New Technologies

Monday, November 23rd, 2015

By Jeff Dorsch, Contributing Editor

The second day of the InvenSense Developers Conference saw presenters get down to cases – use cases for sensors.

There were track sessions devoted to mobile technology and the Internet of Things, with the latter featuring presentations on industrial and automotive applications, smart homes and drones, smartphones and tablet computers, and wearable electronics. InvenSense partner companies had their own track on New Technologies, fitting into the conference’s “Internet of Sensors” theme.

The conference also featured two developer tracks in parallel, providing five InvenSense presentations on its FireFly hardware and software, SensorStudio, and other offerings.

One of the presentations that wrapped up the conference on Wednesday afternoon (November 18) was given by Pim Tuyls, chief executive officer of Intrinsic-ID, the Dutch company that worked with InvenSense to develop the TrustedSensor product, a secure sensor-based authentication system incorporating the FireFly system-on-a-chip device.

TrustedSensor will be shipped to alpha customers in the first quarter of 2016 and will go out to beta customers in the second quarter of next year, according to Tuyls. “This is real,” he said.

The Intrinsic-ID founder briefly reviewed the company’s history, to start. It was spun out of Royal Philips in 2008 and is an independent company with venture-capital funding, Tuyls noted.

Intrinsic-ID was founded to provide “cyber physical security based on physically unclonable function,” or PUF, Tuyls said. “We invented PUF,” he added. “It has been vetted by security labs and government agencies,” among other parties.

Taking “The Trusted Sensor” as his theme, the Intrinsic-ID CEO said, “Sensors are the first line of defense. You want to make sure you can provide a certain level of security.”

It is critical to achieve “the right balance” in designing, fabricating, and installing sensors, with security, flexibility, and low footprint among the key considerations, according to Tuyls.

While whimsically describing PUF as “a magic concept,” Tuyls noted, “Chips are physically unique,” with no two completely alike due to manufacturing processes.

PUF can “extract a crypto key from any device,” he added. “You can authenticate any device.”

Intrinsic-ID has tested the PUF technology with a wide variety of silicon foundries, Tuyls said – namely, Cypress Semiconductor, GlobalFoundries, IBM, Intel, Renesas Electronics, Samsung Electronics, Taiwan Semiconductor Manufacturing, and United Microelectronics. It has been implemented by Altera, Microsemi, NXP Semiconductors, Samsung, and Synopsys, he added, and process nodes ranging from 180 nanometers down to 14nm have been tested.

Tuyls concluded by emphasizing the importance of sensor security for the Internet of Things. “We should not wait; we should not try to save a few cents,” he said. “It is important, but it is hard.”

Earlier in the day, attendees heard from Sam Massih, InvenSense’s director of wearable sensors. “There’s a wearable solution for every part of the body,” he commented.

“Step count isn’t enough,” Massih said. “You need context for data.” He cited the example of a user who goes to the gym three times a week and spends an hour on the elliptical trainer machine for one hour on each visit.

“That’s data that can be monetized,” he said.

InvenSense announced last month that it would enter the market for automotive sensors. Amir Panush, the company’s head of automotive and IoT industrial, said in his presentation, “Sensors need to be smart enough.”

The megatrends in automotive electronics include the use of motion sensors for safety in advanced driver-assistance systems (ADAS), the smart connected car, and tough emission restrictions, according to Panush.

“We have signed a deal with a Tier One partner,” Panush said, meaning a leading automotive manufacturer, without identifying the company. “We are ramping up internal R&D in automotive.” InvenSense is presently opening design centers focusing on the $5 trillion automotive market, he added.

InvenSense was founded in 2003 and went public in 2011. The company posted revenue of $372 million in fiscal 2015 with a net loss of $1.08 million (primarily due to charging $10.55 million in interest expense against net income), after being profitable for the previous four years. InvenSense gets more than three-quarters of its revenue from mobile sensors and has a growing business in IoT sensors.

Customers in Asia accounted for 63 percent of the company’s fiscal 2015 revenue, according to InvenSense’s 10-K annual report. The company spent $90.6 million on research and development, representing about 24 percent of its net revenue.

GlobalFoundries and TSMC make nearly all of InvenSense’s wafers. Assembly packaging of its microelectromechanical system (MEMS) devices and sensors is outsourced to Advanced Semiconductor Engineering, Amkor Technology, Lingsen Precision Industries, and Siliconware Precision Industries.

The company had 644 employees as of March 29, 2015, with nearly half of them involved in R&D.

STMicroelectronics is InvenSense’s primary competitor for consumer motion sensors, the 10-K states, while the company also competes with Analog Devices, Epson Toyocom, Kionix, Knowles, Maxim Integrated Products, MEMSIC, Murata Manufacturing, Panasonic, Robert Bosch, and Sony.

Mentor Graphics Presents at TSMC Forum

Monday, September 21st, 2015

By Jeff Dorsch, Contributing Editor

Mentor Graphics had a hand in presenting two of the 30 papers offered Thursday at Taiwan Semiconductor Manufacturing’s Open Innovation Platform Ecosystem Forum in Santa Clara, Calif.

The 30 presentations were provided in three tracks: electronic design automation, intellectual property, and EDA/IP/services. Mentor’s participation was in the EDA track.

On Tuesday afternoon, HiSilicon and Mentor presented on the subject of “Fill-As-You-Go: Leveraging Calibre SmartFill to cut your 16nm design verification runtime.” The presenters were Zhe Liu, a senior design engineer at HiSilicon, and Bill Graupp, DFM application technologist at Mentor.

The presentation described the work of HiSilicon, Mentor, and TSMC to implement methodology changes.

Later in the afternoon, Qualcomm and Mentor Graphics made a presentation titled “2-5x Productivity Improvement in Converging to a DRC-clean Cell Design – Qualcomm’s Experience with Calibre RealTime.” Tom Williams of Qualcomm was the presenter.

Cadence Design Systems and Synopsys also made multiple presentations at the TSMC OIP Ecosystem Forum.

TSMC Moves from 16nm to 10nm to 7nm

Monday, September 21st, 2015


By Jeff Dorsch, Contributing Editor

While Taiwan Semiconductor Manufacturing continues to fine-tune its 16-nanometer FinFET process, the world’s largest silicon foundry will begin making chips with 10nm features later this year and will put 7nm chips into risk production in early 2017, top executives said Thursday at a company event in Santa Clara, Calif.

Jack Sun, TSMC’s vice president of research and development and chief technology officer, said the 7nm process node will offer significant enhancements in speed, power, and device density. Processors, graphics processing units, and field-programmable gate arrays will benefit from 7nm technology, along with mobile and networking chips. He noted that TSMC has been able to turn out a functional test chip with 7nm features, implemented in a static random-access memory.

Cliff Hou, the company’s vice president of research and development/design and technology platform, said the foundry has collaborated with ARM Holdings on core implementation for scaling to 7nm. The transition from 10nm to 7nm will provide an area reduction of 40 percent to 45 percent, he added.

TSMC is looking toward employing extreme-ultraviolet lithography, direct self-assembly, and multi-beam electron-beam lithography to fabricate 7nm chips, Sun said. The company is working with ASML Holding on laser light sources with 90 watts of power, he added. Sun also said “settings are being finalized” for EUV systems capable of producing 125 wafers per hour.

Hou noted that the foundry put its 16nm FinFET Plus (16FF+) process into volume production earlier this year and introduced its 16FFC process, a “compact,” lower-cost version of 16FF+. TSMC will put 16FFC into NTO in the second quarter of 2016, he added.

Sun said TSMC is developing embedded resistive RAM and embedded magnetoresistive RAM technology to complement its SRAMs and flash memory devices.

He also reviewed the company’s wafer-level packaging technology, the chip-on-wafer-on-substrate (CoWoS) packaging and its integrated fan-out (InFO) packaging. InFO, a multichip package, will go into production next year and “could replace flip chip,” Sun said.

TSMC Forum Emphasizes Industry Collaboration

Thursday, September 17th, 2015


By Jeff Dorsch, Contributing Editor

Taiwan Semiconductor Manufacturing kicked off its Open Innovation Platform (OIP) Ecosystem Forum with thanks – not for another beautiful day in Silicon Valley, but for the collaborative work it does with its customers, suppliers, and other industry partners.

Rick Cassidy, the foundry’s senior vice president and president of TSMC North America, kicked off the all-day event in Santa Clara, Calif., saying he wanted to debunk the myth of the “lone creative genius” in the chip business. “It is a lot of geniuses working together,” he said. “Innovation happens collectively.”

While there has been much attention paid to the slowing growth in the smartphone market, mobile technology will continue to be a significant driver for the semiconductor industry, according to Cassidy. He reviewed the areas of mobile technology, the Internet of Things, and automotive electronics.

“IoT will require an incredible amount of interconnection technology,” Cassidy said.

Between IoT and automotive tech, there will be “a very significant amount of data that’s going to be needed to be stored and processed,” he added.

Cassidy emphasized TSMC’s relations with its many collaborators, large and small. “We’re a pure-play foundry,” he said. “We do not have any products.”

He added, “Nobody does yield better than TSMC.”

Cassidy noted that TSMC will spend more than $2.2 billion this year on research and development, compared with more than $1.9 billion last year. The foundry’s capital expenditure budget for 2015 is $10.5 billion to $11 billion, up from $9.5 billion in 2014, he added.

The opening session also heard from Jack Sun, TSMC’s vice president of R&D and chief technology officer, and Cliff Hou, vice president of the R&D design technology platform, as well as executives of Avago Technologies and Xilinx, two TSMC customers.

Solid State Watch: June 5-11, 2015

Thursday, June 11th, 2015
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Solid State Watch: April 3-9, 2015

Friday, April 10th, 2015
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TSMC Certifies Mentor Graphics Tools for Early Design Start in TSMC’s 10nm FinFET Technology

Monday, April 6th, 2015

Mentor Graphics Corp. (NASDAQ: MENT) announced that TSMC and Mentor Graphics have reached the first milestone of their collaboration on 10nm EDA certification. Calibre® physical verification and design for manufacturing (DFM) platform, and the Analog FastSPICE™ (AFS™) Circuit Verification Platform, including AFS Mega, are certified by TSMC based on the most current version of 10nm design rules and SPICE models.  New tool feature enhancement based on 10nm process requirements has been made in Olympus-SoC™ digital design platform with TSMC validation, and certification of full chip integration is actively on-going. In addition to 10nm, Mentor has also completed 16FF+ version 1.0 certification of the Calibre, Olympus-SoC and AFS platforms. These certifications provide designers with the earliest access to signoff technology optimized for TSMC’s most advanced process nodes, with improved performance and accuracy.

“The long-term partnership we have with Mentor Graphics enables us to work closely from the earliest phases of technology development so we can have production ready design kits and software available for our customers concurrently with the announcement of new process offerings,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “Mentor’s design solutions have successfully met the accuracy and compatibility requirements for TSMC 10nm FinFET technology, so customers can initiate their designs with accurate verification solutions.”

The Analog FastSPICE Platform provides fast circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. For large circuits the AFS Platform also delivers high capacity and fast mixed-signal simulation. For embedded SRAM and other array-based circuits, AFS Mega delivers highly accurate simulation results.

As circuit reliability remains a focus, Mentor and TSMC have enhanced the Calibre PERC™ product offering in 10nm to ensure that design and IP development teams have robust verification solutions for identifying sources of electrical error. Additionally, the Calibre xACT™ extraction suite includes updated models to deliver more accurate results to fulfill tighter accuracy requirements of 10nm.

For TSMC’s 16FF+ 1.0 Calibre design kit release, the Calibre team has worked with TSMC to speed up DRC performance by 30% on average. In addition, TSMC and Mentor released new filling use models that will improve first-pass fill runs, making ECO changes easier and faster. The new fill methodology will also help ensure consistent cycle times during post fill verification.

“Because Mentor and TSMC work together from the earliest stages of design rule development for a new process node, we learn what the new design and verification challenges are right along with TSMC.” said Joseph Sawicki, vice president and general manager of the Design to Silicon division at Mentor Graphics. “This gives us the ability to have the most advanced capabilities in place for ecosystem early adopters, and to continue to optimize performance as the new process moves to full production status.”

Proponents of EUV, immersion lithography face off at SPIE

Wednesday, February 25th, 2015

By Jeff Dorsch, contributing editor

The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium in San Jose, Calif.

Extreme-ultraviolet lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing.

On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.

There are other lithography technologies being discussed at the conference, of course. They are bit players in the drama, so to speak, although there is a lot of discussion and buzz about directed self-assembly technology this week.

ASML broke big news on Tuesday morning, reporting that Taiwan Semiconductor Manufacturing was able to expose more than 1,000 wafers in one day this year with ASML’s NXE:3300B EUV system. “During a recent test run on an NXE:3300B EUV system we exposed 1,022 wafers in 24 hours with sustained power of over 90 watts,” Anthony Yen, TSMC’s director of research and development, said at SPIE.

While ASML was obviously and justifiably proud of this milestone, after achieving its 2014 goal of producing 500 wafers per day, it cautioned that more development remains for EUV technology.

“The test run at TSMC demonstrates the capability of the NXE:3300B scanner, and moves us closer to our stated target of sustained output of 1,000 wafers per day in 2015,” ASML’s Hans Meiling, vice president service and product marketing EUV, said in a statement. “We must continue to increase source power, improve system availability, and show this result at multiple customers over multiple days.”

The day before, Cymer announced the first shipment of its XLR 700ix light source, which is said to improver scanner throughput and process stability for manufacturing chips with 14-nanometer features. The company also debuted DynaPulse as an upgrade option for its OnPulse customers. The XLR 700ix and DynaPulse together are said to offer better on-wafer critical dimension uniformity and provide stable on-wafer performance.

Another revelation at SPIE is that SK Hynix has been working with the NXE:3300, too, and is pleased with the system’s capabilities. According to Chang-Moon Lim, who spoke Monday morning, SK Hynix was recently able to expose 1,670 wafers over three days, with uptime of 86.3 percent over that period.

“Progress has been significant on various aspects, which should not be overshadowed by the delay of [light] sources,” he said of ASML’s EUV systems.

The Korean chipmaker is exploring how it could work without pellicles on the EUV reticle, Lim noted. ASML has been developing a pellicle, made with polycrystalline silicon, in cooperation with Intel and others.

Nikon Precision and other Nikon subsidiaries didn’t issue any press releases at SPIE. The companies presented much information at Sunday’s LithoVision 2015 event, held at the City National Civic auditorium, across the street from the San Jose Convention Center, where SPIE Advanced Lithography is staged.

On offer at the Nikon conference was the claimed superiority of 193i immersion lithography equipment to EUV systems for the 14nm, 7nm and future process nodes. Donis Flagello, Nikon Research Corp. of America’s president, CEO, and chief operating officer, emphasized that message on Tuesday morning with an invited paper on “Evolving optical lithography without EUV.”

Nikon’s champion machine is the NSR-S630D immersion scanner, which was touted throughout the LithoVision event. The system is capable of exposing 250 wafers per hour, according to Nikon’s Yuichi Shibazaki.

Ryoichi Kawaguchi of Nikon told attendees, “EUV lithography needs more stability and improvement.” He also brought up the topic of manufacturing on 450-millimeter wafers, which has mostly gone ignored in the lithography competition. Nikon will ship a 450mm system this spring to the Global 450 Consortium in Albany, N.Y., Kawaguchi said. The bigger substrates could provide “an alternative option to reduce cost,” he added.

Erik Byers of Micron Technology observed, “EUV is not a panacea.”

Which lithography technology will prevail in high-volume manufacturing? The question may not be definitively answered for some time.

Blog review January 26, 2015

Monday, January 26th, 2015

Scott McGregor, President and CEO of Broadcom, sees some major changes for the semiconductor industry moving forward, brought about by rising design and manufacturing costs. Speaking at the SEMI Industry Strategy Symposium (ISS) in January, McGregor said the cost per transistor was rising after the 28nm, which he described as “one of the most significant challenges we as an industry have faced.” Pete Singer reports.

Matthew Hogan, Mentor Graphics writes a tongue-in-cheek blog about IP, saying chip designers need only to merely insert the IP into the IC design and make the necessary connections. Easy-peasey! Except…robust design requires more than verifying each separate block—you must also verify that the overall design is robust. When you are using hundreds of IPs sourced from multiple suppliers in a layout, how do you ensure that the integration of all those IPs is robust and accurate?

Dick James, Senior Analyst at Chipworks IEDM blogs that Monday was FinFET Day. He highlights three finFET papers, by TSMC, Intel, and IBM.

A research team led by folks at Cornell University (along with University of California, Berkeley; Tsinghua University; and Swiss Federal Institute of Technology in Zurich) have discovered how to make a single-phase multiferroic switch out of bismuth ferrite (BiFeO3) as shown in an online letter to Nature. Ed Korczynski reports.

SEMI praised the bipartisan effort in the United States Congress to pass the Revitalize American Manufacturing and Innovation (RAMI) Act as part of the year-end spending package. Since its introduction in August 2013, SEMI has been a champion and leading voice in support of the bill that would create public private partnerships to establish institutes for manufacturing innovation.

Phil Garrou takes a look at some of the key presentations at the 2014 IEEE 3DIC Conference recently held in Cork, Ireland.

Adele Hars writes that there were about 40 SOI-based papers presented at IEDM. In Part 1 of ASN’s IEDM coverage, she provides a rundown of the top SOI-based advanced CMOS papers.

Karen Lightman of the MEMS Industry Group says power is the HOLY GRAIL to both the future success of wearables and IoT/Everything.  Power reduction and management through sensor fusion, power generation through energy harvesting as well as basic battery longevity. It became very clear from conversations at the MIG conference as well as in talking with folks on the CES show floor that the issue of power is the biggest challenge and opportunity facing us now.

In order to keep pace with Moore’s Law, semiconductor market leaders have had to adopt increasingly challenging technology roadmaps, which are leading to new demands on electronic materials (EM) product quality for leading-edge chip manufacturing. Dr. Atul Athalye, Head of Technology, Linde Electronics, discusses the challenges.

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