By Mark LaPedus
About every five years or so, a new and hot market emerges in the specialty foundry business that resembles a frenetic gold rush.

The last big gold rush occurred around 2008, when more than a dozen foundries jumped into the bipolar-CMOS-DMOS (BCD) market to capitalize on the booming power-management sector. Now, the next gold rush is centering on an emerging technology—the radio frequency (RF) silicon-on-insulator (SOI) market.

Today, IBM, STMicroelectronics and TowerJazz offer RF SOI foundry processes for the merchant market. Over time, analysts estimate that a dozen or more foundries could offer RF SOI. Altis Semiconductor and Grace Semiconductor have announced plans to enter the RF SOI fray. Two others, Lapis Semiconductor and Silanna, have put RF SOI on their foundry roadmaps. And sources indicate that GlobalFoundries, MagnaChip and TSMC are developing RF SOI or evaluating the technology.

Foundries are jumping on the RF SOI bandwagon amid a boom for select parts, particularly within the RF front-end for the latest smartphones and tablets. Typically, the RF front-end consists of power amplifiers (PAs), RF switches, tunable capacitors and filters. Generally, the PA and switch are based on gallium arsenide (GaAs), while the tunable capacitors and filters use various technologies.

RF SOI and its variant, silicon-on-sapphire (SOS), recently have made inroads for the RF switch—at the expense of GaAs. Most PAs are still based on GaAs, but the tide is slowly turning. For example, Peregrine Semiconductor is developing an SOS-based PA for a future smartphone at Apple, according to RBC Capital Markets.

Generally, RF chipmakers make GaAs-based devices in their own fabs. Chips based on RF CMOS, RF SOI and SOS generally are outsourced to the foundries. RF SOI is not a difficult technology to develop, but the real issue is that the sector could meet the same fate as BCD. As it turned out, the BCD market was not big enough to support a dozen foundries, prompting a shakeout in the arena.

In all likelihood, there is room for only a handful of RF SOI foundry players. “I would say IBM and TSMC are the only ones that have the economies of scale (in RF SOI),” said Doug Freedman, an analyst at RBC. “IBM is the leader in RF SOI right now, with TSMC trying to play catch-up. There are some other vendors like TowerJazz in the market, as well.”

From a supply/demand perspective, there is already ample RF SOI capacity to meet demand right now. “I have heard that capacity in RF SOI is adequate,” said Christopher Taylor, an analyst with Strategy Analytics. “I would have my doubts about the prospects of serious shortages barring compelling information to the contrary. Also, in light of the fact that RF SOI does not really push into the CMOS, small-node frontier, there is potentially quite a bit of capacity available from older fabs and foundries at the higher nodes.”

Rushing into RF SOI
The stakes are high, especially as RF content continues to increase in the latest mobile devices. In total, the PA market is expected to grow from $1.7 billion in 2008 to $3.8 billion by 2015, according to RBC. The multi-throw RF switch market is projected to grow from $262 million in 2008 to $1.2 billion by 2015, according to RBC. And the tunable capacitor market is expected to reach $500 million by 2016, it said.

“Driving this growth is rising handset and tablet units, which requires a greater amount of PA ICs,” RBC’s Freedman said. “Principally driving (RF switch) growth is rising radio bands. Driving (tunable capacitor) growth is the wider frequency range of bands and the need to reduce antenna size without performance trade-off.”

There is also an increase in design complexity amid a transition from 3G networks to the next-generation, 4G/LTE wireless standard. “LTE and carrier aggregation are thorny problems even in the best of situations,” said Michael Noonen, executive vice present of global sales, marketing, quality and design at GlobalFoundries. “You also want to be as Spartan as possible in the RF front-end design from a battery consumption standpoint.”

GlobalFoundries, which has been expanding its RF process offerings, is “very much interested” in RF SOI, Noonen said. “We have a lot of experience with SOI, but there are also other approaches in RF,” he said.

Indeed, OEMs face a series of complex device and process choices. For years, GaAs has dominated the RF landscape. GaAs has a larger energy gap and is faster than silicon, but it is more expensive to manufacture. RF CMOS, RF SOI, SOS and silicon-germanium (SiGe) are also in the mix. The RF version of SOI combines CMOS with a highly-resistive, thick-film SOI substrate.

RF SOI is an alternative to GaAs, with equivalent insertion loss and noise isolation characteristics. RF SOI also enables OEMs to integrate various chips on the same die. Another technology, SOS, makes use of an insulating sapphire substrate. And SiGe is built with silicon transistors to create RF circuits.
Meanwhile, after years of promises, RF SOI and its variants are finally cracking the RF front-end. OEMs are moving from GaAs pHEMT to RF SOI and SOS for the RF switch, said Paul Boudre, chief operating officer at Soitec, an SOI wafer supplier. “GaAs pHEMT will not disappear, but it will remain for more specific devices,” Boudre said.

Actually, the buzz started when Apple incorporated Peregrine’s SOS-based RF switches in the iPhone 5. Samsung’s Galaxy S4 and other smartphones are also using SOS-based switches, according to RBC. SOS is a proprietary technology that is only offered by Peregrine. Its SOS chips are made on a foundry basis by Lapis, MagnaChip and Silanna.

Rodd Novak, chief marketing officer of Peregrine, said SOS has better insulating properties than RF SOI. SOS also uses sapphire wafers, making it a more expensive than RF SOI. But the overall cost for SOS is declining. This is because sapphire wafers are ramping up in high-volume markets like LEDs, which will impact the cost of SOS, Novak said.

Peregrine recently rolled out a new version of SOS, based on 0.35-micron technology. “Before, we grew an epi (layer) on top of our sapphire process,” Novak said. “Now, we are taking a very clean silicon substrate and bonding that to the sapphire. That process enables better performance.”

Apple to drive SOI?
The fact that Apple and other OEMs have adopted SOS and RF SOI for the RF switch has given the technology some credence. It also has caused a stampede of foundry players looking to enter the RF SOI sweepstakes.

Now, with help from the foundries, RF chipmakers are looking to displace SOS-based switches with traditional and less-expensive RF SOI technology. “RF switches are typically based on GaAs pHEMT, SOS and SOI, with SOI gaining more and more market share away from the other and more expensive technologies,” said Marco Racanelli, senior vice president and general manager at TowerJazz.

In addition to cost, OEMs are also interested in capacity. In one effort to ensure supply, IBM recently signed a second-source foundry deal for its 0.18-micron, RF SOI process with Altis.

Besides the RF switch, the next big market for RF SOI and SOS could be the PA, with Apple emerging as the possible driving force. “We believe that Peregrine is developing a unique integrated PA solution that is targeting the next generation of Apple’s PA product needs,” said RBC’s Freedman. “(This) could add approximately $1.25 in content, assuming (Apple integrates) five to six single PAs in 3G smartphones. We note that in 4G, PA content opportunity rises to approximately $3.00 due to rising single chip PAs per device.”

In another example, Qualcomm recently rolled out the RF360, an RF front-end that includes a PA based on SOI. Today, however, the jury is still out for PAs based on RF SOI and SOS. For the PA, GaAs still has a higher power-efficiency over CMOS.

Still, the handwriting is on the wall for GaAs. “For the PA, SiGe BiCMOS has strong market share in WiFi, while GaAs HBT has strong market share in cellular. RF CMOS is relegated to the very low-end 2G/2.5G cellular space,” TowerJazz’ Racanelli said. “SOI for the PA is only in R&D and may not deliver the best performance by itself. But combined with switches and other functions, (SOI-based PAs) could become relevant as new architectures are adopted. Our view is that SiGe has the best tradeoff in performance. The cost structure is closer to CMOS/SOI. SiGe is likely to gain more ground in the future.”

Also in the RF front-end, there is a tunable capacitor, which tunes the antennae to boost efficiencies. Peregrine is selling SOS-based tunable devices. Paratek and STMicroelectronics are selling components based on barium strontium titanate (BST). And WiSpry is offering a MEMS solution.

“There are two vectors worth exploring here,” GlobalFoundries’ Noonen said. “If you can do something in CMOS, it will be done in CMOS. We will see other ways to approach the problem. Using a tunable capacitor based on MEMs, for instance, you can attack the problem from an entirely different angle.”

Indeed, in the RF front-end, there is no one-size-fits-all technology; OEMs likely will adopt several types of chips and processes. “We will also see more functionality in the RF subsystem,” Noonen said. “The idea is to bring RF into more of a mainstream technology.”

By Mark LaPedus
After its formation nearly 20 months ago, a 450mm consortium has reached its latest milestone by recently completing a cleanroom and installing the first 450mm demonstration tools in the facility.

The so-called Global 450 Consortium (G450C) also has set a goal to bring 450mm fabs into high-volume manufacturing at the 10nm or 7nm nodes by 2018. That gives the industry a little less than five years to develop the production tools for 450mm fabs, which are expected to cost a whopping $10 billion or more. Based in Albany, N.Y., the G450C has five members—GlobalFoundries, Intel, IBM, Samsung and TSMC.

But between now and 2018, there is a staggering amount of work to be done. Based on the current progress for select equipment, fab technologies and standards, the path towards 450mm will be a bumpy road and it’s unclear if the industry can meet the 2018 target.

The most obvious problem is lithography. For example, ASML Holding is not expected to deliver a production-worthy, 450mm version of its extreme ultraviolet (EUV) lithography scanner until 2018. Other challenges include lithographic cost-of-ownership and throughput.

On the wafer-processing front, Applied, Lam, TEL and others are moving full speed ahead in 450mm. TEL also is proposing an “open platform” standard—a move that has received a lukewarm response. Meanwhile, there is some movement in metrology, as a new consortium has recently been formed to address the challenges in 450mm.

And the industry is still debating over various 450mm fab standards, such as aisle space and ceiling height. There is even a debate over the type of cranes needed to install 450mm tools. Other standards, such as gas interface boxes, cooling water manifolds, and hookups for power, are also in the works.

That’s just the tip of the iceberg. The goal for the G450C is not only to help develop these technologies, but it also has the arduous task of getting the various players to synchronize on the roadmap. “It’s going to require a collaborative and concerted effort to introduce (450mm technology) in an efficient manner,” said Steve Johnston, director of external programs and technology strategy in the Technology Manufacturing Engineering Group at Intel, at a recent SEMI event. “All of this requires flawless and synchronized execution across the industry and at multiple levels.”

Avoiding past mistakes
Indeed, the industry hopes to avoid past mistakes. In the mid-1990s, the IC industry wanted to make the shift from 200mm to 300mm fabs. The equipment industry had the 300mm tools ready in the late 1990s, but chipmakers pushed out their 300mm fabs amid an IC downturn. Equipment vendors ended up holding the bag and lost a fortune. Shortly thereafter, chipmakers began to ramp up their 300mm fabs, but the events left a bad taste in vendors’ mouths.

Recently, Intel, Samsung and TSMC have been pushing for 450mm fabs. The argument is that the industry needs to make a wafer transition every 15 years to stay on Moore’s Law. Moving to 450mm wafers will give chipmakers a 2.25x boost in wafer area and a 30% cost reduction, according to chipmakers.

For some time, however, fab tool vendors were lukewarm about 450mm. There are only a handful of customers who would buy 450mm tools, and it’s unclear who will foot the R&D bill for the technology.

More recently, 450mm has become a reality. Intel and TSMC have outlined plans to build 450mm fabs. And in 2011, the G450C was established at the College of Nanoscale Science and Engineering’s NanoTech Complex. The G450C recently opened a cleanroom. Its roadmap also calls for 450mm pilot lines in 2015 and 2016, with high-volume production targeted for 2018.

“Synchronization and collaboration are very important to avoid the same type of issues we ran into in the late 1990s with the transition to 300mm,” said Kirk Hasserjian, corporate vice president for the Silicon Systems Group at Applied Materials.

There are other issues, namely supply-chain readiness, return-on-investment and R&D funding. “The (R&D funding) issue requires a very different business model,” Hasserjian said. “That has not been completely resolved. We have the consortium activities, which have provided some level of funding.”

Fab tool challenges
The industry has moved to fund at least one technology, namely lithography. Intel, Samsung and TSMC recently invested in ASML, in an effort to accelerate ASML’s efforts in 450mm and EUV. And with separate funding from Intel, Nikon is developing a 193nm immersion scanner for 450mm.

ASML itself has initiated 450mm programs on two separate platforms and four wavelengths, including EUV. The goal is to deliver “early version tools” in 2015 to 2016, with 450mm production systems due out by 2018, said Jim Koonmen, general manager of Brion Technologies, a division of ASML.

The development of a 450mm EUV scanner is expected to be a herculean effort. Today, ASML is struggling to deliver 300mm EUV tools amid delays with the power sources. Cost is also an issue, as ASML’s pre-production EUV scanners cost $100 million or more per unit today.

Throughput is also an issue. The throughput for a 450mm scanner in general is projected to be only about one-half of a 300mm tool, Koonmen said. A 300mm tool has a throughput of about 250 wafers per hour (wph), while a 450mm system can run 100-125 wph at 1.1x the cost, he said.

“If you look at the entire semiconductor process, there are steps that do get a lot of leverage from larger wafer sizes and can realize cost reduction,” he said. “Unfortunately, with lithography, there simply isn’t that much of a benefit in going to larger wafer sizes. We are scanning as fast as we can. The number of fields is going to increase when we go to larger wafers, but that just means your throughput for each 450mm wafer is going to go down. So you’ve got double the number of fields, but you are going at half the throughput. That in itself is not easy to do. In order to handle a 450mm wafer, you need to have larger stages with larger masks, and that creates a whole bunch of issues for us.”

Meanwhile, amid the problems with EUV, the industry is hedging its bets by developing 193nm immersion scanners for 450mm. Optical is a proven technology, but the solution is expensive. At 10nm or 7nm, chipmakers must also use expensive multiple patterning schemes.

Delivery schedules for 193nm immersion are more certain, however. “450mm is expected to be in production by 2018,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “We will ship development tools earlier than that.” By 2015, Nikon plans to ship “early learning tools” based on 193nm immersion for 450mm, Zarringhalam said. Nikon has already garnered “multiple orders” for the systems, he added.

On the wafer processing side, there are also some technical and cost challenges. “Prices could rise 30% to 50% for 450mm tools, as they did when the wafer size shifted to 300mm from 200mm,” said analyst David Motozo Rubenstein, who is also the author of a blog entitled “Chips and Dips.”

Applied, Lam, TEL and others are developing standalone 450mm tools. TEL also is proposing the idea of having an “open and modular platform” for 450mm. This would enable fab tool vendors to develop various plug-and-play process modules for the open platform, thereby reducing costs and development times. TEL and its rivals could develop modules for the platform. “The open platform is a concept for the 450mm high-volume manufacturing era,” said Aki Sekiguchi, vice president and general manager for SPE marketing at TEL.

The open platform could benefit smaller companies that don’t have the resources to develop standalone tools. But larger companies are not eager to endorse an open platform, because it will give its rivals a competitive edge. “We are looking at it,” said Applied’s Hasserjian. “We are not doing what TEL is doing and advocating a modular platform.”

Metrology challenges

Another challenge is the development of 450mm metrology gear. “There are not many companies that can invest six years in advance,” said Menachem Shoval, chairman of Metro450, an Israeli-based consortium that is developing 450mm metrology technology. “Even without going 450mm, there are huge challenges for metrology in terms of going down from 22nm to 14nm to 10nm to 7nm.”

This is especially true when moving from today’s planar devices to finFETs at 22nm and beyond. “Going to 3D has created numerous challenges for us,” said John Allgair, senior member of the technical staff at GlobalFoundries. “We see tenfold measurement problems as we go to 3D. A lot of things you see in 2D tend to get amplified as we go to these 3D structures. Then, we see some real challenges when it comes to compositional analysis. In finFET devices, we’ve got compositional measurements like SiGe with a percentage of germanium and a percentage of boron on a 3D structure. That’s a very complex measurement. Finally, we try and do measurements on test structures. The test structures don’t always mimic what’s actually taking place on your device. That really adds to the complexity of trying to manufacture finFETs in a stable manner.”

One solution to the problem is to collaborate through a consortium, Metro450′s Shoval said. Last year, for example, the Metro450 consortium was formed by the following companies—Applied Materials, Nova, Jordan Valley, Nanomotion and Intel. The group also consists of four universities in Israel, with some 60% of the funding coming from the Israeli government.

“Each company develops its own technology,” Shoval said. “They are competing with each other. But we can collaborate on those parts which are common. We will work on platforms, but not on detection.”

One of the goals for the Metro450 group is to meet the design rule targets by 2017. It is also devising technologies that are 2.5x faster than 300mm, thereby meeting the cost requirements for 450mm. To reach its goals, the group is working on five specific technologies: wafer handling; sampling optimization; wafer damage and contamination; calibration; and data processing.

“We plan to complete our work in three years,” Shoval said. “So companies will still have about three years to complete the development of their high-volume manufacturing tools.”

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Serge Tedesco, lithography program manager at CEA-Leti; Laurent Pain, lithography lab manager at CEA-Leti; and Raluca Tiron, a senior scientist at CEA-Leti.

SMD: CEA-Leti has two major and separate programs, including one in directed self-assembly (DSA) and another in multi-beam e-beam. Let’s start with DSA. What is CEA-Leti doing in DSA?
Pain: For DSA, we have what we call the ‘Ideal’ program. We are developing 300mm processes. We have materials development with Arkema. Other partners include TEL and Sokudo. We are working with STMicroelectronics to transfer the technology from a process point of view. We are developing this capability for lab scaling to industry production.

SMD: What have you demonstrated with DSA?
Pain: We have demonstrated resolutions down to 18nm half-pitch, which is considered the 7nm logic node. We think we can extend PS-b-PMMA down to the 7nm node. The concept is to enable 7nm to 4nm resolutions with Arkema’s materials.

SMD: The big question is when do you think DSA will move into production?
Pain: From my point of view, it should be 10nm. You will start to see some demonstrations at 14nm.
Tedesco: You can ask me that in July. I still say 2014.

SMD: What are the challenges with DSA?
Pain: There will be some challenges in terms of defectivity and process maturity.
Tiron: For contact shrinks, the processes are here. It’s stable. That means you can absorb a lot of the variations with the block copolymers. But you don’t have pitch or density. If you move to contact doubling, you have the density. But you lose the process window stability. The placement of the contacts is also less certain. But what is important is now we have materials, processes and tracks. What we really need now is some real fabrication. The applications depend on the end-user. What we need is the end-users to tell us: ‘We need this and that and then move in that direction.’ That’s what is missing today.

SMD: What have you accomplished in your DSA process flow?
Tiron: We have implemented a process flow on a 300mm track, which comes from Sokudo. We have a complete DSA process cycle in one track. The track handles the brush coat and block copolymer coating. The track also has high temperature hot plates for block copolymer cure. We also worked with Sokudo to develop a PMMA removal process. We demonstrated different exposure treatments and solvents. What we are trying to do now is address contact hole shrinks and contact multiplication. With the polymers from Arkema, we are able to do resolutions from 20nm period, which means 10nm resolution, to 60nm period, which means 35nm resolution. Contact shrink is possible using both cylindrical and lamellar morphologies.

SMD: What about yield or defects?
Tiron: We have shown good uniformities with three sigma around 2nm. After the optimization of the process, we counted 6,800 divisional points on the wafer. We only found five missing contacts. By using block copolymers, we showed 99.93 % valid contacts on the wafer. This is just using PMMA.

SMD: Let’s move to multi-beam. What is CEA-Leti doing in multi-beam?
Pain: The second program is called Imagine. This program started last year. We have a partnership with (multi-beam e-beam vendor) Mapper Lithography. Other partners include Aselta, JSR, TOK, TSMC, Sokudo, Dow, STMicroelectronics, TEL and Mentor.

SMD: How far along is Mapper’s multi-beam tool?
Pain: The first machine will consist of 1,300 beams. The throughput is one wafer per hour. The tool will arrive the beginning of June. That’s targeted for the 14nm logic node. This machine will be interfaced with the Sokudo track. The first exposures will start in the last quarter of this year. Eventually, the target is to reach 16nm half-pitch. Our goal is to have 13,000 beams with the Mapper tool. We expect to scale the throughput from one wafer per hour to 10 wafers an hour. Then, we plan to push the resolutions down to 10nm half-pitch.

SMD: What is the cost-of-ownership for the Mapper tool?
Pain: The cost is 1 million euros for two wafers per hour. So in other words, that’s 5 million euros for 10 wafers per hour. Our eventual goal is to cluster 10 machines together. That’s 50 million euros for the cluster configuration.

SMD: Isn’t multi-beam taking longer than expected and behind schedule?
Pain: If you take the original roadmap, we are late. Some of the technical achievements have taken a long time.
Tedesco: One of the problems is there is a lack of support from the industry. It’s a shame that there is a lack of support, when you look at what’s being done on the EUV side. That’s one of the reasons that multi-beam is not mature yet. Of course, there is the technical aspect. TSMC, of course, is the one that is pushing this technology. But beyond TSMC, there is a lack of support. But I think the support will eventually come.

SMD: TSMC has stated it wants to do all layers with multi-beam. Is that practical or will multi-beam end up doing traditional direct-write applications like ASICs?
Tedesco: It could be a challenge to do all layers with multi-beam. But a maskless tool could be useful in terms of ASICs or prototyping. It’s ideal for the foundries. But the first applications for multi-beam will likely be contact holes and the cut layer.

SMD: How about STMicroelectronics? STMicroelectronics has been involved with direct-write for many years.
Tedesco: ST is a partner of Leti. So they are following Imagine very closely.

SMD: What about funding for multi-beam from the likes of Intel, GlobalFoundries and Samsung?
Tedesco: Good question. What we can say is that they are following us very closely. They know what we are doing. At this point, they are not part of the program.

By Ann Steffora Mutschler
As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable.

But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to solve it. You’re on autopilot until you hit a disruption, and 3D represents a disruption.”

Whether it is memory stacked on logic, which is most common today, or stacking multiple logic die on top of each other vertically with through silicon vias (TSVs), both approaches are complicated and require more infrastructure than traditional SoCs.

Yervant Zorian, a Synopsys fellow and chief architect, noted that we have always dealt with multiple chips—but the multiple chips that we dealt with previously were packaged chips. “Having packaged chips on a board allowed us to test the chips fully upon packaging when they are on the wafer. And also, after being packaged to give the full quality chip, proven and warrantied to the board-level team to assemble it on the board. Now that’s all good when a die is packaged—a package protects it from further defectively. However, with 3D stacks or 2.5D interposers or some other advanced packaging technologies we are dealing with there is bare die that is unpackaged so the whole issue starts with that.”

So even though the bare die are fully tested, they are prone to defectively during assembly, mounting, transportation. “Whatever you do between the production of that die up through the time it is assembled with the rest of the dies there is this defectivity magnet situation where certain things happen to it and therefore we need to retest it after it’s been assembled—whether it is two dies, four dies, at every stage you need to test it again to make sure that nothing is damaged,” he added.

Clearly, the test challenges with stacked die include the need to test things at multiple points during fabrication and assembly, Petrakis said. “Then there is a big question about how much testing is required. With test there is cost and what do you forgo and what do you actually test.”

There are two schools of thought here, he noted. One is to use the normal manufacturing test type of approaches such as implanting test circuitry as is normally done and testing each die separately. “You make sure that you apply all the tests and then you know you probably have good die to work with. ‘Probably’ is a good term because you never know.”

Then, if the design will use through-silicon vias, what is the best approach to test and how do you get access to the test interface? “On a normal chip you just go to the pads and you say, ‘These are the test pads,’ and you target those. On a TSV-based design there is a lot of talk about landing probes, but the dimensions are so small that there is fear that they are going to be damaged,” he added.

It’s not all doom and gloom with stacked die, though. “The fun comes in when you start stacking logic die,” asserted Stephen Pateras, product marketing director for Mentor Graphics’ Silicon Test Solutions group. “In the case where you had a single logic die you had full access to it. If there were any test pins and memories that needed to be accessed directly even though they are stacked, you’re going through the BiST, the JEDEC standard interface, so you don’t have to worry about accessing the DRAMs directly. But with stacked logic die, now presumably you want to test pieces of a logic die. You want to test the interconnect between them, so you need access each of those logic die independently somehow. Generally you don’t have access to them, because if they are stacked vertically the idea is that the bottom die will be the one that is connected to the package and the other die are connected to each other. So there may be neighbors top or bottom in that stack. That’s where we need to have a way of going through the stack to get access to those die for test so you need some kind of test access architecture that makes use of the TSVs.”

At the foundation of such a test access architecture is the proposed IEEE P1838 standard, which gives just such access.

Zorian explained that IEEE P1838 complements the work that was done previously with JTAG 1149.1 and IEEE 1500, whereby JTAG was for the chips on the board and 1500 was for the cores in the SoC. “P1838 is for the dies in a 3D structure to talk to those dies. You need an access port and this access port cannot be JTAG. It cannot be 1500, but it can be something between the two and very complementary to those working hand-in-hand coherently with the first two standards to handle the new multi-dies in a package. P1838 will allow us to know exactly what that test bus is. The seven-bit communication bus proposed today will communicate the test related functions between one die to the other, from that die to the next and so on.”

By the time 3-D becomes prominent it is expected that P1838 will be ratified as an IEEE standard.

Further, Cadence’s Petrakis noted that the idea behind p1838 is isolation. “How do we isolate one die from the others such that we can test it internally without disturbing anything else? Then it’s not quite really disturbing it. It’s really a matter of true isolation. You do not want any foreign signals or unknown traditions to affect the testing that you are doing. The isolation is that we put the chip in a mode where it only sees data coming in and out from itself. In other words, the application of test reading the results back is not influenced by anything else.”

The looming cost concern
Amidst the technical challenges of 3D and 2.5D stacked die is the discussion surrounding who will pay for all of this extra testing.

Synopsys’ Zorian said, “The two stops in test that we used to have, which is testing the chip at the wafer level and testing the chip post-package, will still be there. But now we introduce intermediate steps so suddenly we need to do more test in between. When I have two dies together, three dies together—these are the prevalent situations where we need to test them. And there is a cost associated with it because it is after the die has been produced, so you cannot cost-wise expect the die producer that is the chip manufacturer to do that. It is a packaging-oriented cost because it happens later on during the stages of pulling those dies together. It depends who will be doing it and therefore who will pay for it.”

At this point, it seems that the cost will not fall to the die producer, but it depends on how the business model develops—especially because several chip manufacturers and foundries have expressed interest in being part of this ecosystem. “Whether it is TSMC, GlobalFoundries or otherwise, if they are doing it then of course it will be the last stage, because it’s not the wafer manufacturing stage or the wafer testing stage. It is one stage after that.”

However the situation turns out, the rising wave of 3D manufacturing and test is causing ripples throughout the entire ecosystem.

By Mark LaPedus
Qualcomm has the highest market share for baseband solutions in handsets, resulting in a position far out in front of its competitors. ST-Ericsson has strong products on the market with competitive features. But one analyst at ABI Research questions why ST-Ericsson was broken up just as it finally came out with a highly competitive product, which was based on FD-SOI.

The worldwide semiconductor foundry market totaled $34.6 billion in 2012, a 16.2% increase from 2011, according to final results by Gartner. TSMC maintained the No. 1 spot in the rankings in 2012. Strong performance on 32nm yields and the availability of sub-45nm wafer capacity at the Dresden, Germany, fabs allowed GlobalFoundries to advance to the No. 2 position in 2012. UMC‘s market share decreased due to reduced wafer shipments. Driven by the wafers consumed by Apple, Samsung moved up four spots to the No. 5 position with 175.5% growth in 2012.

At this year’s Symposium on VLSI Technology, Intel will report technical details of its embedded DRAM with 22nm technology on bulk silicon wafers. Intel realized a 0.029mm2 DRAM cell capable of meeting >100us retention at 95 C. In the DC-DC converter session, Intel will present a switched capacitor step-down converter designed in a 22nm tri-gate CMOS technology. The VLSI Symposium is slated for June 11–14 in Kyoto, Japan.

At the VLSI event, STMicroelectronics and CEA-LETI will report six transistor SRAM (6T-SRAM) cells for high-density and low-voltage. The technology is fabricated at the 28nm node using FD-SOI technology for the first time.

At the VLSI Symposium, IBM and GlobalFoundries will report a SiGe channel tri-gate pFET with aggressively scaled fin width and gate length dimensions. It is fabricated using SiGe on an insulator substrate. Excellent electrostatic control down to Lg= 18nm and Wfin<18nm has been reported.

At the event, IMEC and GlobalFoundries will present the first demonstration of strained germanium channel pFETs fabricated on SiGe strain relaxed buffers, which is surrounded by STI region. Also, they introduced raised SiGe source/drain structures (Ge concentration= 75%) with an implant-free quantum well, replacement metal-gate process and germanide in contacts to solve void issues.

In addition, STMicrolectronics, Samsung, GlobalFoundries and IBM will report a 64nm pitch BEOL integration and material strategy. A self-aligned-via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask.

SEMI reported that for the quarter ending Dec. 31, 2012, the worldwide photovoltaic manufacturing equipment book-to-bill ratio remained well below parity, at 0.45, for the seventh consecutive quarter. Booking levels continue to be low as PV manufacturers grapple with oversupply across the supply chain.

Khaled Juffali Company (KJC), a Saudi Arabian investment company, and Soitec, signed a memorandum of understanding (MOU) to cooperate in driving solar industry growth in Saudi Arabia and the Middle East. Under the MOU, the two companies will create a joint venture to market and sell concentrator photovoltaic (CPV) systems in the Kingdom of Saudi Arabia.

Hwa Chong Institution emerged as the winner of the Applied Materials Clean Tech Competition in Singapore. The project focused on utilizing calcium carbonate found in clam shells to remove toxic metal ions from waste water.

The separate hardware and software teams in companies are notorious for not being on the same page, thereby putting product development times and cost at risk. Mentor Graphics CEO Walden Rhines outlined some new and practical solutions to the problem.

Mentor Graphics announced the release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon. The tool provides a tighter connection between hardware and software co-development, but allows software developers to use existing programming tools with extensions.

Cadence announced results for the first quarter of fiscal year 2013. Cadence also completed its previously announced acquisition of Tensilica.

Advantest will acquire W2BI, a provider of system level test automation software focusing on wireless communications.

Shipments of smart glasses may rise to as high 6.6 million units in 2016, up from just 50,000 in 2012, for a total of 9.4 million units for the five-year period, according to an upside forecast from IMS Research.

The worldwide mobile phone market grew 4% year over year in the seasonally slow first quarter of 2013 as smart phones out-shipped feature phones for the first time, according to IDC. Nokia, BlackBerry and HTC have dropped out of the top rankings.

By Mark LaPedus

The complexity of today’s chips is forcing silicon foundries to expand on both the leading-edge and specialty-process fronts.

For example, GlobalFoundries is expanding in both areas. On the specialty process front, GlobalFoundries confirmed that it recently bought 300mm fab tools from Taiwan’s ProMos Technologies. Many of the tools will be used within GlobalFoundries’ 300mm fab in Singapore, which makes wafers based on various analog and mixed-signal processes. The idea behind this move is to offer “mixed-signal technologies with 300mm economies of scale,” said Michael Noonen, executive vice present of global sales, marketing, quality and design at GlobalFoundries.

On the leading-edge, the silicon foundry vendor recently expanded its technology platform offerings to five, including bulk planar, super-steep retrograde well (SSRW), fully-depleted silicon-on-insulator (minimum), fully-depleted silicon-on-insulator (maximum) and finFET.

Despite a recent setback with FD-SOI, GlobalFoundries will continue to offer the technology and also gave a ringing endorsement about FD-SOI. In March, Ericsson and STMicroelectronics announced plans to disband ST-Ericsson, a supplier of cell-phone chipsets, including an integrated applications processor based on FD-SOI. Ericsson will take on the design, development and sales of the LTE multimode modem products from ST-Ericsson. STMicroelectronics assumed the ownership of the integrated applications processor based on FD-SOI.

Meanwhile, for some time, GlobalFoundries and STMicroelectronics have had a foundry arrangement under which GlobalFoundries will make FD-SOI products on a foundry basis for STMicroelectronics. GlobalFoundries has not wavered in its support for FD-SOI, saying it will continue to provide the technology on a foundry basis for customers.

FD-SOI provides a viable option for customers, enabling them to differentiate their products, Noonen said. “We want to supply options to customers,” he said. “There is a tremendous amount of interest (for FD-SOI).”

Noonen is also seeing strong interest for its finFET process. GlobalFoundries, Samsung and TSMC have all accelerated their finFET process roadmaps. “We’ve accelerated it,” said Morris Chang, chairman and chief executive of Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), at a recent event. At the event, TSMC reiterated its finFET roadmap, saying it would move into “risk production” by the fourth quarter of 2013.

Like TSMC and Samsung, GlobalFoundries is in mass production for its 28nm processes and is ramping up its 20nm technology. “20nm will be a fast ramp,”  Noonen said. “In general, 28nm is going to be a long-lived node.”

On the specialty process front, meanwhile, GlobalFoundries recently disclosed an initiative called “Vision 2015.”  The initial phase of the plan will include a capacity expansion of its current Fab 7 300mm facility to be on a trajectory of nearly 1 million wafers per year, up from 600,000 wafers a year right now. The expansion is expected to be completed by the middle of 2014.

As part of that effort, GlobalFoundries wants to give analog- and mixed-signal customers a viable 300mm option to compete against the analog leader—Texas Instruments. For some time, TI has been in production within the world’s first 300mm analog fab, dubbed RFAB, based in Texas.

“We want to be the answer to that,” Noonen said.

By Jeff Chappell
There may have been a time when AMD founder Jerry Sanders famous quote: “real men (i.e., real companies) have their own fabs” rang true, but in today’s business climate it seems quaint at best.

Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues by offering foundry services—Intel and Samsung among them. Then there is the fact that the third-largest chipmaker in 2012, in terms of revenue, was a pure-play foundry.

As the 28nm node capacity ramp continues in the foundry market in 2013, following unexpected demand and capacity bottlenecks in 2012, today’s foundry market is the end result of market trends and forces with old roots. But those trends and forces have been compounded in modern times by extreme financial and market necessities, not to mention technology.

In one sense, however, at its core, the foundry market hasn’t changed since Taiwan Semiconductor Manufacturing Co. (TSMC) launched as the industry’s first pure-play foundry in 1987: Chip companies look to foundries, either as a customer or as a provider, to maximize productivity and thereby minimize costs. That part of the game hasn’t changed, whether it involves a component supplier designing power modules with 0.18-micron design rules for manufacturing on 200mm wafers, or one of the two GPU giants producing their next-generation graphics processors based on the latest technology.

The trend for years now has been fabless or fab-lite; even Sanders’ own AMD spun out its manufacturing arm several years ago to create one of the world’s largest pure-play foundries, GlobalFoundries. This has naturally in turn spawned the growth of the pure-play foundry market from its birth some 26 years ago.

Indeed, last year the overall foundry market enjoyed revenues of $29.6 billion, managing year-over-year growth of 12%, which is three times that of the chip industry over all in 2012. That growth caught everyone by surprise including the foundries themselves; 28nm capacity was tight for much of the year, even as yields improved dramatically—so much so that it reportedly impacted some capital equipment purchases, in spite of tight foundry capacity.

But that illustrates the biggest and most obvious change in the foundry industry in modern times: The foundries themselves are involved directly with developing leading-edge semiconductor technology. In fact, with the industry looking at the end of planar CMOS at the leading edge for some devices with the advent of 3D transistor architectures and the high-k materials they require, leading foundries no longer can rely on a mix of conventional scaling, publicly available data and equipment and process technology suppliers to get their jobs done. Research and development now must be within their purview, at least for those playing at the leading edge.

“Historically foundries don’t do R&D, their clients do it,” noted Dean Freeman, a research vice president at Gartner Research. That’s not so, today.

Nothing illustrates that fact better than TSMC’s R&D budget. In 2012 the company spent 33.8 billion NT, or about $1.13 billion, on R&D—a quarter of its revenue. This year the company plans to spend 40.4 billion NT, or about $1.35 billion, which includes adding some 500 people to its employee headcount, bolstering its R&D staff from 3,400 people to 3,900.

Indeed, leading foundries have joined the leading IDMs and technology consortia as purveyors of—not just manufacturers of—advanced technology.

While TSMC and its foundry brethren in the first tier of the pure-play market—Globalfoundries and United Microelectronics Corp. (UMC)—continue to build out 28nm capacity, they are also hard at work on the 20nm node and the subsequent hybrid 14/16nm finFET based on a 20nm back-end of line process. In fact, TSMC just announced first tapeouts of an ARM A-57 processor, based on the 64-bit ARMv8 processor series and built with 16nm transistor technology, including finFETs. This followed their rival’s announcement of a few months earlier. In February, GlobalFoundries announced a “first implementation” of a dual-core ARM A9 processor using the company’s 14nm-XM FinFET transistor architecture.

Follow the money
Being on the very leading edge of technology is driving growth among the first-tier foundries.

Like many others in the industry, TSMC and its chairman and CEO, Morris Chang, are quite bullish on the continued demand for 28nm technology as well as the development of 20nm technology. In general, 28nm designs, with their combination of lower power consumption and speedier transistors, have consequently proven cost-effective for a chip industry currently driven by mobile devices—smartphones, tablets and ultra lightweight notebooks. During TSMC’s review of its 2012 results earlier this year, Chang said the company will continue to aggressively grow its 28nm capacity and output; 2013 capacity and output will triple that of 2012, he said.

“It’s all about lower power with functionality and no sacrifice on the power requirements,” observed Kathryn Ta, managing director of strategic marketing for Applied Materials’ Silicon Systems Group. The equipment and process technology supplier’s foundry customers are seeing a need to move to 3D transistor architectures with minimal leakage, she said, because of those power requirements.

Development will continue at 20nm and 16nm as well at TSMC and its rivals. This year, 88% of the 9 billion NT that TSMC will spend on capital expenditures will go to 28nm, 20nm and 16nm capacity; an additional 5% will be spent on additional R&D equipment. Chang predicted that by Q3 of this year high-k metal gate production will surpass that of standard oxynitride gates, a gap that naturally will widen in Q4 and beyond.

“Enough discussions have taken place with enough customers … to lead us to believe that in both its first and second year of production (2014 and 2015, respectively) the volume of 20nm SoCs will be larger than that of 28nm in its first and second years of production (2012 and 2013),” Chang said.

He further noted that this represented the state of the art, and not just for the foundry industry, but for the industry as whole. This may indeed prove to be true in a few years as those 20nm and 16nm/14nm SoC devices move into production. It’s a far cry from the days when foundries were traditionally technological also-rans.

But then the first-tier foundries at the leading edge are still playing catch-up in the meantime with those IDMs at the leading edge, namely Intel. The world’s biggest chipmaker has kept Moore’s Law on track on the CPU side of the ITRS roadmap, last year having brought its Ivy Bridge processors to market. These feature 22nm transistors replete with finFETs; Intel’s own roadmap calls for 14nm designs to be in production in 2014; in terms of mobile SoCs like those the foundries are talking about, the company has promised its 22nm Atom SoCs will be in production in 2015.

“Intel seems to be able to continue to shrink because they spend a fortune on R&D,” said Gartner’s Freeman. “The foundries are pushing hard to catch up,” He noted that while both GlobalFoundries and TSMC have 16nm/14nm chips featuring finFETs in development, they are taking a shortcut, so to speak, by employing 20nm metal interconnects. “It’s close to what Intel is doing. Intel’s design may be more sophisticated, but the lithography is the same.”

Plenty of room, and business, at the trailing end
But not everybody in the foundry market is playing at the leading edge. The same market and industry forces that have induced the bigger pure-play foundries to move beyond their historical roles also have created a two-tiered pure-play foundry market. In the first tier are those that have the deep pockets to play in this space: TSMC, Globalfoundries, UMC, and to a lesser extent China’s Semiconductor Manufacturing International Corp. (SMIC).

Then there are the second-tier companies, those that are still fulfilling a traditional foundry role—at trailing edge processes, but nevertheless needed or even essential semiconductor manufacturing technology and capacity. Indeed, many second-tier foundries do quite well with their particular market niches and technologies. In the world of mobile consumer gadgets, including but not limited to smartphones and tablets, there are still many components fabricated on established, trailing-edge technology, such as sensors, microcontrollers and power components.

Even in 2013, where CPUs with 22nm transistors and mobile SoCs with 28nm transistors represent the current state of the art, some 40% of all silicon used to manufacture chips goes into mature devices fabricated on 200mm wafers. That’s typically 0.18-micron designs or larger. And much, if not most, of that is coming from pure-play foundries.

At the top of that second-tier foundry market, Israel’s TowerJazz, for example, has found a relatively comfortable niche making high-speed devices for a broad range consumer applications utilizing 0.13-micron designs and larger. It also makes CMOS image sensors with 0.16- and 0.11-micron design rules. In terms of financials, this has translated to record revenues: last year TowerJazz posted revenues of $638.8 million, an increase of 5% over the previous year.

Freeman suggested there are plenty of opportunities for these second-tier foundries. The so-called “Internet of Things,” for example, is a major driver behind sensor applications, as it is for the controllers needed to coordinate the data these sensors produce—data that can be managed via mobile Internet devices. These supplemental and complementary applications typically don’t need cutting-edge technology.

As has always been the case in the foundry industry, as leading-edge technology becomes trailing-edge, there will be new opportunities for second-tier foundries, as well. Some of the larger second-tier foundries eventually may have the opportunity to compete with first-tier companies head-to-head with 28nm capacity if they have deep-enough pockets to invest.

In the bifurcated smartphone market, for example, low-end smartphones that originally utilized chips manufactured with 40nm technology soon will migrate to chips with 28nm technology, as capacity ramps and it becomes even more cost effective, said Applied’s Ta. Even as the leading-edge players are driven beyond the 28nm node and the adoption of 3D gate architectures, the industry could very well see an extended 28nm node, driven by this market for lower-end smartphones and other mobile devices, she said.

But What About …
Things rarely ever prove to be so clearly defined in the chip industry. With players such as Samsung, Intel and IBM among others flirting with the foundry business, and some of the larger first-tier foundries suffering the same financial headaches that have plagued the IDMs in the past—problems that drove some of them to a fabless model in the fist place—there are some significant unknowns.

While 3D, high-k metal gate architectures, i.e, finFETs and the like, seem to be the wave of the near future, there are still those in the industry that tout the efficacy of fully depleted silicon-on-insulator (FD-SOI) as either an alternative to complement to 3D gate technology, for example.

IBM and its technology alliance partners have considered FD-SOI as a possible outcome of the semiconductor technology roadmap in the near future, Ta noted. “We see most of the effort on the finFET/Intel approach, but some of our customers are still talking about SOI,” perhaps used in some combination with finFETs, she added.

Gartner’s Freeman noted that Intel’s finFET devices are already fully depleted devices, although SOI could conceivably provide a bit less leakage; as such it may be an option at future nodes. Given the transistor speed and power usage achieved by its 22nm Atom processors, which are manufactured on top of bulk silicon technology, that seems unlikely though for Intel and those choosing to follow its lead. Freeman further observed that GlobalFoundries, once a proponent of FD-SOI, has backed off somewhat, although some of its largest customers remain committed to an FD-SOI strategy for the foreseeable future. IBM, for one, has publicly stated it will use FD-SOI, finFETs and stacked die together at future nodes.

But what does this mean for the leading-edge foundries? As always they will have to be able to manufacture what their customers want. It may be that some chipmakers will choose to go the FD-SOI route and that could prove a competitive opportunity for any foundry.

Another wild card that the top-tier foundries will need to take into account is the overlapping of technology nodes, which may become more pronounced with the extension of the 28nm node coupled with the rush to get 20nm devices into production. “It’s happening faster than previous node transitions have happened,” Applied’s Ta, noting that it’s driven by the low-power promise of finFETs. In the past node transitions typically took two to 2.5 years; “This time we may see a 1.5 year transition to finFETs,” she added.

Another question mark in the foundry market itself is SMIC. While most would still classify the Chinese foundry as a top-tier foundry, it is in a very real way straddling the gap between first and second tier. The company, once relatively close behind TSMC and UMC, has foundered in red ink and legal woes in recent years. While it has subsequently experienced an impressive turnaround financially under the helm of current CEO Tzu-Yin Chiu in 2012, it’s capital expenditures fell dramatically, even as capacity utilization hit 95% in Q2, and it is well behind its rivals in terms of technology.

Customer tapeouts of 28nm devices won’t take place until the end of this year; One of SMIC’s largest domestic customers, Spreadtrum, already has been forced to move to rival TSMC to meet its current plans for 28nm devices.

SMIC’s Chiu has said that the company’s 28nm technology will include both standard polysilicon oxynitride devices and high-k metal gates, and that it has plans to manufacture finFET devices at the 20nm node. In the meantime, it has found a saving grace in applications typically manufactured by second-tier players: smart cards, CMOS image sensors and power management chips.

Which way will SMIC go? Will it continue its impressive turn around by abandoning the leading edge or will it continue to play technological catch up? Or perhaps a little bit of both?

Time will tell. But it’s certainly an interesting time for the foundry business, and certain that for the foreseeable future the pure-play foundries will have to work hard at the cutting edge of semiconductor technology.

By Mark LaPedus
What impact will Intel have on the overall foundry business? In a research note, Weston Twigg, an analyst with Pacific Crest Securities, said: “Competition between Intel and the foundries, and the foundries and each other, should force high spending at the leading edge over the next two to three years. We remain bullish on equipment demand as long as Intel continues to play an aggressive role in the x86 versus ARM battle and its new foundry effort. We believe Intel is attempting to exploit its manufacturing technology advantage, which should pressure rivals TSMC and Samsung to maintain aggressive node transition plans.”

Staying in the leading-edge process technology race requires deep pockets. At 20nm and beyond, chipmakers will have to raise the CapEx ante to stay in the race. “Capital and production costs are rising faster than historic levels as logic and foundry producers migrate to 20nm and below,” Twigg said. “We expect equipment costs to rise 25% at the 22nm node and 28% at the 14nm node. New gate technologies, along with multiple-patterning steps and pitch-splitting techniques, are driving costs higher.”

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena—a series of events that brings the technology one step closer to mass production.

In coordination with the National Academy of Sciences, GlobalFoundries helped host a conference titled, “New York’s Nanotechnology Model: Building the Innovation Economy” at the Hudson Valley Community College in Troy, N.Y.

Fabless ASIC house Socle Technology named Michael Noonen as its new chairman. Noonen is still the executive vice president of global sales and marketing at GlobalFoundries, which is an investor in Socle.

The Silicon Integration Initiative (Si2) said that the ESD Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.

Mentor Graphics announced availability of a comprehensive IP-to-system, UPF-based low-power verification flow.

ARM and Cadence disclosed the details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16nm finFET process.

Peregrine Semiconductor said that its UltraCMOS phase locked loop (PLL) frequency synthesizer and prescaler devices are designed into six Globalstar mobile communication satellites that were launched into orbit in February. UltraCMOS is an advanced RF silicon-on-Insulator (SOI) process.

Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials, has been named a fellow of the Institute of Electrical and Electronics Engineers (IEEE).

Sematech executive Raj Jammy has joined Intermolecular as senior vice president and general manager of the semiconductor group.

RF Micro Devices announced the appointment of James Clifford, a former executive at Qualcomm, as vice president of foundry services.

More than one quarter of installed wafer capacity worldwide is dedicated to producing IC devices using process geometries smaller than 40nm, according to IC Insights.

In 2012, Intel retained the No. 1 market share position for the 21st year in a row, according to Gartner. Qualcomm climbed from No. 6 in 2011 to No. 3, and now trails only Intel and Samsung. Texas Instruments retained its fourth-place ranking, although Toshiba slipped to fifth place.

By Mark LaPedus

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena–a series of events that brings the technology one step closer to mass production.

On the 3D front, GlobalFoundries has produced its first functional 20nm silicon wafers with integrated through-silicon vias (TSVs). At its Fab 8 facility in Saratoga County, N.Y., the silicon foundry vendor manufactured TSV test wafers using its 20nm-LPM process technology.

At the same time, the company also demonstrated a 32mm x 26mm interposer test vehicle for 2.5D chips. For some time, it has been developing a 65nm interposer manufacturing line within its Fab 7 complex in Singapore.

These are key steps to enable the eventual production of 2.5D and 3D chips. GlobalFoundries’ next step is to work in conjunction with its chip-assembly partners. At some point in the future, the OSATs will take the TSV-enabled wafers and then assemble and qualify 3D test vehicles for customers.

GlobalFoundries is making progress on other fronts. It is taping out a 3D design for an undisclosed customer and is working with two others on 2.5D. “2.5D is already here,” said David McCann, vice president of packaging technology at GlobalFoundries.  “Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality.”

Other foundries, including IBM, Samsung, Tezzaron, TSMC and UMC, are also ramping up or developing their respective 2.5D/3D capabilities. But advanced chip stacking has several challenges and is still a few years away from mass production. Some estimate that volume production won’t occur until 2014 or 2015.

E. Jan Vardaman, president of TechSearch International, said the ability to obtain stacked memory is one of the stumbling blocks for 3D designs.  Devices based on the Wide I/O-2 standard are not due out until 2014 or 2015. “Everyone is waiting for the memory cubes,” Vardaman said. “The main question is when are the memory cubes going to ship?”

There are other issues as well. “I think that a number of people are trying out new materials to handle the bond/debond step. That takes more time,” she said. “Many companies indicated they still needed floor planning tools.”

Cost, of course, is still a factor. “Once the technology issues are resolved, the industry will need to bring up the yields in order to lower the cost,” she added.

Still, GlobalFoundries is moving full speed ahead in the arena. Last year, the company entered the 2.5D/3D chip-stacking foundry market and began to install the production tools within its Fab 8 complex.

Now, the company has developed the first 20nm silicon with TSVs, which measure 6u in diameter and 60u deep. “Our integration strategy works for TSV,” McCann said. It is also obtaining good results and yields with its silicon interposer technology in Singapore, he added.

GlobalFoundries’ strategy is far different than TSMC and Samsung, both of which are offering turnkey solutions. In contrast, GlobalFoundries will handle the traditional front-end steps and the “via creation” process. Then, the foundry vendor will hand off the traditional backend steps—such as temporary bonding/debonding, grinding, assembly and test—to the third-party packaging houses.

GlobalFoundries’ strategy, according to McCann, is more flexible and has more advantages over the turnkey model. “Our supply chain is an open model,” he said.

Like its rivals, GlobalFondries utilizes a “via-middle” approach to TSV integration. To overcome the challenges associated with the migration of TSV technology from 28nm to 20nm, the company has developed a proprietary contact protection scheme. This scheme enables the company to integrate the TSVs with minimal disruption to the 20nm-LPM platform technology, demonstrating SRAM functionality with critical device characteristics in line with those of standard 20nm-LPM silicon.

By Mark LaPedus
Amid ongoing delays and setbacks, extreme ultraviolet (EUV) lithography and multi-beam e-beam have both missed the 10nm logic node. So for the present, chipmakers must take the brute force route at 10nm by using 193nm immersion with multiple patterning.

Now, it’s time to hit the reset button. For the 7nm node, chipmakers currently are lining up the lithographic competition. As before, with perhaps a slightly different twist, the candidates are EUV, multi-beam and the old standby, 193nm immersion with multiple patterning.

The same candidates also are competing for next-generation DRAM and NAND production. Nanoimprint is vying for a spot in NAND. But another option, directed self-assembly (DSA), could change the entire landscape if chipmakers can bring the technology from the lab to the fab.

Based on the delays with EUV, chipmakers could end up using 193nm with multiple patterning at 7nm. But they also are shuddering at the thought, as the costs and complexities for multiple patterning are enormous.

At 7nm, IC makers would prefer to use EUV or maskless for the critical or cut layers. But after a series of ongoing delays with these next-generation lithography (NGL) candidates, lithographers clearly are frustrated and beginning to run out of patience. “I am not happy with the progress of EUV,” said Burn Lin, vice president of research and development at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). “I am also not happy with the progress of maskless, but it is making progress.”

Lin, considered the father of immersion lithography, is the industry’s biggest proponent for multi-beam e-beam. In addition, TSMC has installed an EUV scanner and recently invested in ASML to jumpstart technology. Intel and Samsung also have invested in ASML.

EUV or bust?
For now, chipmakers hope to put EUV in pilot production at the 10nm logic and next-generation memory nodes. At 7nm, EUV remains the leading NGL candidate, with maskless running a distant second. TSMC still has EUV and maskless running neck-and-neck, although both technologies could be used in production for different applications.

To date, the progress with EUV is mixed. ASML Holding’s production-worthy EUV scanner, the NXE:3300B, is ready to roll. The scanner has a numerical aperture (NA) of 0.33 and a resolution of 22nm (half-pitch). ASML plans to ship the first NXE:3300B in the second quarter of 2013, but the throughputs are far less than previously advertised.

The throughput issues are due to the source, which is being developed by Cymer. The development of the EUV source has been “more difficult than what we anticipated,” said David Brandt, senior director of EUV marketing and business development at Cymer, which recently was acquired by ASML.

Last year, Cymer promised to ship a 100 Watt source by the end of 2012. So far, in the lab, Cymer has demonstrated the ability to generate 40 Watts and 50 Watts of EUV power. A 55 Watt source translates to an EUV throughput of 43 wafers an hour.

Cymer’s EUV source is based on laser-produced plasma (LPP) technology. In LPP, plasma is generated by a laser pulse hitting a target. The source also makes use of a pre-pulse laser and a master-oscillator power amplifier (MOPA), which will help generate more EUV power.

By the end of 2013, Cymer hopes to ship an 80 Watt source with a MOPA upgrade, enabling an EUV throughput of 58 wafers per hour. By 2015, ASML hopes to ship an EUV scanner with a 250 Watt source, which translates to a throughput of 126 wafers an hour.

Two other vendors, Gigaphoton and Xtreme, are racing against Cymer to deliver a 250 Watt EUV source. So far, Gigaphoton has achieved an EUV light output equivalent to a maximum of 20 Watts, said Yuji Minegishi, manager of the sales division for the company.

By 2015 or so, the IC industry is expected to be at the 10nm node. EUV is a 13.5nm wavelength technology, meaning chipmakers must use multiple pattering with EUV. With self-aligned double patterning (SADP), ASML’s NXE:3300B has demonstrated resolutions down to 9nm.

But if EUV is used in conjunction with double patterning, the EUV scanner itself will require twice the source power than before—or about 500 Watts, contends TSMC’s Lin. However, to deal with the resists, Yan Borodovsky, a senior fellow and director of advanced lithography at Intel, recently said that EUV source power needs to be in the range of 1,000 Watts.

Another way to extend EUV is by moving to higher NAs. For example, with an NA of 0.45, an EUV scanner can print 9.5nm feature sizes, but the image contrast drops, according to Zeiss. To address that problem, the current 4X magnification scheme can be increased to 6X or 8X.

Current EUV scanners with 4X magnification support standard 6-inch photomasks. A 0.45 NA lens with 6X magnification may improve EUV resolutions, but in some cases, that solution may require the photomask industry to move to a new and larger 9-inch mask size. In other words, photomask tool makers must develop new equipment.

“I don’t think we should give up on 4X just yet,” said Harry Levinson, senior fellow and manager of strategic lithography technology at GlobalFoundries, at the recent SPIE conference. “We may be able to extend 4X a bit. Maybe for a later node, we can go for more of these radical changes, such as larger format masks and higher lens reductions.”

Still, Levinson urged the industry to explore the idea of moving toward 9-inch masks, a move that is less painful than some might think. To support 9-inch reticles, the optics and other critical parts of a photomask tool will not need to be re-engineered, but vendors will need to develop new handling systems, he said.

In another scenario, EUV with 8X magnification could support 6-inch masks, but scanning would be done in a smaller field size. “You put this all together and we get less than half the throughput at 8X than 4X,” he said. “This is not an attractive situation.”

Beam me up
Amazingly, multi-beam e-beam or maskless lithography has seen more delays than EUV. Summarizing the state of multi-beam, Serge Tedesco, lithography program manager at CEA-Leti, said: “It’s a shame. There is a lack of support from the industry, when you compare it to the EUV side. This is one of the reasons why the technology is not mature yet.”

In 2002, for example, Mapper Lithography claimed that within three years it would ship its 13,000-beam tool for the 45nm node. As it turned out, Mapper’s initial production tool, which only will consist of 1,300 beams, won’t ship until the end of 2013.

Two other vendors, KLA-Tencor and Multibeam, are separately developing multi-beam tools. In another major move, Golden Gate Capital, a venture capital firm, recently sold its e-beam company, Vistec, to two different companies.

In one transaction, Raith recently acquired Vistec’s Gaussian e-beam unit, called Vistec Lithography. Vistec Lithography continues to specialize in conventional direct-write applications in the aerospace and military arena.

In a separate move, the Heidenhain Group recently acquired Vistec’s variable shaped beam (VSB) e-beam unit. That operation, Vistec Electron Beam, sells a single-beam e-beam tool based on VSB technology. It also is working on a multi-beam tool based on a variant of VSB called multi-shape beam (MSB), said Ines Stolberg, manager of strategic marketing at Vistec Electron Beam.

Given that MSB is based on proven VSB technology, Vistec Electron Beam may have an advantage over rival multi-beam approaches, said Hans Pfeiffer, principal of HCP Consulting. “This has a greater chance for success,” Pfeiffer said.

Multi-beam’s future still remains unclear, as only two entities, CEA-Leti and TSMC, are basically propping up and supporting the entire industry. CEA-Leti recently launched the Imagine Program, a multinational consortium aimed to bring maskless into production.

TSMC is working with both KLA-Tencor and Mapper. For years, KLA-Tencor has been developing what it calls Reflective Electron Beam Lithography (REBL). REBL makes use of a six-wafer rotary stage and a linear column. The 75-100-KeV design also consists of a CMOS-based digital pattern generator module, a 4,096 x 247 pixel array unit that enables more than 1 million beams at full current.

When operating with the rotary stage, REBL has demonstrated the ability to print 120nm half-pitch resolutions, a modest effort at best. In a static mode, the tool demonstrated 28nm resolutions, said Thomas Gubiotti of KLA-Tencor. A high-throughput version of REBL is due out in 2015.

Rival Mapper is developing a multi-beam tool, which is supposed to consist of 13,260 beams with sub-25nm resolutions. However, the first production tool, dubbed the Matrix 1.1, will consist of only 1,300 beams and a throughput of 1 wafer an hour, according to CEA-Leti. In June, CEA-Leti is expected to receive one of the first Matrix 1.1 tools. First exposures for the Matrix 1.1 are slated for the fourth quarter of 2013.

By 2015 or 2016, the overall goal is to cluster 10 Matrix systems together, enabling an overall throughput of 100 wafers an hour. In terms of the cost-of-ownership (COO), the Matrix runs €1 million for a system with a throughput of 2 wafers per hours, €5 million for 10 wafers an hour, and $50 million euros for a 10-cluster unit.