By Mark LaPedus
Qualcomm has the highest market share for baseband solutions in handsets, resulting in a position far out in front of its competitors. ST-Ericsson has strong products on the market with competitive features. But one analyst at ABI Research questions why ST-Ericsson was broken up just as it finally came out with a highly competitive product, which was based on FD-SOI.

The worldwide semiconductor foundry market totaled $34.6 billion in 2012, a 16.2% increase from 2011, according to final results by Gartner. TSMC maintained the No. 1 spot in the rankings in 2012. Strong performance on 32nm yields and the availability of sub-45nm wafer capacity at the Dresden, Germany, fabs allowed GlobalFoundries to advance to the No. 2 position in 2012. UMC‘s market share decreased due to reduced wafer shipments. Driven by the wafers consumed by Apple, Samsung moved up four spots to the No. 5 position with 175.5% growth in 2012.

At this year’s Symposium on VLSI Technology, Intel will report technical details of its embedded DRAM with 22nm technology on bulk silicon wafers. Intel realized a 0.029mm2 DRAM cell capable of meeting >100us retention at 95 C. In the DC-DC converter session, Intel will present a switched capacitor step-down converter designed in a 22nm tri-gate CMOS technology. The VLSI Symposium is slated for June 11–14 in Kyoto, Japan.

At the VLSI event, STMicroelectronics and CEA-LETI will report six transistor SRAM (6T-SRAM) cells for high-density and low-voltage. The technology is fabricated at the 28nm node using FD-SOI technology for the first time.

At the VLSI Symposium, IBM and GlobalFoundries will report a SiGe channel tri-gate pFET with aggressively scaled fin width and gate length dimensions. It is fabricated using SiGe on an insulator substrate. Excellent electrostatic control down to Lg= 18nm and Wfin<18nm has been reported.

At the event, IMEC and GlobalFoundries will present the first demonstration of strained germanium channel pFETs fabricated on SiGe strain relaxed buffers, which is surrounded by STI region. Also, they introduced raised SiGe source/drain structures (Ge concentration= 75%) with an implant-free quantum well, replacement metal-gate process and germanide in contacts to solve void issues.

In addition, STMicrolectronics, Samsung, GlobalFoundries and IBM will report a 64nm pitch BEOL integration and material strategy. A self-aligned-via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask.

SEMI reported that for the quarter ending Dec. 31, 2012, the worldwide photovoltaic manufacturing equipment book-to-bill ratio remained well below parity, at 0.45, for the seventh consecutive quarter. Booking levels continue to be low as PV manufacturers grapple with oversupply across the supply chain.

Khaled Juffali Company (KJC), a Saudi Arabian investment company, and Soitec, signed a memorandum of understanding (MOU) to cooperate in driving solar industry growth in Saudi Arabia and the Middle East. Under the MOU, the two companies will create a joint venture to market and sell concentrator photovoltaic (CPV) systems in the Kingdom of Saudi Arabia.

Hwa Chong Institution emerged as the winner of the Applied Materials Clean Tech Competition in Singapore. The project focused on utilizing calcium carbonate found in clam shells to remove toxic metal ions from waste water.

The separate hardware and software teams in companies are notorious for not being on the same page, thereby putting product development times and cost at risk. Mentor Graphics CEO Walden Rhines outlined some new and practical solutions to the problem.

Mentor Graphics announced the release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon. The tool provides a tighter connection between hardware and software co-development, but allows software developers to use existing programming tools with extensions.

Cadence announced results for the first quarter of fiscal year 2013. Cadence also completed its previously announced acquisition of Tensilica.

Advantest will acquire W2BI, a provider of system level test automation software focusing on wireless communications.

Shipments of smart glasses may rise to as high 6.6 million units in 2016, up from just 50,000 in 2012, for a total of 9.4 million units for the five-year period, according to an upside forecast from IMS Research.

The worldwide mobile phone market grew 4% year over year in the seasonally slow first quarter of 2013 as smart phones out-shipped feature phones for the first time, according to IDC. Nokia, BlackBerry and HTC have dropped out of the top rankings.

By Ed Sperling
STMicroelectronics yesterday unveiled the results of its 28nm production silicon chips using fully depleted silicon on insulator technology, which it claims offers a 30% improvement in speed over bulk CMOS while using less power.

The debate over FD-SOI and FinFETs has been notching up over the past few months. While FinFETs and FD-SOI both promise improvements in controlling leakage current, the FinFETs are more difficult to design. FD-SOI uses the same design flow, although it does use a different SPICE model with better characteristics than the one used for bulk CMOS.

ST also used an ultra thin body and box (UTBB) and body biasing to boost performance, according to Joel Hartmann, the company’s executive vice president of front-end manufacturing and process R&D. Hartmann presented his results at an SOI Consortium-sponsored event at the IEDM show last night.

“We are using body bias to boost performance,” Hartmann said. “You can do that with FD-SOI. We also decreased the Vdd of the device by applying body biasing.”

What’s particularly attractive about FD-SOI is that is can be implemented at the 28nm node for a boost in performance and a reduction in power. The mainstream process node right now is 40nm. And while Intel introduced its version of a finFET transistor called Tri-Gate at 22nm, TSMC and GlobalFoundries plan to introduce it at the next node—whether that’s 16nm or 14nm. That leaves companies facing a big decision about whether to move all the way to 16/14nm to reap the lower leakage of finFETs, whether to move to 20nm on bulk, or whether to stay longer at 28nm with FD-SOI.

Hartmann said ST has seen improvements in analog running on FD-SOI, and for memory where the minimum voltage required is lower. He said ST’s road map calls for FD-SOI all the way down to 10nm, with voltages dropping from 0.9v at 28nm to 0.8v at 14nm and 0.7v at 10nm.

One of the sticking points in adopting FD-SOI has been market acceptance. Despite the promise of improved performance and/or lower power, bulk CMOS has been extended using a variety of techniques such as strain engineering and FD-SOI is considered more expensive. At 28nm and beyond, however, bulk has run out of steam, which is why Intel has opted for finFETs.

Still, FinFETs are more difficult to design and manufacture, and they potentially can add significantly to the cost of an SoC. FD-SOI, in contrast, uses the same design tools and reduces the number of masks and metal layers. ST is the first large fab-lite company to adopt FD-SOI and to move beyond just test chips. It remains to be seen which path the rest of the industry takes—and how quickly.

By David Lammers

Intel will provide technical details of its tri-gate technology and 22nm MPU circuitry at the 2012 Symposia on VLSI Technology & Circuits, planned for June 12-15 in Honolulu.

The IBM-led semiconductor research alliance will detail its gate-last HKMG technology, as well as its bulk (see photo at bottom) and SOI-based transistor technology for the 22nm generation.

Heterogeneous transistor research will be front-and-center at the technology symposium, with papers from the University of Tokyo describing progress in the integration of a III-V nFET and a Ge-based pFET.

Transmission electron micrographs of Intel’s 22-nm-generation tri-gate PMOS transistors under the gate (left) and in the source/drain region (right).

It remains to be seen what new information Intel will divulge at the VLSI Symposium on Technology, as the Intel paper abstract was not included in the finFET session description.

The abstracts for the other four papers in the finFET technology session describe channel doping and silicide implant approaches, and work on nanowire devices which may succeed conventional finFETs.

A joint paper by the IBM Research Division and GlobalFoundries describes the methods used to create a multiple Vth solution for 22nm finFETs. The team investigated the impact of finFET channel doping on relevant device parameters such as Tinv, mobility, electrostatic control and Vth mismatch. “The absence of a body contact in finFETs and insensitivity to back-gate bias leaves the conventional channel doping approach as the most practical technique to achieve multiple Vth,” the IBM-GF team argues.

Cross-sectional transmission electron micrograph of an IBM 22-nm-generation SiGe-channel transistor with an extremely thin body thickness of 6 nm.

Also, Ali Khakifirooz and colleagues at IBM Research will detail their work on extremely thin SOI (ETSOI) devices, including efforts to strain the 22nm planar transistors and create implant-free raised-source/drain structures.

A paper from researchers based at Sematech and the University of Albany’s College of Nanoscale Science and Engineering (CNSE) describes contact formation with antimony (Sb) co-implantation and segregation to reduce Schottky barrier height (SBH) and parasitic series resistance for nFET FinFETs. “Experiments with shallow Sb, Ge, and As co-implantation in the source/drain (S/D) regions of SOI FinFET structures found that all three implant species significantly reduced extrinsic resistance,” the paper abstract reports, with the best results from the Sb implant.

Nanowires create the possibility of gate-all-around transistors. A paper from Toshiba and the Tokyo Institute of Technology describes 10nm-diameter tri-gate nanowire transistors based on a thin buried oxide (BOX). The abstract said the approach features “Vth tunability, small variability and negligible self-heating,” while optimized S/D and stress memorization technique (SMT) “lead to significant parasitic resistance reduction and mobility enhancement.”

A presentation from researchers based at CEA-LETI, Minatec, STMicroelectronics, and IMEP-LAHC describes performance improvements to finFETs and Omega FETs by straining the nanowires. “For the first time, an improvement of electron mobility in strained SOI nanowires scaled down to 10nm width has been successfully demonstrated,” the French researchers reported, with a 55% advantage compared with unstrained SOI nanowire transistors.

IBM Alliance and Applied Materials will describe a novel cobalt-Al-based metal fill scheme which can scale to 11-nm gates. Bright-field transmission electron micrograph of a filled 25-nm metal gate electrode (a), and corresponding elemental maps of the individual layers present in the gate stack (c-d).

An IBM Alliance report on its replacement metal gate (RMG) process is among several papers on high-k/metal gate (HKMG) technology. The team – including IBM, GlobalFoundries, Samsung, and STMicroelectronics – said the gate-last approach requires gate fill with low resistance materials on top of work function tuning metals. The abstract describes a cobalt (Co)-aluminum based metal fill scheme, including a promised discussion of the CMP challenges and an “assessment on resistance and device characteristics of this new low resistance fill scheme.”

The HKMG session includes presentations from Korea’s KAIST, Europe’s Imec, and others.

IBM Alliance's 20nm bulk transistor. A cross-section scanning electron micrograph of an IBM Alliance 20-nm-generation planar bulk CMOS chip, showing a dense (64-nm minimum pitch) hierarchy of metal wiring. (Source for all photos: 2012 VLSI symposia)

Continuing a tradition of programmable logic serving as a driver of foundry technology, Tabula Inc. (Santa Clara) said Tuesday (Feb. 21) that it is working with Intel Custom Foundry to manufacture Tabula’s programmable logic devices on Intel’s 22nm tri-gate process.

Intel last year signed up another FPGA house, Achronix, as a foundry customer. With their need for high-density and fast transistors, FPGA vendors have pushed foundries to the next node for several decades. Intel appears to be taking a similar path, working with innovative programmable logic vendors such as Achronix and Tabula which are eager to cut into the markets held by Altera and Xilinx.

Tabula said the combination of its innovative architecture and Intel’s smaller 22nm transistor process will give it a smaller die size and a technology lead over conventional FPGA vendors.

Tabula claims that it uses “time as the third dimension” to reduce the number of components needed to implement a function. Its “Spacetime” programmable fabric delivers an architecture with “dramatically shorter interconnects than traditional FPGAs and the ability to clock the entire fabric – logic, DSP, memory, and interconnect — at the same frequency.”

Tabula and Intel have been working together for some time prior to the public announcement, including an effort to co-optimize packaging technology. Tabula’s products are aimed at network infrastructure systems requiring high-bandwidth data flows such as switches, routers, packet inspection appliances, and other high-performance systems.

Daniel Gitlin, Tabula’s manufacturing vice president, is expected to discuss his company’s technology further on Wednesday at the Ethernet Technology Summit in San Jose. In a press release, Gitlin said the foundry relationship with Intel “will provide our company with a head start of several years, much as Intel achieved in 2007 by introducing high-k metal-gate (HKMG) transistors at the 45nm node.”

Sunit Rikhi, a vice president at Intel’s Technology and Manufacturing Group, said  Intel has worked closely with Tabula throughout the product design cycle to co-optimize Tabula’s 3PLD family with Intel’s 22nm manufacturing process and design kits.

Founded in 2003, Tabula is in volume production with its ABAX family, made on a 40nm process and operating clock speeds of up to 1.6 GHz.

By Mark LaPedus, SemiMD senior editor

In a presentation at the Intel Developer Forum (IDF) in San Francisco, senior fellow Mark Bohr claimed that the tri-gate-based process will bring power and performance advantages to 22nm system-on-a-chip (SoC) products that planar transistors will not be able to match. Bohr also provided a glimpse of Intel’s 14nm process.

Already planning to ramp up production of its 22nm products this year, Intel is moving full speed ahead to develop a 14nm technology. Intel plans to build on its vertical tri-gate transistor structure at the 14nm node by extending the strained silicon and high-k/metal-gate schemes, said Bohr, Intel’s director of process architecture and integration. He provided few details about the 14nm process, however.

Other companies, including IBM, GlobalFoundries and TSMC, are pursuing finFETs for the 14nm node. Intel plans to begin ramping up its 14nm process by the fourth quarter of 2013, Bohr said, claiming that Intel will have a “four-year lead in tri-gate technology.”

Bohr reiterated the company’s position that extreme ultraviolet (EUV) lithography will not be ready in time for the 14nm node. Intel has said it plans to extend traditional 193nm optical lithography down to 14nm, with the help of multiple patterning and other techniques.

“We would like to use EUV, but it’s not ready,” Bohr said in an interview, adding that “I’d like to have EUV” ready for the 10nm node.

Intel’s 22nm SoC Process

Bohr discussed Intel’s SoC process recipes for the 22nm node, a critical weapon in Intel’s effort to gain share in the smartphone space. In previous years, Intel developed a standard “one-size-fits-all” CPU process technology for a particular node.

Starting at the 32nm node, Intel developed a CPU (P1268) and an SOC (P1269) process. The CPU and SoC processes have identical feature sets, but the SoC version incorporates a superset of features optimized for SoC designers.

For example, Intel will provide a standard CPU process at 22nm, internally called P1270. Based on a tri-gate transistor structure, the CPU process incorporates high-speed logic circuits and interconnects.

The SoC version, dubbed P1271, makes use of a low leakage technology, dense interconnects and passives. It will also include 1.2V low-power and 1.8V thick-gate options.

Dick James, a technology analyst at ChipWorks, the Canadian reverse-engineering firm, said he believes the SoC process will roll out in Intel products sometime in 2012.

Intel will provide four SoC process flows or recipe options for designers: high-performance, standard performance, low power and ultra low power, according to Bohr.

(Source: IDF 2011)

The SoC technology is aimed at a range of applications, including the mobile space. Intel is seeking to propel its x86-based processors in the mobile space, and displace the ARM-based products in the process.

Bohr said Intel’s tri-gate transistor, rolled out in May, represents a fundamental departure from the two-dimensional planar transistor structure. The first tri-gate-based processor, code-named “Ivy Bridge,” is slated for high-volume production by the end of this year.

Bohr said Intel’s tri-gate structure enables a “10X reduction in leakage” over planar devices. Compared to tri-gate structures, ‘’22nm planar transistors would provide only a modest improvement in delay versus voltage,’’ he said, arguing that “tri-gate transistors provide an unprecedented 37 percent delay improvement at low voltage,’’ as compared with 32nm planar structures.

Intel’s first 22nm processor, called Ivy Bridge, is mainly geared for desktops and possibly higher-end notebooks. The next 22nm processor is code-named Haswell, which is tailored for Ultrabooks. Developed by Intel, Ultrabooks is a new class of portables that are aimed at the tablet PC market.

At IDF, Intel described the new class of platform power management in development for the 2013 “Haswell” products for Ultrabooks. Haswell will reduce idle platform power by more than 20 times over current designs, according to Intel.

By Ed Sperling
Mark Bohr, senior fellow and director of Intel’s process architecture and integration, sat down with Semiconductor Manufacturing & Design to talk about his company’s push into Tri-Gate, its future SoC direction and what will drive chip design and manufacturing in the future. What follows are excerpts of that conversation.

SemiMD: Will Tri-Gate be as repeatable for other types of less regular SoCs as for Intel’s processors?
Bohr: Yes. All of this is base technology that is intended to meet the needs of a wide range of products. That’s certainly true for the 22nm generation. The same Tri-Gate structures will be used on our high-performance processors as well as our low-power and SoC types of products.

SemiMD: Intel has always tried to limit the number of masks it uses for economic reasons. Can others do that, and can Intel do that for other types of chips?
Bohr: Intel historically has tried to minimize costs with the number of masking steps. That’s our goal on any technology—to deliver the best-possible density and the best-possible performance at the minimum amount of mask-out. But that’s getting more difficult for all of us. At 22nm we have to either start adding more interconnect layers to meet the needs of the high-performance processors or we have to start using more double-patterning layers to get down to the tight pitches and tight design rules. We’re still very cognizant and sensitive to keeping wafer costs low, but our processors—which range from high-performance to low-power Atom SoCs—will not use the same number of interconnect layers.

SemiMD: Is Intel looking at 2.5D and 3D stacking?
Bohr: Yes, absolutely. It’s not only how to optimize the transistor on the chip, but how you package multiple chips into a 3D form factor. We’ve been exploring TSV technology and 3D packaging for quite awhile and they’re coming along.

SemiMD: Is Wide I/O a major factor in this?
Bohr: That’s one of the ways to use 2.5D and 3D stacking. You can have a Wide I/O memory chip, which has better memory bandwidth at lower power so the memory solution is more power-efficient. But these small handheld devices also are very cost-sensitive. What’s holding us back now are the cost issues around TSVs and 3D stacking. We’ll see that solution coming, but it will not be widely adopted very soon.

SemiMD: Is it a matter of volume and experience?
Bohr: It’s that and drilling through the wafer and thinning down the wafer for stacking. Those are expensive added steps.

SemiMD: Is this all still bulk CMOS forever?
Bohr: When Intel looked at our Tri-Gate technology we settled on a bulk wafer. You can also make Tri-Gate or FinFET devices using SOI wafers, and some people may choose that. We felt our bulk approach was a bit more cost-effective, but there’s a good chance over the next five years that other companies will produce FinFETs using SOI wafers.

SemiMD: How about new channel materials? There was talk about indium gallium arsenide in the NFET and germanium in the PFET?
Bohr: Intel has been pretty active in researching that and publishing papers. Every year we’ve presented data at IEDM on channel materials. This is another good example of how we’re trying to explore new materials and new device structures to reduce operating voltage. 3-5 channel materials may get us from 0.7 volts down to 0.5 volts.

SemiMD: Where do we stand with EUV and eBeam?
Bohr: It probably won’t be available at 14nm, but we’re hoping it will be available for the generation after that.

SemiMD: What does that buy you?
Bohr: What Intel always does for technology as important as lithography is to pursue multiple parallel paths. When it comes time, that way we have more than one choice. We choose the one that best meets the dimensional capabilities as well as the cost. We have had our hopes on EUV for some time, but luckily we’ve also pursued immersion and double patterning in parallel. That has come up better than most of us dreamed possible. It’s not that EUV isn’t there yet, but double patterning with immersion has really delivered.

SemiMD: So you can get by with double patterning and immersion for the foreseeable future?
Bohr: Yes.

SemiMD: What will finally force a shift, if anything?
Bohr: It will come down to cost. Are two immersion-patterning steps more cost effective than a single EUV step? Right now, double patterning is more cost-effective.

SemiMD: When you look out a couple nodes, what does a chip look like? Is it still planar and denser, or is it a completely different approach?
Bohr: One important perspective is that chip technology is becoming more heterogeneous. If you go back 10 or 20 years ago, it was homogenous. There was a CMOS transistor, it was the same materials for NMOS and PMOS, maybe different dopant atoms, and that basic CMOS transistor fit the needs of both memory and logic. Going forward we’ll see chips and 3D packages that combine more heterogeneous elements, different materials, and maybe transistors with very different structures whether they’re for logic or memory or analog. Combining these very different devices onto one chip or into a 3D stack—that’s what we’ll see. It will be heterogeneous integration.

SemMD: It sounds as if you’re venturing heavily into the SoC world, where Intel hasn’t really been a force.
Bohr: Mainstream microprocessors are very much like an SoC chip. They’re not quite like what you expect in a smart phone, but if you look at the Sandy Bridge chip compared with a processor 10 years ago that was just logic transistors and SRAM memory. Today’s chips have integrated logic controllers, integrated graphics, a lot of analog elements and phase-lock loops. If you go into a different market, like a true SoC chip for a smart phone, then you have even more integrated functions. But that’s where Intel and our industry are headed—integrating more functionality into a small form factor, whether it’s an SoC or a 3D stack.

SemiMD: Is part of the goal to sell the whole device, or maybe just a piece of the device?
Bohr: The technology goal is to integrate as many functions into the smallest possible form factor for the lowest possible power. From a business perspective, a company that can do as much of that combined stack as possible will be in a better place than if you’re just one of the component suppliers.

SemiMD: But you probably won’t develop all the pieces yourself, right? For that, you’re going to need partners.
Bohr: Yes, and that’s the expected tension. Do you do all the pieces and control the full integration or do you do better if you pick and choose pieces from partners in the industry. The winning solution will probably be a compromise of those two. You may not do everything on your own, but maybe you do most of it.

SemiMD: This is a massively broader market for Intel.
Bohr: Intel is re-inventing itself. We are getting much more into this SoC business, and it requires different skills and interests as we put together all these pieces.

SemiMD: As a large IDM, Intel has the ability to define what goes where on a chip and how the chips that are stacked with it are designed.
Bohr: I don’t disagree with that. The more technology pieces you control internally, so you can do that co-optimization, the better the technology will be and the better your business will be.

SemiMD: Does that mean you now push only certain pieces to the bleeding edge of Moore’s Law?
Bohr: That’s certainly one of the options, and one of the desirable features, of the 3D stacking approach. You don’t have to use leading-edge technology to do the whole chip. You can use the right technology for the right part of the system.

SemiMD: And quickly too, right?
Bohr: Yes.

SemiMD: Most SoC developers are talking about more software content. Will that be part of this focus, particularly with the Wind River acquisition?
Bohr: I’m not a software expert, but one thing that is not well known is just how large of a software company Intel is. Wind River was just one acquisition, but we are among the top companies in the world in terms of the number of companies working on software.

SemiMD: But are the software and hardware teams now working together?
Bohr: There is a lot of collaboration. It’s not enough just to offer a certain core. The SoC circuits have to be optimized for the software.

By David Lammers

Intel Corp. may have as much as a five-year lead in bringing finFETs into widescale production, experts said. A dual-epi process, and close control over other steps, represent manufacturing challenges which may prevent other companies from quickly following Intel’s lead, they said.

Chenming Hu

Chenming Hu, who led a University of California at Berkeley team which proposed a workable finFET a dozen years ago, said “The main point is that Intel is taking FinFETs into production. Intel deserves a lot of respect, because they continue to lead the industry on a two-year cycle of scaling.”

Hu said the May 4 announcement “further bolsters their reputation as a company with a can-do attitude. And it shows that if an organization invests sufficiently, they can make a very good return on those investments. Initially, these transitions are going to be so very difficult, but if the right amount of time, money, and people are invested, they can get it done.”

“I remain steadfast in my comments about both FinFETs and UTB-SOI going to manufacturing. I expect both to go into production. The very large companies, such as Intel and TSMC, will have the resources to go to FinFETs. Some other companies may go to UTB-SOI. ST Microelectronics is probably the closest to using UTB-SOI,” he said, referring to the ultra-thin body silicon-on-insulator technology.

“FinFETs may be more versatile in performance and power. On the other hand, FinFETs take a lot more development resources, in terms of the manufacturing control, the layouts, and the libraries,” Hu said.

Making a finFET is challenging. “The sense that I have gotten is that the equipment industry was not much more in the know than the rest of the world, which tells me that Intel really didn’t have to do that much in terms of new equipment. If the interface with the design team is close, and the resources are large enough, the lure of finFETs is that they can be scaled. But it does take investments. UTB-SOI does not take as much technology development investment,” Hu said.

Hu said the fin must be very thin, about equal to the gate length, in order to accomplish the goal of suppressing the leakage current. To keep the fin thickness exactly the same across the wafer requires that the process be very well controlled.

“To scale the finFETs, the industry will need to make the fin thinner and thinner. Back in our 1999 paper, we theorized that it can be scaled to 10 nm, but now I believe we can go beyond that,” Hu said.

Thompson Sees Five-Year Lead

Scott Thompson, a professor at the University of Florida, said, “developing a complex technology like tri-gate requires significant investments in silicon resources and manpower — development teams of perhaps more than 1,000 people.”

Prof. Scott Thompson

The challenges, Thompson said, are so complex that Intel probably ran hundreds of thousands of wafers to solve the issues. Tri-gate is “at least an order of magnitude more complex than strained silicon at the 90nm generation or high-k metal gate at 45nm. That is why it took Intel eight years to implement and why I don’t think anyone else will have it in the market for more than five years,” said Thompson, who earlier worked as a technology program manager at Intel’s technology manufacturing group.

Tri-gate has quite a number of very innovative elements, he said, the most critical of which are “not in production in any foundry today.” The complexity resides in developing a true “gate-last” stack with dielectric and metal deposited last with atomic layer deposition (ALD) tools.

“The integration of the p+ SiGe S/D (with >50% Ge) / n+ Si S/(>1e19) requires a very sophisticated process, materials and exotic recipes. The fin silicon density present during growth appears to be very low and it appears challenging to get uniform epi on the fin’s etched sidewalls,” he added.

To have low contact resistance to the fins, epitaxy must be grown on the source and drain of the fins — otherwise the drive current and performance would suffer. “Based on Intel’s performance claims, it can be concluded for pFETs, a highly in situ doped boron p+ SiGe is grown on the fin for p-type transistors. For the nFET, silicon or doped silicon epitaxy needs to be grown on the source/drains.”

To grow the dual selective epitaxial films on pFETs and nFETs with low defects on the fins “is a difficult, complex and expensive process,” he said. To manufacture the dual epi, Thompson said he believes Intel “implemented many restrictive design rules on the layout of the fins. These new design rules will prevent reuse of legacy IP. None of these issues are a problem for Intel’s targeted market: high-performance and high-margin CPUs. But the economic trade-offs are different for the SOC world, where many different type of transistors are offered,” Thompson said.

Thompson said the fins on the 22nm tri-gate appear to be relatively short, and over the next two nodes Intel will likely try to make them taller. That provides more area. “But taller fins will introduce additional capacitance with a higher overlap capacitance between the fin and contact, and a larger gate capacitance. Variation along the fin height dimension increases the threshold variation, greater than the standard line edge roughness and will increase Vt variation, which is critical at 22nm and below.”

“Intel did not publish their AVT, but others have for a bulk finFET and reported a value of 2 mVum, which is higher than desired. The physics behind this is that it is very difficult to dope the fins, and random dopant effects (i.e. some fins get 50 dopant atoms and others get 100) cause drawn identical transistors to have different threshold voltages,” Thompson said.

Manufacturing perfect fins over billion or trillions transistors is “quite a challenge,” Thompson said, though Intel’s advantage is that Intel’s fabs run a single process, with equipment and settings that are kept constant.

“The tri-gate structure requires very complex elements that are difficult to control and reproduce with high yield. The manufacturing flow has unique advantages for high-end processors but it does have problems supporting several key features needed for SOCs: multiple Vt’s, and thin and thick oxides in support of analog. There still quite some work to do to use finFETs to manufacture SoCs like Apple’s A5 or Nvidia’s Tegra,” he said.

Intel’s development costs are difficult to compute, Thompson said, adding that “a realistic estimate could be upwards of $2 billion. Significant investments are needed to fund the required development for numerous new modules: new STI/fin pattering, mid-section etch modules, metrology all on fins, SiGe etch and deposition processes, new gate stack, and inline metrology modules.”

The cost of a new fab to produce 22nm wafers is high, in the range of $4-5B, which may be behind Intel’s decision raise its capital spending plan to about $10 billion this year, Thompson said.

Applied Sees ‘Bold Step’

Klaus Schuegraf, the chief technology officer at the Silicon Systems Group at Applied Materials, said “I think we first should recognize Prof. Chenming Hu and the device group at Berkeley for leading the vision in 1999. This is part of a decade-long quest into how to meet the ultimate capability of a transistor, with respect to its ability to turn on in a very abrupt fashion.”

Intel’s move at the 22nm generation “is a bold step, and it took courage by Intel to make it a reality. With finFETs we are in new territory,” Schuegraf said.

FinFETs require that the fin be “very vertical,” which presents challenges on a few fronts. To etch a structure at a near 90 degree angle, with no taper, is essential. “That etched structure is actually the channel for the device. If it slightly off-axis, the mobility of the transistor will be less than ideal.”

Lithography must be able to make a very narrow fin, less than the scanner’s resolution limit. “In this case, fin is in the same situation as the gate. The fin is less than the photo limits, so two layers have to be less.”

How to shrink the CD at such a tight pitch, how to etch the films to get a reliable shrink, at less than the photo limit and do it reliably, are just a few of the many challenges.

Working at the Dan Maydan Center, Applied’s technologists have been “working very diligently on CD uniformity on etch products, very precise control on etch processes. The need for this is universal, not just for finFETs but for many other structures” including flash and DRAMs, Schuegraf said.

By David Lammers

About four years ago, Intel Corp. committed to the tri-gate transistor architecture for its 22nm technology and set to work on the manufacturing and design challenges, said Kaizad Mistry, the 22nm program manager at Intel Corp.’s technology manufacturing group in Hillsboro, Ore.

Intel calls its finFET design a tri-gate transistor because current flows along the two sides and the top of the fin.

Kaizad Mistry

“We had long discussions, both within the technology group and with our design partners at Intel. The tri-gate technology is more challenging, and it did make design execution different, because the transistor width is now discretized. After the debate both within the technology group and with design emerged a consensus on both sides that the improved performance characteristics were worth the effort,” Mistry said.

Mistry said “the biggest challenge with the tri-gate technology is to have a robust manufacturing process, to pattern the fins with the required fidelity of the fin width and height, and do it for billions of transistors,” he said.

Extracting the full performance benefits requires dealing with the series resistance and parasitic capacitance issues, which he said were “secondary challenges.”

“The principal difficulty is maintaining the integrity of the fin,” he said. While more double patterning is required for the critical layers, Intel was still able to use immersion 193nm scanners. With no radically different techniques or equipment required, making the tri-gate required improvements in “conventional control,” a realization that bolstered Intel’s confidence several years ago when it committed to a tri-gate architecture.

Current flows on both sides and the top of the tri-gate device. Source: Intel Corp.

Controlling the width of the fin is important to limiting the short-channel effect (SCE). The width — and to some extent the doping — also is critical to setting the threshold voltage (Vt), and to fully deplete carriers from the depletion layer.

“The fin has to be at the right width to get that fully depleted behavior,” Mistry said in a telephone interview following the May 4 rollout of the 22nm platform.

There is a tradeoff for both the fin width and fin height. A skinnier fin provides the  fully depleted behavior, as well as controlling the short channel effect. But Mistry explained that “if the fin is too skinny, then the current resistance gets larger. Too wide, and we don’t get nice fully depleted behavior. Too narrow, and there is too much series resistance.”

There is a similar tradeoff for the fin height. A taller fin delivers more drive current, but at a higher gate capacitance. “The tradeoff is there, but it depends on the type of circuit, whether it has more interconnect load or more transistor load.”

The vertical structure supports a higher density, as the fins can be placed as close together as the lithography permits. And there is more transistor area with a vertical device than a planar design.

The effective transistor width, or W, equals twice the height plus the width, 2H plus W. Unlike planar transistors, which can be made with a variable width, the effective width is the same for every fin – a “discretized” W. Intel will use up to six fins, traversed by a single gate, in circuits requiring high drive current.

“With more fins, we get more drive current,” Mistry said.  And with a bigger area, there is more drive current. “We have to deal with the series resistance, and we don’t get more series resistance if we add fins in parallel. In a planar regime, we would draw a wider transistor, but with the tri-gate, the transistor is now discretized. Conceptually it is not different, we just have to deal in increments of one fin.”

The fully depleted tri-gate supports a steeper threshold swing than in a planar bulk transistor.  For partially depleted planar bulk transistors, as the gate is trying to turn the inversion layer off, the silicon substrate has a fixed influence on the inversion layer: the “body effect.”

In a fully depleted transistor, on the other hand, the substrate effect on the channel is turned off. For the tri-gate transistor, the effect of the silicon substrate is “completely shielded,” Mistry said, removing the body effect, and allowing the sub-threshold slope to be steeper.

In a fully depleted transistor, the width of the depletion region is less than the thickness of the silicon. While the width of the depletion region does depend on the doping level, Mistry said the Vt is less dependent on doping. “The silicon is not completely undoped, but it is much more lightly doped. Fewer dopants improves the performance, because there is less ion impurity scattering,” he said.

Ions provide free electrons or holes that provide charge to the rest of the dopant atoms stuck in place in the lattice. Ion impurity scattering reduces the mobility or velocity of the electrons or holes. “Having fewer dopant atoms does improve the transistor’s performance, particularly at low voltages,” he said.

With fewer dopants, there is a marked improvement to variations in the threshold voltage, the Vt mismatch. With a steeper sub-threshold slope and improved Vt mismatch, the threshold voltage can be lower, supporting a lower operating voltage.

The minimum voltage, or Vmin, that a circuit can operate at reliably is largely depending on the Vt mismatch. The  improved Vt variability allows circuits which must retain data — including cache memory, register files, latches, and others — to operate at a lower Vmin than Intel’s planar transistors.

A tri-gate transistor can have a lower operating voltage.

“We estimate we can drop the operating voltage by 100 to 150 millivolts, closer to 150,” Mistry said. “Depending on the type of circuit, we can operate anywhere from 100-150-200 millivolts better than planar.”

An operating voltage drop of 100 millivolts, combined with the transistor size shrink, means that the access power for a given logical function is cut by half, or more, while running at the same frequency. “That is a pretty big deal,” Mistry said, saying that advantage helped drive Intel towards the tri-gate design during its pathfinding stage.

The advantages in density, performance, and power led Intel’s design group to take on the design challenges. “Being an IDM is an advantage for us in that respect. Whenever the design tools need to change, we are able to partner very quickly to create the tools, and with the designers themselves.”

Asked if designing with a tri-gate was more complicated than with a planar transistor, Mistry said, “It is just different. I wouldn’t say it is more complex.” Earlier, the design tools created the optimum W for power and delay. That tool “now has to map a discrete width for a fin. That is not more complicated, just different.”

By David Lammers

Intel Corp. is developing a heterogeneous CMOS tri-gate solution that could be ready “seven or eight years down the road,” Intel fellow Paolo Gargini said during a presentation at the SEMI Industry Strategy Symposium (ISS) Europe event, held in Grenoble, France.

“It makes sense to look at germanium again” for the PFET, with a III-V indigum gallium arsenide (InGaAs) compound in the NFET channel, he said. By using chemical vapor deposition (CVD), germanium and InGaAs could be deposited locally on a silicon substrate. “It takes about five years to do, but with germanium we could get a saturation current that is 2X better at the same leakage than silicon, with a smaller supply voltage. The next step is to bring in the III-V’s,” Gargini said. He added that the heterogeneous Ge/InGaAs combination is one of several options that Intel is considering.

Intel has been researching InGaAs quantum well FETs, with an IEDM 2010 presentation on the work by Marko Radosavljevic and colleagues.  The IEDM paper includes details about a high-k dielectric applied to the III-V gate stack.

Gargini cautioned that single-crystal III-V channel materials “still have a lot of defects, so it may be seven or eight years down the road before we can make it workable. But a tri-gate with III-Vs is a real structure, it is not just a Powerpoint implementation.”

Gargini said Intel’s work on a FinFET structure – which Intel calls a TriGate transistor – would carry over into the heterogeneous Ge/III-V generation of technology. “It could come in by 2020 if we can make it manufacturable. We know it will work,” he said. During the SEMI ISS Europe presentation he called on Europe’s equipment and materials manufacturers to work with Intel on bringing the heterogeneous technology to fruition.

A Ge/III-V implementation exhibits better DIBL (drain induced barrier lowering), a key challenge at future CMOS nodes. “There is a reduced influence of the drain on lowering the voltage on the source,” he said. In the IEDM 2010 paper, Radosavljevic wrote that compared to the planar high-k InGaAs QWFET with similar Tox, the non-planar, multigate InGaAs QWFET has a better enhancement-mode Vt and significantly improved electrostatics due to better gate control.

At the SEMI ISS Europe event, Gargini was asked if CMOS is nearing the end of scaling. He said scaling “is not a beauty contest. We will squeeze the existing technologies to the limit. We will get the III-V technology ready, and then the manufacturing will be ready two to four years later.” He noted that heterogeneous Ge/III-V transistors have moved from the International Technology Roadmap for Semiconductors (ITRS) emerging technologies committee to the PIDS committee. Gargini is chairman of the ITRS general committee.

Further out, Gargini said he sees some promise in tunneling transistors, or TFETs. He described how the early work of Nobel Prize winner Leo Esaki in TFETs could provide a path toward band tunneling transistors, operating at 0.3 Volts. And the devices could be optimized for low leakage, providing one order of magnitude faster speeds and two orders lower leakage.

Fig. 1: Evolution of InGaAs QWFET from planar to non-planar, multi-gate architecture:
(a) Planar Schottky gate QWFET with source/drain comprised of n++ InGaAs cap, thick upper barriers and Si–doping.
(b) Planar QWFET structure similar to (a) except the Schottky gate is replaced by high-K/metal gate stack.
(c) Planar high-K QWFET similar to (b) except the thick upper barriers and Si-doping are removed in the S/D area [this work].
(d) Non-planar, multi-gate high-K QWFET, with the transistor channel being in the shape of a “fi”, and ultra scaled drain-gate and source-gate separations (LSIDE) [this work].
Eliminating the thick upper barriers and Si-doping in (c) and (d) while using n++ InGaAs cap as the carrier supply enables S/D contact area scaling with low resistance. (Source: IEDM 2010 presentation)