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Photonics in Silicon R&D Toward Tb/s

Tuesday, January 3rd, 2017


By Ed Korczynski, Sr. Technical Editor

The client:server computing paradigm colloquially referred to as the “Cloud” results in a need for extremely efficient Cloud server hardware, and from first principles the world can save a lot of energy resources if servers run on photonics instead of electronics. Though the potential for cost-savings is well known, the challenge of developing cost-effective integrated photonics solutions remains. Today, discrete compound-semiconductor chips function as transmitters, multiplexers (MUX), and receivers of photons, while many global organizations pursue the vision of lower-cost integrated silicon (Si) photonics circuits.

Work on photonics chips—using light as logic elements in an integrated circuit—built in silicon (Si) has accelerated recently with announcements of new collaborative research and development (R&D) projects. Leti, an institute of CEA Tech, announced the launch of a European Commission Horizon 2020 “COSMICC” project to enable mass commercialization of Si-photonics-based transceivers to meet future data-transmission requirements in data centers and super computing systems.

The Leti-coordinated COSMICC project will combine CMOS electronics and Si-photonics with innovative fiber-attachment techniques to achieve 1 Tb/s data rates. These scalable solutions will provide performance improvement an order of magnitude better than current VCSELs transceivers, and the COSMICC-developed technology will address future data-transmission needs with a target cost per bit that traditional wavelength-division multiplexing (WDM) transceivers cannot meet. The project’s 11 partners from five countries are focusing on developing mid-board optical transceivers with data rates up to 2.4 Tb/s with 200 Gb/s per fiber using 12 fibers. The devices will consume less than 2 pJ/bit. and cost approximately 0.2 Euros/Gb/s.

Figure 1: Schematic of COSMICC on-board optical transceiver at 2.4 Tb/s using 50 Gbps/wavelength, 4 CWDM wavelengths per fiber, 12 fibers for transmission and 12 fibers for reception. (Source: Leti)

A first improvement will be the introduction of a silicon-nitride (SiN) layer that will allow development of temperature-insensitive MUX/DEMUX devices for coarse WDM operation, and will serve as an intermediate wave-guiding layer for optical input/output. The partners will also evaluate capacitive modulators, slow-wave depletion modulators with 1D periodicity, and more advanced approaches. These include GeSi electro-absorption modulators with tunable Si composition and photonic crystal electro-refraction modulators to make micrometer-scale devices. In addition, a hybrid III-V on Si laser will be integrated in the SOI/SiN platform in the more advanced transmitter circuits.

Meanwhile in the United States, Coventor, Inc. is collaborating with the Massachusetts Institute of Technology (MIT) on photonics modeling. MIT is a key player in the AIM Photonics program, a federally funded, public-private partnership established to advance domestic capabilities in integrated photonic technology and strengthen high-tech U.S.-based manufacturing. Coventor will provide its SEMulator3D process modeling platform to model the effect of process variation in the development of photonic integrated components.

“Coventor’s technical expertise in predicting the manufacturability of advanced technologies is outstanding. Our joint collaboration with Coventor will help us develop new design methods for achieving high yield and high performance in integrated photonic applications,” said Professor Duane Boning of MIT. Boning is an expert at modeling non-linear effects in processing, many years after working on the semiconductor industry’s reference model for the control of chemical-mechanical planarization (CMP) processing.


Technologies for Advanced Systems Shown at IMEC Tech Forum USA

Tuesday, July 14th, 2015


By Ed Korczynski, Sr. Technical Editor

Luc Van den hove, president and CEO, imec opened the Imec Technology Forum – USA in San Francisco on July 13 by reminding us of the grand vision and motivation behind the work of our industry to empower individuals with micro- and nano-technologies in his talk, “From the happy few to the happy many.” While the imec consortium continues to lead the world in pure materials engineering and device exploration, they now work on systems-integration complexities with over 100 applications partners from agriculture, energy, healthcare, and transportation industries.

We are now living in an era where new chip technologies require trade-offs between power, performance, and bandwidth, and such trade-offs must be carefully explored for different applications spaces such as cloud clusters or sensor nodes. An Steegen, senior vice president process technology, imec, discussed the details of new CMOS chip extensions as well as post-CMOS device possibilities for different applications spaces in her presentation on “Technology innovation: an IoT era.” EUV lithography technology continues to be developed, targeting a single-exposure using 0.33 Numerical Aperture (NA) reflective lenses to pattern features as small as 18nm half-pitch, which would meet the Metal1 density specifications for the industry’s so-called “7nm node.” Patterning below 12nm half-pitch would seem to need higher-NA which is not an automatic extension of current EUV technology.

So while there is now some clarity regarding the pre-competitive process-technologies that will be needed to fabricate next-generation device, there is less clarity regarding which new device structures will best serve the needs of different electronics applications. CMOS finFETs using strained silicon-doped-with-Germanium Si(Ge) will eventually be replaced by gate-all-around (GAA) nano-wires (NW) using alternate-channel materials (ACM) with higher mobilities such as Ge and indium-gallium-arsenide (InGaAs). While many measures of CMOS performance improve with scaling to smaller dimensions, eventually leakage current and parasitic capacitances will impede further progress.

Figure 1 shows a summary of energy-vs.-delay analyses by imec for all manner of devices which could be used as switches in logic arrays. Spin-wave devices such as spin-transfer-torque RAM (STT-RAM) can run at low power consumption but are inherently slower than CMOS devices. Tunnel-FET (TFET) devices can be as fast or faster than CMOS while running at lower operating power due to reduced electrostatics, leading to promising R&D work.

Fig.1: Energy vs. delay for various logic switches. (Source: imec)

In an exclusive interview, Steegen explained how the consortium balances the needs of all partners in R&D, “When you try to predict future roadmaps you prefer to start from the mainstream. Trying to find the mainstream, so that customers can build derivatives from that, is what imec does. We’re getting closer to systems, and systems are reaching down to technology,” said Steegen. “We reach out to each other, while we continue to be experts in our own domains. If I’m inserting future memory into servers, the system architecture needs to change so we need to talk to the systems people. It’s a natural trend that has evolved.”

Network effects from “the cloud” and from future smart IoT nets require high-bandwidth and so improved electrical and optical connections at multiple levels are being explored at imec. Joris Van Campenhout, program director optical I/O, imec, discussed “Scaling the cloud using silicon photonics.” The challenge is how to build a 100Gb/s bandwidth in the near term, and then scale to 400G and then 1.6T though parallelism of wavelength division multiplexing; the best results to date for a transmitter and receiver reach 50Gb/s. By leveraging the existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon photonics platform enables high integration density and reduced power consumption, as well as high yield and low manufacturing cost. Supported by EDA tools including those from Mentor Graphics, there have been 7 tape-outs of devices in the last year using a Process Design Kit (PDK). When combined with laser sources and a 40nm node foundry CMOS chip, a complete integrated solution exists. Arrays of 50Gb/s structures can allow for 400Gb/s solutions by next year, and optical backplanes for server farms in another few years. However, to bring photonics closer to the chip in an optical interposer will require radical new new approaches to reduce costs, including integration of more efficient laser arrays.

Alexander Mityashin, project manager thin film electronics, imec, explained why we need, “thin film electronics for smart applications.” There are billions of items in our world that could be made smarter with electronics, provided we can use additive thin-film processes to make ultra-low-cost thin-film transistors (TFT) that fit different market demands. Using amorphous indium-gallium-zinc-oxide (a-IGZO) deposited at low-temperature as the active layer on a plastic substrate, imec has been able to produce >10k TFTs/cm2 using just 4-5 lithography masks. Figure 2 shows these TFT integrated into a near-field communications (NFC) chip as first disclosed at ISSCC earlier this year in the paper, “IGZO thin-film transistor based flexible NFC tags powered by commercial USB reader device at 13.56MHz.” Working with Panasonic in 2013, imec showed a flexible organic light-emitting diode (OLED) display of just 0.15mm thickness that can be processed at 180°C. In collaboration with the Holst Center, they have worked on disposable flexible sensors that can adhere to human skin.

Fig.2: Thin-Film Transistors (TFT) fabricated on plastic using Flat Panel Display (FPD) manufacturing tools. (Source: imec/Holst Center)

Jim O’Neill, Chief Technology Officer of Entegris, expanded on the systems-level theme of the forum in his presentation on “Putting the pieces together – Materials innovation in a disruptive environment.” With so many additional materials being integrated into new device structures, there are inherently new yield-limiting defect mechanisms that will have to be controlled. With demand for chips now being driven primarily by high-volume consumer applications, the time between first commercial sample and HVM has compressed such that greater coordination is needed between device, equipment, and materials companies. For example, instead of developing a wet chemical formulation on a tool and then optimizing it with the right filter or dispense technology, the Process Engineer can start envisioning a “bottle-to-nozzle wetted surface solution.” By considering not just the intended reactions on the wafer but the unintended reactions that can occur up-steam and down-stream of the process chamber, full solutions to the semiconductor industry’s most challenging yield problems can be more quickly found.


Monolithic 3D processing using non-equilibrium RTP

Friday, April 17th, 2015


By Ed Korczynski, Senior Technical Editor, Solid State Technology

Slightly more than one year after Qualcomm Technologies announced that it was assessing CEA-Leti’s monolithic 3D (M3D) transistor stacking technology, Qualcomm has now announced that M3D will be used instead of through-silicon vias (TSV) in the company’s next generation of cellphone handset chips. Since Qualcomm had also been a leading industrial proponent of TSV over the last few years while participating in the imec R&D consortium, this endorsement of M3D is particularly relevant.

Leti’s approach to 3D stacking of transistors starts with a conventionally built and locally-interconnected bottom layer of transistors, which are then covered with a top layer of transistors built using relatively low-temperature processes branded as “CoolCube.” Figure 1 shows a simplified cross-sectional schematic of a CoolCube stack of transistors and interconnects. CoolCube M3D does not transfer a layer of built devices as in the approach using TSV, but instead transfers just a nm-thin layer of homogenous semiconducting material for subsequent device processing.

Fig. 1: Simplified cross-sectional rendering of Monolithic 3D (M3D) transistor stacks, with critical process integration challenges indicated. (Source: CEA-Leti)

The reason that completed transistors are not transferred in the first place is because of intrinsic alignment issues, which are eliminated when transistors are instead fabricated on the same wafer. “We have lots of data to prove that alignment precision is as good as can be seen in 2D lithography, typically 3nm,” explained Maud Vinet, Leti’s advanced CMOS laboratory manager in an exclusive interview with SST.

As discussed in a blog post online at Semiconductor Manufacturing and Design ( last year by Leti researchers, the M3D approach consists of sequentially processing:

  • processing a bottom MOS transistor layer with local interconnects,
  • bonding a wafer substrate to the bottom transistor layer,
  • chemical-mechanical planarization (CMP) and SPE of the top layer,
  • processing the top device layer,
  • forming metal vias between the two device layers as interconnects, and
  • standard copper/low-k multi-level interconnect formation.

To transfer a layer of silicon for the top layer of transistors, a cleave-layer is needed within the bulk silicon or else time and money would be wasted in grinding away >95% of the silicon bulk from the backside. For CMOS:CMOS M3D thin silicon-on-insulator (SOI) is the transferred top layer, a logical extension of work done by Leti for decades. The heavy dose ion-implantation that creates the cleave-layer leaves defects in crystalline silicon which require excessively high temperatures to anneal away. Leti’s trick to overcome this thermal-budget issue is to use pre-amorphizing implants (PAI) to completely dis-order the silicon before transfer and then solid-phase epitaxy (SPE) post-transfer to grow device-grade single-crystal silicon at ~500°C.

Since neither aluminum nor copper interconnects can withstand this temperature range, the interconnects for the bottom layer of transistors need to be tungsten wires with the highest melting point of any metal but somewhat worse electrical resistance (R). Protection for the lower wires cannot use low-k dielectrics, but must use relatively higher capacitance (C) oxides. However, the increased RC delay in the lower interconnects is more than offset by the orders-of-magnitude reduction in interconnect lengths due to vertical stacking.

M3D Roadmaps

Leti shows data that M3D transistor stacking can provide immediate benefit to industry by combining two 28nm-node CMOS layers instead of trying to design and manufacture a single 14nm-node CMOS layer:  area gain 55%, performance gain 23%, and power gain 12%. With cost/transistor now expected to increase with sequential nodes, M3D thus provides a way to reduce cost and risk when developing new ICs.

For the industry to use M3D, there are some unique new unit-processes that will need to ramp into high-volume manufacturing (HVM) to ensure profitable line yield. As presented by C. Fenouillet-Beranger et al. from Leti and ST (paper 27.5) at IEDM2014 in San Francisco, “New Insights on Bottom Layer Thermal Stability and Laser Annealing Promises for High Performance 3D Monolithic Integration,” due to stability improvement in bottom transistors found through the use of doping nickel-silicide with a noble metal such as platinum, the top MOSFET processing temperature could be relaxed up to 500°C. Laser RTP annealing then allows for the activation of top MOSFETs junctions, which have been characterized morphologically and electrically as promising for high performance ICs.

Figure 2 shows the new unit-processes at <=500°C that need to be developed for top transistor formation:

*   Gate-oxide formation,

*   Dopant activation,

*   Epitaxy, and

*   Spacer deposition.

Fig. 2: Thermal processing ranges for process modules need to be below ~500°C for the top devices in M3D stacks to prevent degradation of the bottom layer. (Source: CEA-Leti)

After the above unit-processes have been integrated into high-yielding process modules for CMOS:CMOS stacking, heterogeneous integration of different types of devices are on the roadmap for M3D. Leti has already shown proof-of-concept for processes that integrate new IC functionalities into future M3D stacks:

1)       CMOS:CMOS,

2)       PMOS:NMOS,

3)       III-V:Ge, and

4)       MEMS/NEMS:CMOS.

Thomas Ernst, senior scientist, Electron Nanodevice Architectures, Leti, commented to SST, “Any application that will need a ‘pixelated’ device architecture would likely use M3D. In addition, this approach will work well for integrating new channel materials such as III-V’s and germanium, and any materials that can be deposited at relatively low temperatures such as the active layers in gas-sensors or resistive-memory cells.”

Non-Equilibrium Thermal Processing

Though the use of an oxide barrier between the active device layers provides significant thermal protection to the bottom layer of devices during top-layer fabrication, the thermal processes of the latter  cannot be run at equilibrium. “One way of controlling the thermal budget is to use what we sometimes call the crème brûlée approach to only heat the very top surface while keeping the inside cool,” explained Vinet. “Everyone knows that you want a nice crispy top surface with cool custard beneath.” Using a laser with a short wavelength prevents penetration into lower layers such that essentially all of the energy is absorbed in the surface layer in a manner that can be considered as adiabatic.

Applied Materials has been a supplier-partner with Leti in developing M3D, and the company provided responses from executive technologists to queries from SST about the general industry trend to controlling short pulses of light for thermal processing. “Laser non-equilibrium heating is enabling technology for 3D devices,” affirmed Steve Moffatt, chief technology officer, Front End Products, Applied Materials. “The idea is to heat the top layer and not the layers below. To achieve very shallow adiabatic heating the toolset needs to ramp up in less than 100 nsec. In order to get strong absorption in the top surface, shorter wavelengths are useful, less than 800 nm. Laser non-equilibrium heating in this regime can be a critical process for building monolithic 3D structures for SOC and logic devices.”

Of course, with ultra-shallow junctions (USJ) and atomic-scale gate-stacks already in use for CMOS transistors at the 22nm-node, non-equilibrium thermal processing has already been used in leading fabs. “Gate dielectric, gate metal, and contact treatments are areas where we have seen non-equilibrium anneals slowly taking the place of conventional RTP,” clarified Abhilash Mayur, senior director, Front End Products, Applied Materials. “For approximate percentages, I would say about 25 percent of thermal processing for logic at the 22nm-node is non-equilibrium, and seen to be heading toward 50 percent at the 10nm-node or lower.”

Mayur further explained some of the trade-offs in working on the leading-edge of thermal processing for demanding HVM customers. Pulse-times are in the tens of nsec, with longer pulses tending to allow the heat to diffuse deeper and adversely alter the lower layers, and with shorter pulses tending to induce surface damage or ablation. “Our roadmap is to ensure flexibility in the pulse shape to tailor the heat flow to the specific application,” said Mayur.

Now that Qualcomm has endorsed CoolCube M3D as a preferred approach to CMOS:CMOS transistor stacking in the near-term, we may assume that R&D in novel unit-processes has mostly concluded. Presumably there are pilot lots of wafers now being run through commercial foundries to fine-tune M3D integration. With a roadmap for long-term heterogeneous integration that seems both low-cost and low-risk, M3D using non-equilibrium RTP will likely be an important way to integrate new functionalities into future ICs.

Germanium Junctions for CMOS

Tuesday, November 25th, 2014


By Ed Korczynski, Sr. Technical Editor, Solid State Technology and SemiMD

It is nearly certain that alternate channel materials with higher mobilities will be needed to replace silicon (Si) in future CMOS ICs. The best PMOS channels are made with germanium (Ge), while there are many possible elements and compounds in R&D competition to form the NMOS channel, in part because of difficulties in forming stable n-junctions in Ge. If the industry can do NMOS with Ge then the integration with Ge PMOS would be much simpler than having to try to integrate a compound semiconductor such as gallium-arsenide or indium-phosphide.

In considering Ge channels in future devices, we must anticipate that they will be part of finFET structures. Both bulk-silicon and silicon-on-insulator (SOI) wafers will be used to build 3D finFET device structures for future CMOS ICs. Ultra-Shallow Junctions (USJ) will be needed to make contacts to channels that are nanoscale.

John Borland is a renowned expert in junction-formation technology, and now a principle with Advanced Integrated Photonics. In a Junction Formation side-conference at SEMICON West 2014, Borland presented a summary of data that had first been shown by co-author Paul Konkola at the 2014 International Conference on Ion Implant Technology. Their work on “Implant Dopant Activation Comparison Between Silicon and Germanium” provides valuable insights into the intrinsic differences between the two semiconducting materials.

P-type implants into Ge showed an interesting self-activation (seen as a decrease in of p-type dopant after implant, especially for monomer B as the dose increases.  Using 4-Point-Probe (4PP) to measure sheet-resistance (Rs), the 5E14/cm2 B-implant Rs was 190Ω/□ and at higher implant dose of 5E15/cm2 Rs was 120Ω/□. B requires temperatures >600°C for full activation in PMOS Ge channels, and generally results in minimal dopant diffusion for USJ.

Figure 1 shows a comparison between P, As, and Sb implanted dopants at 1E16/cm2 into both a Si wafer and 1µm Ge-epilayer on Si after various anneals. The sheet-resistance values for all three n-type dopants were always lower in Ge than in Si over the 625-900°C RTA range by about 5x for P and 10x for As and Sb. Another experiment to study the results for co-implants of P+Sb, P+C, and P+F using a Si-cap layer did not show any enhanced n-type dopant activation.

Fig.1: Sheet-resistance (Rs) versus RTA temperatures for P, As, and Sb implanted dopants into Ge and Si. (Source: Borland)

Prof. Saraswat of Stanford University showed in 2005—at the spring Materials Research Society meeting— that n-type activation in Ge is inherently difficult. In that same year, Borland was the lead author of an article in Solid State Technology (July 2005, p.45) entited, “Meeting challenges for engineering the gate stack”, in which the authors advocated for using a Si-cap for P implant to enable high temperature n-type dopant activation with minimal diffusion for shallow n+ Ge junctions that can be used for Ge nMOS. Now, almost 10 year later, Borland is able to show that it can be done.

Ge Channel Integration and Metrology

Nano-scale Ge channels wrapped around 3D fin structures will be difficult to form before they can be implanted. However, whether formed in a Replacement Metal Gate (RMG) or epitaxial-etchback process, one commonality is that Ge channels will need abrupt junctions to fit into shrunk device structures. Also, as device structures have continued to shrink, the junction formation challenges between “planar” devices and 3D finFET have converged since the “2D” structures now have nano-scale 3D topography.

Adam Brand, senior director of transistor technology in the Advanced Product Technology Development group of Applied Materials, explained that, “Heated beamline implants are best when the priority is precise dose and energy control without lattice damage. Plasma doping (PLAD) is best when the priority is to deliver a high dose and conformal implant.”

Ehud Tzuri, director strategic marketing in the Process Diagnostic and Metrology group at Applied Materials reminds us that control of the Ge material quality, as specified by data on the count and lengths of stacking-faults and other crystalline dislocations, could be done by X-Ray Diffraction (XRD) or by some new disruptive technology. Cross-section Transmission Electron Microscopy (X-TEM) is the definitive technology for looking at nanoscale material quality, but since it is expensive and the sample must be destroyed it cannot be used for process control.

Figure 2 shows X-TEM results for 1 µm thick Ge epi-layers after 625°C and 900°C RTA. Due to the intrinsic lattice mis-match between Ge and Si there will always be some defects at the surface, as indicated by arrows in the figure. However, stacking faults are clearly seen in the lower RTA sample, while the 900°C anneal shows no stacking-faults and so should result in superior integrated device performance.

Fig. 2: Cross-section TEM of 1µm Ge-epi after 625°C and 900°C RTA, showing great reduction in stacking-faults with the higher annealing temperature. (Source: Borland)

Borland explains that the stacking-faults in Ge channels on finFETs would protrude to the surface, and so could not be mitigated by the use of the “Aspect-Ratio Trapping” (ART) integration trick that has been investigated by imec. However, the use of a silicon-oxide cap allows for the use of 900°C RTA which is hot enough to anneal out the defects in the crystal.

Brand provides an example of why integration challenges of Ge channels include subtle considerations, “The most important consideration for USJ in the FinFET era is to scale down the channel body width to improve electrostatics. Germanium has a higher semiconductor dielectric constant than silicon so a slightly lower body width will be needed to reach the same gate length due to the capacitive coupling.”

Junction formation in Ge channels will be one of the nanoscale materials engineering challenges for future CMOS finFETs. Either XRD or some other metrology technology will be needed for control. Integration will include the need to control the materials on the top and the bottom surfaces of channels to ensure that dopant atoms activate without diffusing away. The remaining challenge is to develop the shortest RTA process possible to minimize all diffusions.

— E. K.