By Ann Steffora Mutschler
As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable.

But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to solve it. You’re on autopilot until you hit a disruption, and 3D represents a disruption.”

Whether it is memory stacked on logic, which is most common today, or stacking multiple logic die on top of each other vertically with through silicon vias (TSVs), both approaches are complicated and require more infrastructure than traditional SoCs.

Yervant Zorian, a Synopsys fellow and chief architect, noted that we have always dealt with multiple chips—but the multiple chips that we dealt with previously were packaged chips. “Having packaged chips on a board allowed us to test the chips fully upon packaging when they are on the wafer. And also, after being packaged to give the full quality chip, proven and warrantied to the board-level team to assemble it on the board. Now that’s all good when a die is packaged—a package protects it from further defectively. However, with 3D stacks or 2.5D interposers or some other advanced packaging technologies we are dealing with there is bare die that is unpackaged so the whole issue starts with that.”

So even though the bare die are fully tested, they are prone to defectively during assembly, mounting, transportation. “Whatever you do between the production of that die up through the time it is assembled with the rest of the dies there is this defectivity magnet situation where certain things happen to it and therefore we need to retest it after it’s been assembled—whether it is two dies, four dies, at every stage you need to test it again to make sure that nothing is damaged,” he added.

Clearly, the test challenges with stacked die include the need to test things at multiple points during fabrication and assembly, Petrakis said. “Then there is a big question about how much testing is required. With test there is cost and what do you forgo and what do you actually test.”

There are two schools of thought here, he noted. One is to use the normal manufacturing test type of approaches such as implanting test circuitry as is normally done and testing each die separately. “You make sure that you apply all the tests and then you know you probably have good die to work with. ‘Probably’ is a good term because you never know.”

Then, if the design will use through-silicon vias, what is the best approach to test and how do you get access to the test interface? “On a normal chip you just go to the pads and you say, ‘These are the test pads,’ and you target those. On a TSV-based design there is a lot of talk about landing probes, but the dimensions are so small that there is fear that they are going to be damaged,” he added.

It’s not all doom and gloom with stacked die, though. “The fun comes in when you start stacking logic die,” asserted Stephen Pateras, product marketing director for Mentor Graphics’ Silicon Test Solutions group. “In the case where you had a single logic die you had full access to it. If there were any test pins and memories that needed to be accessed directly even though they are stacked, you’re going through the BiST, the JEDEC standard interface, so you don’t have to worry about accessing the DRAMs directly. But with stacked logic die, now presumably you want to test pieces of a logic die. You want to test the interconnect between them, so you need access each of those logic die independently somehow. Generally you don’t have access to them, because if they are stacked vertically the idea is that the bottom die will be the one that is connected to the package and the other die are connected to each other. So there may be neighbors top or bottom in that stack. That’s where we need to have a way of going through the stack to get access to those die for test so you need some kind of test access architecture that makes use of the TSVs.”

At the foundation of such a test access architecture is the proposed IEEE P1838 standard, which gives just such access.

Zorian explained that IEEE P1838 complements the work that was done previously with JTAG 1149.1 and IEEE 1500, whereby JTAG was for the chips on the board and 1500 was for the cores in the SoC. “P1838 is for the dies in a 3D structure to talk to those dies. You need an access port and this access port cannot be JTAG. It cannot be 1500, but it can be something between the two and very complementary to those working hand-in-hand coherently with the first two standards to handle the new multi-dies in a package. P1838 will allow us to know exactly what that test bus is. The seven-bit communication bus proposed today will communicate the test related functions between one die to the other, from that die to the next and so on.”

By the time 3-D becomes prominent it is expected that P1838 will be ratified as an IEEE standard.

Further, Cadence’s Petrakis noted that the idea behind p1838 is isolation. “How do we isolate one die from the others such that we can test it internally without disturbing anything else? Then it’s not quite really disturbing it. It’s really a matter of true isolation. You do not want any foreign signals or unknown traditions to affect the testing that you are doing. The isolation is that we put the chip in a mode where it only sees data coming in and out from itself. In other words, the application of test reading the results back is not influenced by anything else.”

The looming cost concern
Amidst the technical challenges of 3D and 2.5D stacked die is the discussion surrounding who will pay for all of this extra testing.

Synopsys’ Zorian said, “The two stops in test that we used to have, which is testing the chip at the wafer level and testing the chip post-package, will still be there. But now we introduce intermediate steps so suddenly we need to do more test in between. When I have two dies together, three dies together—these are the prevalent situations where we need to test them. And there is a cost associated with it because it is after the die has been produced, so you cannot cost-wise expect the die producer that is the chip manufacturer to do that. It is a packaging-oriented cost because it happens later on during the stages of pulling those dies together. It depends who will be doing it and therefore who will pay for it.”

At this point, it seems that the cost will not fall to the die producer, but it depends on how the business model develops—especially because several chip manufacturers and foundries have expressed interest in being part of this ecosystem. “Whether it is TSMC, GlobalFoundries or otherwise, if they are doing it then of course it will be the last stage, because it’s not the wafer manufacturing stage or the wafer testing stage. It is one stage after that.”

However the situation turns out, the rising wave of 3D manufacturing and test is causing ripples throughout the entire ecosystem.

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. This paper focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based.

To view this white paper, click here.

By Mark LaPedus
Qualcomm has the highest market share for baseband solutions in handsets, resulting in a position far out in front of its competitors. ST-Ericsson has strong products on the market with competitive features. But one analyst at ABI Research questions why ST-Ericsson was broken up just as it finally came out with a highly competitive product, which was based on FD-SOI.

The worldwide semiconductor foundry market totaled $34.6 billion in 2012, a 16.2% increase from 2011, according to final results by Gartner. TSMC maintained the No. 1 spot in the rankings in 2012. Strong performance on 32nm yields and the availability of sub-45nm wafer capacity at the Dresden, Germany, fabs allowed GlobalFoundries to advance to the No. 2 position in 2012. UMC‘s market share decreased due to reduced wafer shipments. Driven by the wafers consumed by Apple, Samsung moved up four spots to the No. 5 position with 175.5% growth in 2012.

At this year’s Symposium on VLSI Technology, Intel will report technical details of its embedded DRAM with 22nm technology on bulk silicon wafers. Intel realized a 0.029mm2 DRAM cell capable of meeting >100us retention at 95 C. In the DC-DC converter session, Intel will present a switched capacitor step-down converter designed in a 22nm tri-gate CMOS technology. The VLSI Symposium is slated for June 11–14 in Kyoto, Japan.

At the VLSI event, STMicroelectronics and CEA-LETI will report six transistor SRAM (6T-SRAM) cells for high-density and low-voltage. The technology is fabricated at the 28nm node using FD-SOI technology for the first time.

At the VLSI Symposium, IBM and GlobalFoundries will report a SiGe channel tri-gate pFET with aggressively scaled fin width and gate length dimensions. It is fabricated using SiGe on an insulator substrate. Excellent electrostatic control down to Lg= 18nm and Wfin<18nm has been reported.

At the event, IMEC and GlobalFoundries will present the first demonstration of strained germanium channel pFETs fabricated on SiGe strain relaxed buffers, which is surrounded by STI region. Also, they introduced raised SiGe source/drain structures (Ge concentration= 75%) with an implant-free quantum well, replacement metal-gate process and germanide in contacts to solve void issues.

In addition, STMicrolectronics, Samsung, GlobalFoundries and IBM will report a 64nm pitch BEOL integration and material strategy. A self-aligned-via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask.

SEMI reported that for the quarter ending Dec. 31, 2012, the worldwide photovoltaic manufacturing equipment book-to-bill ratio remained well below parity, at 0.45, for the seventh consecutive quarter. Booking levels continue to be low as PV manufacturers grapple with oversupply across the supply chain.

Khaled Juffali Company (KJC), a Saudi Arabian investment company, and Soitec, signed a memorandum of understanding (MOU) to cooperate in driving solar industry growth in Saudi Arabia and the Middle East. Under the MOU, the two companies will create a joint venture to market and sell concentrator photovoltaic (CPV) systems in the Kingdom of Saudi Arabia.

Hwa Chong Institution emerged as the winner of the Applied Materials Clean Tech Competition in Singapore. The project focused on utilizing calcium carbonate found in clam shells to remove toxic metal ions from waste water.

The separate hardware and software teams in companies are notorious for not being on the same page, thereby putting product development times and cost at risk. Mentor Graphics CEO Walden Rhines outlined some new and practical solutions to the problem.

Mentor Graphics announced the release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon. The tool provides a tighter connection between hardware and software co-development, but allows software developers to use existing programming tools with extensions.

Cadence announced results for the first quarter of fiscal year 2013. Cadence also completed its previously announced acquisition of Tensilica.

Advantest will acquire W2BI, a provider of system level test automation software focusing on wireless communications.

Shipments of smart glasses may rise to as high 6.6 million units in 2016, up from just 50,000 in 2012, for a total of 9.4 million units for the five-year period, according to an upside forecast from IMS Research.

The worldwide mobile phone market grew 4% year over year in the seasonally slow first quarter of 2013 as smart phones out-shipped feature phones for the first time, according to IDC. Nokia, BlackBerry and HTC have dropped out of the top rankings.

By Mark LaPedus
The term carbon footprint seems to be “old hat” and yesterday’s measure of sustainability. “Sustainable development” is the new term. But what is it and can someone please define it? The recent European Coatings Show provided a clue, according to Lux.

For years, smart watches have failed to take off for one reason or another: they looked ugly, had weak functionality, or the battery life was lousy, according to ABI Research. However, a new collection of smart watches have emerged that could change consumers’ perceptions. Market intelligence firm ABI Research projects more than 1.2 million smart watches will be shipped in 2013.

Intel announced its results and cut its CapEx by $1 billion from $13 billion to $12 billion. Hans Mosesmann, an analyst with Raymond James, made the following observations: “With smartphones/tablets not contributing much for Intel in 2013 and the foundry growth vector still 2-3 years from being a real business, Intel is, in our view, quite vulnerable. The hope is for a datacenter recovery as an offset in 2H13 – we’ll see. Interestingly, Intel indicated in relation to its foundry strategy that it would not enable competitors that license ARM processor technology. Outside of programmable logic devices (PLDs), isn’t everybody of significance already using ARM?”

For total fab spending, GlobalFoundries plans to spend $4.4 billion this year to expand production as demand for smartphones and tablets jumps, according to Bloomberg. The spending compares with $3.8 billion last year.

TSMC raised its capital spending. Spending will be $9.5 billion to $10 billion, compared to an earlier forecast of $9 billion, according to Bloomberg. TSMC is accelerating its 20nm and finFET production.

In a blog, Applied Materials said it has recently completed the electrical characterization of through-silicon via (TSV) structures. This development is important because TSVs are the vertical interconnections that carry power and high-bandwidth speed signals between the stacked die of layered logic and memory devices.

Recently, more than 270 students from National Tsing Hua University in Hsinchu, Taiwan, crowded into the campus auditorium to hear Mike Splinter, chairman and CEO, of Applied Materials, to deliver a talk. The Applied Materials CEO told students to follow their passion.

Soitec’s solar unit has completed a debt financing plan for its Touwsrivier project in South Africa.

Soitec announced consolidated sales of 72.7 million euros for the fourth quarter, down 9.3% on a yearly basis. On a sequential basis, Q4 electronic sales were up by 19.1%.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 1.14 in March, up from 1.10 from April, according to SEMI. id=highlights

Mentor Graphics announced the opening of a new Mentor-sponsored electronics design laboratory at The University of Nottingham Ningbo China (UNNC), based in the Zhejiang province. Mentor has donated more than $10 million in EDA software and support to enable UNNC students to graduate with in-depth knowledge of leading-edge design methodologies.

ASML announced its results and said the contract of Eric Meurice, president and CEO, ends next year. As of July 1, ASML’s leadership will be comprised as follows: Peter Wennink, ASML’s CFO, will be president and CEO; Martin van den Brink, ASML’s executive vice president, will be president and chief technology officer. Meurice will be chairman of ASML and act as adviser to the new leadership and the supervisory board until the end of his contract on March 31, 2014.

Intermolecular has entered into a multi-year technology development and IP licensing agreement with Micron Technology, focused on technology development and related IP for advanced memory technologies. Intermolecular has been working on DRAM technology with Elpida, which is being acquired by Micron. Now, with Micron, Intermolecular is expanding into the nonvolatile memory front with the memory maker, said Dave Lazovsky, president and CEO of Intermolecular. “New materials and device architectures are increasingly needed to meet future embedded and mobile technology requirements, and partnering with Micron in this area is a significant milestone for Intermolecular,” he said.

Tessera has named Richard Hill as interim chief executive and executive chairman of the board. Hill replaces former president and CEO Robert Young, who has decided to step down amid pressure from an investment firm.

Altera has agreed to acquire TPACK, a subsidiary of Applied Micro Circuits Corp. TPACK delivers FPGA-based optical transport network products targeting packet and optical networking equipment suppliers.

”According to Dow Jones VentureWire and other news reports, Avago has reached a deal to acquire Javelin Semiconductor, a manufacturer of CMOS power amplifiers (PAs) which services the mobile market,” said Doug Freedman, an analyst with RBC Capital Markets.

Netronome has raised $19 million in series E and related financing from Sourcefire, Intel Capital and existing investors DFJ Esprit and the Raptor Group. The company is making a next-generation flow processor line, the NFP-6xxx, which is built using Intel’s 22nm tri-gate technology.

Smartphones are forecast to account for 26% of the $30.0 billion NAND flash memory market in 2013. The NAND flash market is forecast to grow 12% in 2013, from $26.8 billion in 2012, according to IC Insights.

The trend to reduce critical features dimension has dramatically increased design file size. Design tape–out flows at the 28 nm technology node handle post-OPC data files that reach hundreds of gigabytes. This trend increases at 20 nm and below. That predicts new challenges in mask data preparation flow for advanced technology nodes. We have developed a mask data preparation flow to tackle the challenge of maintaining a consistent delivery time to mask shops, while efficiently using exiting hardware. Taming data file size required innovations in data processing for fractured data files creation and also in data review techniques. The paper will discuss these innovations and conduct a demonstration with results in a 28 nm technology node production flow. Cost-benefit analysis will be illustrated with runtime comparisons of fractured data creation, and data review between traditional mask data preparation flows and this specific flow.

To view this white paper, click here.

By Ann Steffora Mutschler

With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations.

Certainly, double patterning was the biggest change and the biggest concern on the designer’s minds when they began moving to 20nm, observed David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics. They wanted to know what double patterning was and how to deal with it.

“Also, for the foundries themselves, they wanted to know how were they going to find provide a solution that was viable to the users,” Abercrombie said. “That’s certainly been the bulk of the questions we’ve gotten with the move to 20 nm and below—things related to double patterning, finding and fixing errors, how to deal with parasitic extraction or LVS or whatever, place and route and other things associated with double patterning. It’s certainly a new and different kind of error to deal with.”

The nature of the difference

Most design rule checks typically are associated with either a single polygon or its neighbor. That includes width or spacing or area, which can be complex. For instance, the space is dependent on the width, the run length, etc., but it’s still basically a neighbor-to-neighbor interaction or the layout of the shape itself.

“With odd cycles and anchor path errors, it’s now an issue of the network of interacting shapes—multiple shapes that can be spread over long distances and how they interact with each other in the network of spacings to form this odd cycle or this anchor path,” said Abercrombie. “It’s very different than the traditional rule in that sense. In some ways people have learned to think about it more like an antenna rule that is network-based. It’s not conductivity-based, it’s spacing-based, but it’s about the network of shapes and the spacings.”

This is a whole new level of complexity for designers to deal with. “If you’ve seen 20nm designs from customers, they’re different from 28nm and the reason for that is because of the core fundamental issue in double patterning of conflicts, where one defines a conflict as a native conflict or a loop conflict,” said Manoj Chacko, product marketing director at Cadence noted. “A native conflict is something that you can detect but cannot fix without a design change. That means the designer has to make a design change.”

Consider a loop conflict, for example. If you have four polygons, for example, and two masks for double patterning at 20nm, then each polygon is split into two masks and four polygons is split into eight. That works fine in a very regular layout, but not all layouts are so regular.

“This seems kind of reasonable given that you can assign four polygons eight colors, but in reality it’s a little different because it depends on the proximity of the polygons to the others and so on,” Chacko said. “If you had nine polygons because of an L joint, for example, even if you have to split four into eight but the eighth polygon is not straight, it’s an L—now the L basically may become two colors again, making nine. This is called a loop problem, where you have the eighth polygon that is split into 2 colors. This is the problem that designers see. It doesn’t require systematic changes but it does require identification of the loop, and then there are methods to fix it.”

One other problem is when you think of that last ninth polygon as an L, where at the corner of the L where the two lines join. That could make a split. The foundries decide on the split based on their process. They may not do a split at a joint. They may do it on a straighter edge. But when they make the joint, there is an overlay of these two masks. If you think of that ninth polygon – that eighth polygon that got split into two pieces—they will expose first one joint, then etch it, then expose the remaining portion of that L, then etch it. Now you have to make sure these two exposures make that one L that the customer wants. The idea is that the overlay is a problem. In manufacturing, it’s called overlay. In design, it’s called stitching—meaning they have to make sure there’s enough overlap at the split/splice location. So that is another issue that design tools have to give good feedback about.

These coloring issues are exactly why Mentor Graphics looks at this differently, Abercrombie said. “Displaying the error as a ring is so much more productive than showing the colors because this was the initial mental struggle [with double patterning,] and the request that came up most was, ‘I want to see the colors.’ That was the first thing designers said—only the colors. And I said, ‘Why do you want to see the colors?’ ‘So I know what to fix.’ Seeing the colors is actually a misleading thing. If you imagine an odd cycle there is no legal way to color it. That’s the problem. That’s why it’s an error. There is an odd number of things interacting, and you have two colors and you can’t divide and odd number by an even number or you get a remainder. So you can’t color them alternating colors in an odd cycle, because somewhere in that cycle you’re going to end up with the same two colors next to each other. When you ask the tool to show you colors, inherently the tool can only show you the wrong colors because in that configuration there are no legal colors.”

A second problem is that there are many, many different wrong colorings that could be shown because there is no right one, so the selection of which one to show is completely arbitrary.

This is why Mentor approaches this type of error with a ring scenario. “By showing colors, there could be a random chance that I showed you that one error that may be the hardest one to fix and hence I’ve pushed you down a path of most work,” Abercrombie said. “By ignoring the colors—not showing the colors, if at all possible because it’s just going to mentally push you in a direction—look at the ring and look at the options that it is showing you as a benefit. Now you have multiple choices and you can do what is best for you.”

Not so scary

Mentor’s Abercrombie asserted that as scary as it is for designers to learn something new, “like anything else once they start dealing with it they learned pretty quick and they found it’s not those it’s not as overwhelming as they thought.”

And there are even some nice things about double patterning errors, he said, in that although the error can seem large and involve a lot of shapes with a lot of spaces around things, the advantage of it is that you have multiple options for fixing it. In a given odd cycle, for example, you only have to break one separation within the network of polygons that are interacting and it is clean. You don’t have to fix them all. You only have to fix one of them.

“In that way a single error has many ways to fix it and that’s better than a lot of other DRC rules,” he said. “When the check is like ‘me and my neighbor’ and how far away we are—when you only have one option you’ve got to fix that space and that may be difficult because of the ramifications of trying to fix it. When you try to move those edges, or you might have to move vias and other shapes, that could be a very complicated location to fix. But with a DP error, the fact that it’s got multiple options gives some freedom to say, ‘Here’s an odd cycle with five different spaces and there are actually five choices that I can make.’ I can look at which one is easiest for me.”

Saleem Haider, senior director of marketing for physical design and DFM at Synopsys, agreed. “[DP errors], at the highest level, look pretty much the same as a general design rule error. Even without double patterning at 28nm we have a fairly complex set of design rules that the foundries gives us and design implementation has to adhere to those. Ten years ago, pretty much all design rules were somewhat width- and spacing-oriented. Now the rules are very, very complex. Some of them are based on the size of the object itself, and there are spacings from corners and edges and sides, etc., so it’s a fairly complex set of rules.”

Double patterning becomes a part of that, so at the end of the day, a DP violation or a DP error is going to, generically speaking, look just like a design rule error, he said. Just as if there was a design rule error in the design, the foundry would not accept that design because when the design comes into the foundry, one of the first things they do is run design rule checking on it to see if it meets the checking criteria that they specified. If the design doesn’t meet it, they will send that design back to the design team. It’s part of the incoming process. It’s the same for DP.

Like many new technologies, understanding double-patterning errors is just a learning process, Mentor’s Abercrombie concluded. “The foundries first had to figure out what it is they want to provide and support and work with us to make the tool capabilities to do that. Now that they’ve rolled out the decks to the customers it’s been more about educating the customer to overcome that initial shock of something new and get them educated. As soon as they play with it for a little while, it comes pretty fast. They’re smart. For the ones that have already made that move, they are settling in pretty quickly.”

Additional resources:

http://www.mentor.com/solutions/foundry

http://semimd.com/mentor/

http://www.synopsys.com/Tools/Implementation/CapsuleModule/ic_validator_wp.pdf

http://www.synopsys.com/Solutions/EndSolutions/20nmdesign/Documents/20nm-and-beyond-white-paper.pdf

By Mark LaPedus
The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs.

DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from the lab to the fab.

Perhaps the most glaring gap involves the ability to design chips around DSA. The existing EDA tools are not optimized for DSA, leaving many skeptics to ask a simple question: Can chipmakers design real and useful chips around DSA? Today, the answer is no or maybe someday.

Still, the lack of a design methodology opens up the door for new innovation and the emergence of a new field—design-for-DSA (DFD). In fact, there are some early methodologies surfacing for DFD. One idea is to tweak the current EDA tools for DSA. Another concept is to use 1D layouts. In another approach, Stanford University is developing a methodology using an alphabet soup of characters.

And not to be outdone, Cadence is working with GlobalFoundries to devise yet another approach. The technology, called Squish, uses an underlying classification engine and topological patterns as a means to enable IC designs using DSA, said Luigi Capodieci, director of DFM/CAD and an R&D fellow at GlobalFoundries.

“We have developed the first implementation of DSA modeling,” Capodieci said. “It’s a different way to look at physical design. The introduction of Squish topological patterns is a new way to look at how polygons and shapes come together. We can also enumerate how the patterns come together in a way we can match them.”

To make DSA viable, Capodieci also said that the EDA industry must look at the problem differently and develop an entirely new design methodology. “We need innovation,” he said. “We need a fundamental methodological change in how we put together the physical design.”

Assembling a design
DSA is not a next-generation lithography (NGL) tool per se. It’s more of a complementary and double-patterning scheme. There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

Over the last year, Albany Nanotech, CEA-Leti, IBM and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations and have shown their initial test structures using DSA.

It’s one thing to show intricate patterns and test structures, but it’s an entirely different matter to design chips around the technology. “It’s not good enough to have SEM pictures and show them at a conference,” said Lars Liebmann, a distinguished engineer for design technology co-optimization at IBM. “I can’t do anything with that. To really get your foot into the door you have to demonstrate some circuit-relevant patterns. If you show me a SEM, also show me a circuit pattern where a designer would say: ‘I can do something with that.’”

To satisfy the design community, DSA must meet some basic criteria. “You have to be able to integrate this patterning approach into a real CMOS flow. You have to demonstrate etch selectivity. And any new patterning technique should come with a set of compact models,” Leibmann said.

And, of course, there must be a robust design methodology and EDA tools. “The tools are not ready for DSA,” said Juan Rey, senior director of engineering at Mentor Graphics. “Essentially, the DSA community has developed a credible path for some layers. However, there is quite a bit of extensive research needed for full-chip-level development.”

All told, DSA still remains in the early stages of development and not ready for prime time. “We’ve seen some outstanding first steps in DSA,” Rey said. “But it’s pretty clear that more progress is required. The technology is still immature.”

Wanted: DFD
For some, the design-for-DSA debate centers around one question. “The question is not whether the EDA tools ready,” said GlobalFoundries’ Capodieci. “The question is what are the EDA tools required for DSA?”

One of the prevailing ideas is to use a complementary lithography approach as outlined by Intel. First, poly and metal lines are arranged into 1D gridded arrays. Then, a cut step is done to form a specified pattern. All told, DSA could enable lines and spaces, contact hole shrinks and even patterning a sea of fins.

Using a variant of complementary lithography, IBM has demonstrated the ability to pattern 29nm-pitch fins, which are etched onto a silicon-on-insulator (SOI) substrate. For DSA in general, IBM is using its own, in-house tools as well as conventional technology, said Kafai Lai, a senior scientist/engineer at IBM. “Our computational infrastructure basically builds upon conventional computational lithography platform. Many existing technical elements such as mask decomposition and coloring algorithms, model-based sub-resolution assist features (SRAF) and printable assist features (PRAF), source mask optimization (SMO), DSA optical proximity correction (DSA OPC), OPC verification, are still the building blocks of the DSA infrastructure. The optimum flow for DSA implementation depends on the feature types or the process layers of concern,” Lai said in a recent paper at SPIE.

“We have developed a set of computational lithography tools to enable us to evaluate the application of DSA to full-chip patterning. These toolsets involve new DSA-specific components such as DSA mask decomposition for guiding patterns, DSA-specific OPC or mask optimization and DSA-OPC verification. A fast DSA compact model is the backbone of these new CL components and we have reported such a fast DSA model for vias. A similar compact model for DSA L/S is under development now,” he added.

In any case, 1D layouts may enable DSA-friendly designs, but chipmakers must adhere to some rigid and restrictive design rules. “The designers will say I’m in left field, but I really think we need to spend more time working on the grid approach,” said Christopher Bencher, member of the technical staff at Applied Materials.

Using the 1D layout approach, memory makers could be the early adopters for DSA. For logic, Bencher and others have proposed a scheme that enables a sea of fins for use in future finFET designs. “For example, in the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which holes you want to keep and which ones you want to get rid of,” he said.

The downside to this approach is the inability to obtain a good aerial image of the holes. Still, Bencher said the 1D layout approach has several advantages over the rival alphabet-soup method. In this approach, a designer has the ability to choose a collection of shapes to develop a design. “As you try and stuff more and more (shapes on a pattern), the amount of positional error starts to go up,” he added.

The 1D gridded array approach also has some challenges. “You have to demonstrate some form of self-aligned trimming,” said IBM’s Leibmann. “Otherwise, in tight pitch gratings, it’s not useful at all because you can’t customize it. There is also no tool with the overlay capability to actually map that selectively without either damaging the fins you want to keep or residuals from the fins you want to erase.”

For this and other reasons, it’s unclear if the foundry industry can deploy this methodology. “Gridded with ultra-regular designs won’t work for us,” said Richard Farrell, a principal engineer at GlobalFoundries. “The biggest problem is that we incur a 3% to 5% area penalty for a gridded design, which is something we can’t give up.”

In the 1D layout approach, the IC industry would still require a new class of tools from the established EDA companies or startups willing to take a gamble. “This is possible, but you have to have a dedicated group of people with some capital who are willing to think differently,” said GlobalFoundries’ Capodieci. “But if we just wait for the commercial opportunity to present itself, we will miss the boat.”

Working with Cadence, GlobalFoundries proposes Squish, a design-for-DSA methodology that appears to combine the alphabet-soup approach and today’s pattern matching/classification technology. “This is like doing a Google search,” Capodieci said. “We actually create artificial structures in which patterns can come together.”

For example, the Squish methodology can create 1,716 or so different configurations or representations for a proposed IC layout. “We have the tools we need for classifying geometric and physical designs,” he said. “In literally a few hours, we can analyze a full-chip layout.”

Once this or another methodology is proven viable, the next step is to actually design and make a chip using DSA. “The next challenge for the industry is to process a couple of layers of a processor core using DSA,” he said. “We need a call for action.”

By Mark LaPedus
New research reveals that 53% of office workers with computers are opting to either fix their own computer problems, or ask a co-worker or someone else for help, instead of relying on an IT professional/helpdesk. The nationwide survey, conducted online by Harris Interactive on behalf of Crucial.com, also revealed that 29% of office computer users cite computer problems (lost files, slowness, crashes, etc.) as the top reason for reduced productivity in the office. Office computer problems trumped co-workers (25%), workload (22%), management (22%) and customers/clients/vendors (15%) when it comes to negatively affecting worker productivity in the office.

Big banks may be considered too big to fail, but their size and operational complexity create performance drags that could also make them too big to succeed, according to Gartner. Bank CIOs and COOs must innovate in IT and operations to negate a problem Gartner has identified as the “law of diminishing IT returns.”

Intel announced its annual equipment and materials supplier awards. The awards provide an insight regarding the fab suppliers at Intel, which normally declines to comment about the identity of its vendors. The winners are interesting, but it’s even more interesting to see which vendors failed to make the list. Meanwhile, Intel announced the eight winners of the company’s most prestigious award for equipment and materials suppliers, the Supplier Continuous Quality Improvement (SCQI) award. In addition, Intel announced that 17 equipment and materials companies will receive the 2012 Intel Preferred Quality Supplier (PQS) award.

DARPA has achieved world record power output levels using silicon-based technologies for millimeter-wave power amplifiers. The power amp was based on a multiple-stacked, 45nm silicon-on-insulator (SOI) CMOS device.

Electronic components distributor Digi-Key announced the signing of a global distribution agreement with Adesto Technologies, a developer of nonvolatile memory chips. One of Adesto’s investors is Applied Ventures, the venture capital arm of Applied Materials.

The global semiconductor materials market decreased 2% in 2012 compared to 2011, while worldwide semiconductor revenues declined 3%, according to SEMI.

For the Southeast Asia region, SEMI expects to see capital equipment investment to bottom out in the first half of 2013 and a mild pickup in the second half followed by a strong recovery in 2014. Overall front-end fab equipment spending is expected to double next year from $810 million in 2013 to $1.62 billion in 2014, according to SEMI.

Mentor Graphics announced various hardware and software solutions to accelerate the verification of Serial Attached SCSI (SAS) second-generation (Gen 2) products. Using the Mentor verification solutions, designers can test their SAS Gen2 devices integrated on their SoC designs, and develop and test their software drivers and applications prior to silicon being available.

Entegris, a supplier of contamination control and materials handling solutions, has acquired the assets of Jetalon Solutions, a California-based supplier of fluid metrology products.

Avago announced the execution of a definitive agreement to acquire CyOptics, a supplier of indium phosphide (InP) optical chip and component technologies for the data communications and telecommunications markets, for an aggregate acquisition price of approximately $400 million in cash.

2012 was a miserable year for the semiconductor market, with only 8 of the top 25 chipmakers managing to eke out revenue growth. Among the top 25 suppliers, the only companies to expand revenue in 2012 were No. 2 Samsung, No. 3 Qualcomm, No. 9 Broadcom, No. 11 Sony, No. 14 NXP, No.15 nVidia, No.18 MediaTek and No. 24 LSI.

Worldwide PC shipments totaled 79.2 million units in the first quarter of 2013, a 11.2% decline from the first quarter of 2012, according to preliminary results by Gartner. Global PC shipments went below 80 million units for the first time since the second quarter of 2009.

3D printing, touted as an enabling platform for applications ranging from personalized medicine to personal drones, will grow to an $8.4 billion market in 2025, up from $777 million in 2012. However, consumer applications will have limited upside, according to Lux Research, while industrial uses generate the most value.

By Mark LaPedus
What impact will Intel have on the overall foundry business? In a research note, Weston Twigg, an analyst with Pacific Crest Securities, said: “Competition between Intel and the foundries, and the foundries and each other, should force high spending at the leading edge over the next two to three years. We remain bullish on equipment demand as long as Intel continues to play an aggressive role in the x86 versus ARM battle and its new foundry effort. We believe Intel is attempting to exploit its manufacturing technology advantage, which should pressure rivals TSMC and Samsung to maintain aggressive node transition plans.”

Staying in the leading-edge process technology race requires deep pockets. At 20nm and beyond, chipmakers will have to raise the CapEx ante to stay in the race. “Capital and production costs are rising faster than historic levels as logic and foundry producers migrate to 20nm and below,” Twigg said. “We expect equipment costs to rise 25% at the 22nm node and 28% at the 14nm node. New gate technologies, along with multiple-patterning steps and pitch-splitting techniques, are driving costs higher.”

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena—a series of events that brings the technology one step closer to mass production.

In coordination with the National Academy of Sciences, GlobalFoundries helped host a conference titled, “New York’s Nanotechnology Model: Building the Innovation Economy” at the Hudson Valley Community College in Troy, N.Y.

Fabless ASIC house Socle Technology named Michael Noonen as its new chairman. Noonen is still the executive vice president of global sales and marketing at GlobalFoundries, which is an investor in Socle.

The Silicon Integration Initiative (Si2) said that the ESD Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.

Mentor Graphics announced availability of a comprehensive IP-to-system, UPF-based low-power verification flow.

ARM and Cadence disclosed the details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16nm finFET process.

Peregrine Semiconductor said that its UltraCMOS phase locked loop (PLL) frequency synthesizer and prescaler devices are designed into six Globalstar mobile communication satellites that were launched into orbit in February. UltraCMOS is an advanced RF silicon-on-Insulator (SOI) process.

Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials, has been named a fellow of the Institute of Electrical and Electronics Engineers (IEEE).

Sematech executive Raj Jammy has joined Intermolecular as senior vice president and general manager of the semiconductor group.

RF Micro Devices announced the appointment of James Clifford, a former executive at Qualcomm, as vice president of foundry services.

More than one quarter of installed wafer capacity worldwide is dedicated to producing IC devices using process geometries smaller than 40nm, according to IC Insights.

In 2012, Intel retained the No. 1 market share position for the 21st year in a row, according to Gartner. Qualcomm climbed from No. 6 in 2011 to No. 3, and now trails only Intel and Samsung. Texas Instruments retained its fourth-place ranking, although Toshiba slipped to fifth place.

By Mark LaPedus
Has Apple finally hit the wall after years of sizzling growth? “Relatively soft sales of large-format iPads and iPhones are likely to drive FQ2 revenue to $41.1 billion and FQ3 revenue to $33.5 billion, both of which are below the Street estimates of $42.8 billion and $40.0 billion, respectively,” according to a research note from Pacific Crest Securities. “Among them, we consider the reduction to our large-format iPad estimates to be the most significant, as this appears likely to be a sustained trend as tablet demand shifts to smaller and less expensive models. The shifts to our iPhone estimates are largely related to the product cycle, which we consider to be a transitory issue. However, we continue to believe sell-through evidence supports our view that the high end of the smartphone market is quickly becoming saturated.”

The semiconductor equipment market continues to consolidate. Hitachi High-Technologies has completed its acquisition of SII NanoTechnology from Seiko Instruments. SII, a supplier of photomask repair tools, has been placed into a new subsidiary called Hitachi High-Tech Science. The move also propels Hitachi High-Tech into the mask repair equipment business.

The European Commission is funding yet another 450mm program. The project, called Enable450, includes Intel and fab tool vendors. It is aimed at 450mm wafer processing, specifically targeting European material and equipment companies. The group also consists of U.S. tool vendors, as well. ASM International is the coordinator of the group. Other members are Applied Materials Israel, ASML, CEA-LETI, Fraunhofer, Future Horizons, IMEC, RECIF, SEMI, Soitec, among others. At present, there is no news to report beyond the formation of this group. Stay tuned.

IC Insights has released its top-50 semiconductor supplier rankings. In the rankings, Qualcomm registered a 34% surge in sales and moved up three positions to replace TI as the fourth-largest semiconductor supplier in 2012. GlobalFoundries registered better than 30% growth last year, moving from 21st place in the rankings in 2011 to 15th last year.

Taiwan DRAM maker ProMOS Technologies has agreed to sell its 300mm wafer fab and equipment to GlobalFoundries, according to Reuters.

Peregrine Semiconductor has filed a new suit, alleging the infringement of its RF silicon-on-insulator (SOI) technology by RF Micro Devices. This new legal action is in addition to an existing suit filed by Peregrine against RFMD in February 2012. That case is still pending.

In a blog, Applied Materials’ venture capital arm discusses the lessons it has learned to ensure the mutual success of a startup company and a corporate investor.

In another blog, Applied Materials talks about the evolution of the semiconductor service model. Instead of just repairing the equipment as in the past model, the new idea is to make fab tools work better, with higher output and lower cost of ownership.

SEMI Europe honored four industry leaders for their accomplishments in developing standards for the photovoltaics (PV) industry. The SEMI Standards awards were recently announced at the SEMI PV Fab Manager Forum 2013.

Why is there a need for “best practices” in mixed-signal SoC verification, and what are some of those practices? Cadence provides some insights in a video.

Mentor Graphics said that its FloEFD computational fluid dynamics (CFD) simulation solution helped Skeleton Bobsleigh World Championship winner Shelley Rudman of Great Britain to her first world championship win on Feb. 1 in St. Moritz, Switzerland.

Analog Devices announced that CEO Jerald Fishman passed away suddenly from an apparent heart attack. ADI President Vincent Roche has been appointed CEO on an interim basis by ADI’s board. In a research note, Doug Freedman, an analyst with RBC, said: ”If Jerry Fishman did not touch your life personally, his work and that of ADI have surely touched your life. I had the pleasure of competing against ADI for 12 years, and writing investment research about ADI for another 11 years. While Jerry was given a great company to run he did so much more than could be expected. ADI has been the envy of the analog IC industry for as long as I can remember. In Silicon Valley, we watched ADI build and maintain a data convertor and amplifier franchise that is unmatched in our industry. All the while, competitors tried extremely hard to take away the market share ADI had, and at every turn Jerry, and his east coast based team, turned away the efforts from Silicon Valley and Texas. In one instance, a competitor hired a team of engineers away from ADI and was able to get a foot hold into a market. Jerry fought back and won, not just in the market but in the courts having found patents that were violated. The far reaching impact of Jerry and the work at ADI is being felt in the areas of driver safety, medical imaging, and mobile communication (none of which would be as advanced as they are today without Jerry and his team of analog engineers). In recent years he had turned his attention on making the best better, not just technically but financially. The path he sought was always clear and easy to see, for all those that wished to follow him. I always enjoyed my interactions with him and will miss his conviction, thoughts and guidance. Jerry, Your legacy lives on in your family and ADI.”

China’s move to corner the market for rare-earth minerals (REMs) has prompted manufacturers of low-voltage industrial motors to adopt alternative technologies that reduce or eliminate the use of these materials, spurring new growth in the motors market, according to IHS.