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Technologies for Advanced Systems Shown at IMEC Tech Forum USA

Tuesday, July 14th, 2015


By Ed Korczynski, Sr. Technical Editor

Luc Van den hove, president and CEO, imec opened the Imec Technology Forum – USA in San Francisco on July 13 by reminding us of the grand vision and motivation behind the work of our industry to empower individuals with micro- and nano-technologies in his talk, “From the happy few to the happy many.” While the imec consortium continues to lead the world in pure materials engineering and device exploration, they now work on systems-integration complexities with over 100 applications partners from agriculture, energy, healthcare, and transportation industries.

We are now living in an era where new chip technologies require trade-offs between power, performance, and bandwidth, and such trade-offs must be carefully explored for different applications spaces such as cloud clusters or sensor nodes. An Steegen, senior vice president process technology, imec, discussed the details of new CMOS chip extensions as well as post-CMOS device possibilities for different applications spaces in her presentation on “Technology innovation: an IoT era.” EUV lithography technology continues to be developed, targeting a single-exposure using 0.33 Numerical Aperture (NA) reflective lenses to pattern features as small as 18nm half-pitch, which would meet the Metal1 density specifications for the industry’s so-called “7nm node.” Patterning below 12nm half-pitch would seem to need higher-NA which is not an automatic extension of current EUV technology.

So while there is now some clarity regarding the pre-competitive process-technologies that will be needed to fabricate next-generation device, there is less clarity regarding which new device structures will best serve the needs of different electronics applications. CMOS finFETs using strained silicon-doped-with-Germanium Si(Ge) will eventually be replaced by gate-all-around (GAA) nano-wires (NW) using alternate-channel materials (ACM) with higher mobilities such as Ge and indium-gallium-arsenide (InGaAs). While many measures of CMOS performance improve with scaling to smaller dimensions, eventually leakage current and parasitic capacitances will impede further progress.

Figure 1 shows a summary of energy-vs.-delay analyses by imec for all manner of devices which could be used as switches in logic arrays. Spin-wave devices such as spin-transfer-torque RAM (STT-RAM) can run at low power consumption but are inherently slower than CMOS devices. Tunnel-FET (TFET) devices can be as fast or faster than CMOS while running at lower operating power due to reduced electrostatics, leading to promising R&D work.

Fig.1: Energy vs. delay for various logic switches. (Source: imec)

In an exclusive interview, Steegen explained how the consortium balances the needs of all partners in R&D, “When you try to predict future roadmaps you prefer to start from the mainstream. Trying to find the mainstream, so that customers can build derivatives from that, is what imec does. We’re getting closer to systems, and systems are reaching down to technology,” said Steegen. “We reach out to each other, while we continue to be experts in our own domains. If I’m inserting future memory into servers, the system architecture needs to change so we need to talk to the systems people. It’s a natural trend that has evolved.”

Network effects from “the cloud” and from future smart IoT nets require high-bandwidth and so improved electrical and optical connections at multiple levels are being explored at imec. Joris Van Campenhout, program director optical I/O, imec, discussed “Scaling the cloud using silicon photonics.” The challenge is how to build a 100Gb/s bandwidth in the near term, and then scale to 400G and then 1.6T though parallelism of wavelength division multiplexing; the best results to date for a transmitter and receiver reach 50Gb/s. By leveraging the existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon photonics platform enables high integration density and reduced power consumption, as well as high yield and low manufacturing cost. Supported by EDA tools including those from Mentor Graphics, there have been 7 tape-outs of devices in the last year using a Process Design Kit (PDK). When combined with laser sources and a 40nm node foundry CMOS chip, a complete integrated solution exists. Arrays of 50Gb/s structures can allow for 400Gb/s solutions by next year, and optical backplanes for server farms in another few years. However, to bring photonics closer to the chip in an optical interposer will require radical new new approaches to reduce costs, including integration of more efficient laser arrays.

Alexander Mityashin, project manager thin film electronics, imec, explained why we need, “thin film electronics for smart applications.” There are billions of items in our world that could be made smarter with electronics, provided we can use additive thin-film processes to make ultra-low-cost thin-film transistors (TFT) that fit different market demands. Using amorphous indium-gallium-zinc-oxide (a-IGZO) deposited at low-temperature as the active layer on a plastic substrate, imec has been able to produce >10k TFTs/cm2 using just 4-5 lithography masks. Figure 2 shows these TFT integrated into a near-field communications (NFC) chip as first disclosed at ISSCC earlier this year in the paper, “IGZO thin-film transistor based flexible NFC tags powered by commercial USB reader device at 13.56MHz.” Working with Panasonic in 2013, imec showed a flexible organic light-emitting diode (OLED) display of just 0.15mm thickness that can be processed at 180°C. In collaboration with the Holst Center, they have worked on disposable flexible sensors that can adhere to human skin.

Fig.2: Thin-Film Transistors (TFT) fabricated on plastic using Flat Panel Display (FPD) manufacturing tools. (Source: imec/Holst Center)

Jim O’Neill, Chief Technology Officer of Entegris, expanded on the systems-level theme of the forum in his presentation on “Putting the pieces together – Materials innovation in a disruptive environment.” With so many additional materials being integrated into new device structures, there are inherently new yield-limiting defect mechanisms that will have to be controlled. With demand for chips now being driven primarily by high-volume consumer applications, the time between first commercial sample and HVM has compressed such that greater coordination is needed between device, equipment, and materials companies. For example, instead of developing a wet chemical formulation on a tool and then optimizing it with the right filter or dispense technology, the Process Engineer can start envisioning a “bottle-to-nozzle wetted surface solution.” By considering not just the intended reactions on the wafer but the unintended reactions that can occur up-steam and down-stream of the process chamber, full solutions to the semiconductor industry’s most challenging yield problems can be more quickly found.


Solid State Watch: April 17-23, 2015

Friday, April 24th, 2015
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Proponents of EUV, immersion lithography face off at SPIE

Wednesday, February 25th, 2015

By Jeff Dorsch, contributing editor

The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium in San Jose, Calif.

Extreme-ultraviolet lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing.

On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.

There are other lithography technologies being discussed at the conference, of course. They are bit players in the drama, so to speak, although there is a lot of discussion and buzz about directed self-assembly technology this week.

ASML broke big news on Tuesday morning, reporting that Taiwan Semiconductor Manufacturing was able to expose more than 1,000 wafers in one day this year with ASML’s NXE:3300B EUV system. “During a recent test run on an NXE:3300B EUV system we exposed 1,022 wafers in 24 hours with sustained power of over 90 watts,” Anthony Yen, TSMC’s director of research and development, said at SPIE.

While ASML was obviously and justifiably proud of this milestone, after achieving its 2014 goal of producing 500 wafers per day, it cautioned that more development remains for EUV technology.

“The test run at TSMC demonstrates the capability of the NXE:3300B scanner, and moves us closer to our stated target of sustained output of 1,000 wafers per day in 2015,” ASML’s Hans Meiling, vice president service and product marketing EUV, said in a statement. “We must continue to increase source power, improve system availability, and show this result at multiple customers over multiple days.”

The day before, Cymer announced the first shipment of its XLR 700ix light source, which is said to improver scanner throughput and process stability for manufacturing chips with 14-nanometer features. The company also debuted DynaPulse as an upgrade option for its OnPulse customers. The XLR 700ix and DynaPulse together are said to offer better on-wafer critical dimension uniformity and provide stable on-wafer performance.

Another revelation at SPIE is that SK Hynix has been working with the NXE:3300, too, and is pleased with the system’s capabilities. According to Chang-Moon Lim, who spoke Monday morning, SK Hynix was recently able to expose 1,670 wafers over three days, with uptime of 86.3 percent over that period.

“Progress has been significant on various aspects, which should not be overshadowed by the delay of [light] sources,” he said of ASML’s EUV systems.

The Korean chipmaker is exploring how it could work without pellicles on the EUV reticle, Lim noted. ASML has been developing a pellicle, made with polycrystalline silicon, in cooperation with Intel and others.

Nikon Precision and other Nikon subsidiaries didn’t issue any press releases at SPIE. The companies presented much information at Sunday’s LithoVision 2015 event, held at the City National Civic auditorium, across the street from the San Jose Convention Center, where SPIE Advanced Lithography is staged.

On offer at the Nikon conference was the claimed superiority of 193i immersion lithography equipment to EUV systems for the 14nm, 7nm and future process nodes. Donis Flagello, Nikon Research Corp. of America’s president, CEO, and chief operating officer, emphasized that message on Tuesday morning with an invited paper on “Evolving optical lithography without EUV.”

Nikon’s champion machine is the NSR-S630D immersion scanner, which was touted throughout the LithoVision event. The system is capable of exposing 250 wafers per hour, according to Nikon’s Yuichi Shibazaki.

Ryoichi Kawaguchi of Nikon told attendees, “EUV lithography needs more stability and improvement.” He also brought up the topic of manufacturing on 450-millimeter wafers, which has mostly gone ignored in the lithography competition. Nikon will ship a 450mm system this spring to the Global 450 Consortium in Albany, N.Y., Kawaguchi said. The bigger substrates could provide “an alternative option to reduce cost,” he added.

Erik Byers of Micron Technology observed, “EUV is not a panacea.”

Which lithography technology will prevail in high-volume manufacturing? The question may not be definitively answered for some time.

SPIE plenary takes in photonics, 3DICs, connected devices

Monday, February 23rd, 2015

By Jeff Dorsch, contributing editor

Speakers at the plenary session of the SPIE Advanced Lithography conference covered a wide variety of topics, from photonics to 3D chips to the Internet of Things, on Monday morning, February 23, in San Jose, Calif.

Alan Willner, the Sample Chaired Professor of Engineering at the University of Southern California, described activities of the National Photonics Initiative, which he serves as chair-elect.

The initiative has attracted interest and support in Washington, D.C., with $250 million budgeted to fund an Integrated Photonics Institute for Manufacturing Innovation. There are three proposals being considered for the institute’s operation, with a decision expected in the near future, Willner said.

“Photonics spans a growing range of technologies and industries,” he noted. “This breadth has impeded the formulation of coherent strategies.”

Optics and photonics could benefit from the same type of lobbying and promotion employed by the semiconductor industry, he said. To that end, the NPI has hired the Podesta Group to provide access and insight on working with the federal government.

Tsu-Jae King Liu, chair of the University of California-Berkeley’s Department of Electrical Engineering and Computer Science, spoke about “Sustaining the Silicon Revolution” through three-dimensional semiconductor technology and 3D integration. She described the potential implementation of electro-mechanical switches, scaled down to contemporary transistor size, and a polymeric relay; both subjects led to multiple questions from interested attendees.

The plenary session concluded with a talk about the Internet of Things by Xiaowei Shen, director of IBM Research in China. “This is just the beginning of Big Data,” he said. “IoT data will dominate.”

What IBM hopes to foster is combining systems of engagement (such as social networks) and systems of record into “systems of insight,” Shen said.

Complexity is the Theme at Lithography Conference

Monday, February 23rd, 2015

By Jeff Dorsch, contributing editor

Nikon and KLA-Tencor put on separate conferences in San Jose, Calif., on Sunday, February 22, tackling issues in advanced optical lithography. The overarching theme in both sessions was the increased complexity of lithography as it approaches the 10-nanometer and 7nm process nodes.

“Complexity is much higher,” said Kevin Lucas of Synopsys at the Nikon event, LithoVision 2015. He noted that at the 28nm process node, lithographers could resort to five different options. For 14nm or 16nm, that expanded to eight options. There are 21 options available at 10nm, Lucas said, and at 7nm that explodes to more than 71 options.

“The increase in complexity is pretty dramatic,” he observed.

Electronic design automation vendors have “to provide more accurate modeling,” Lucas said. “We will have to go to better methods of [optical proximity correction].”

Ralph Dammel of EMD Performance Materials reviewed the situation in semiconductor materials as IC gate lengths continue to shrink. “We’re going to move from adding new elements to different forms of elements,” he said, such as graphene, silicine, black phosphorus, and molybdenum disulfide.

At the Lithography Users Forum, the event put on by KLA-Tencor, Mark Phillips of Intel said, “Scaling can continue, but it needs improved metrology.” He added, “We need side-by-side accuracy metrics.”

Phillips reported on Intel’s work with ASML Holding on developing pellicles for the reticles of ASML’s extreme-ultraviolet lithography systems. The companies have together come up with a prototype pellicle, which needs more development as a commercial product, he said.

SPIE panel tackles mask complexity issues

Friday, September 19th, 2014

Photomasks that take two-and-a-half days to write. Mask data preparation that enters into Big Data territory. And what happens when extreme-ultraviolet lithography really, truly arrives?

These were among the issues addressed by eight panelists in a Thursday session at the SPIE Photomask Technology conference in Monterey, Calif. Participants in the “Mask Complexity: How to Solve the Issues?” panel discussion came from multiple segments of the photomask food chain, although only one, moderator Naoya Hayashi of Dai Nippon Printing, represented a company that actually makes masks.

The panelists were generally optimistic on prospects for resolving the various issues in question. Dong-Hoon Chung of Samsung Electronics said solutions to the thorny challenges in designing, preparing, and manufacturing masks were “not impossible.”

Bala Thumma of Synopsys said he was “going to take the optimistic view” regarding mask-making challenges. “Scaling is going to continue,” he added.

“We are not at the breaking point yet,” Thumma said. “Far from it!” Electronic design automation companies like Synopsys will continue to improve their software tools, he asserted. Mask manufacturers will also benefit from “strong partnerships” with vendors of semiconductor manufacturing equipment, and “strong support from semiconductor companies,” he said.

“There is a lot of complexity,” he acknowledged. Still, going by past experience, “this group of people has been able to work together and solve these issues,” Thumma concluded.

To resolve the issue of burgeoning data volumes in mask design and manufacture, Suichiro Ohara of Nippon Control System (NCS) proposed the solution of a unified data format – specifically MALY and OASIS.MASK software. Shusuke Yoshitake of NuFlare Technology later said, “OASIS is gaining, but GDSII still predominates.”

Several panelists took the long-term view and looked beyond the coming era of EUV lithography to when multiple-beam mask writers and actinic inspection of masks will be required. EUV and actinic technology, it was generally agreed, will arrive at the 7-nanometer process node, possibly in 2017 or 2018. Multi-beam mask writers are also several years away, it was said.

As the floor was opened to questions and comments, consultant Ken Rygler noted that commercial mask makers have “very low margins” and asked, “How does the mask maker pay for the inspection tools, the EDA, materials?” Yalin Xiong of KLA-Tencor said the mask business is in “a tough time economically.” He added, “We have to look at where the high-end business is going. Captive [mask shops] should step up.”

ASML on EUV: Available at 10nm

Wednesday, September 17th, 2014


By Jeff Dorsch, contributing editor

Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

Giving the keynote presentation Tuesday at the SPIE Photomask Technology conference in Monterey, Calif., Martin offered a lengthy update on his company’s progress with EUV technology.

Sources for the next-generation lithography systems are now able to produce 77 watts of power, and ASML is shooting for 81W by the end of 2014, Martin said.

The power figure is significant since it indicates how many wafers the litho system can process, a key milestone in EUV’s progress toward becoming a volume manufacturing technology. With an 80W power source, ASML’s EUV systems could turn out 800 wafers a day, he noted.

The goal is to get to 1,000 wafers per day. ASML has lately taken to specifying throughput rates in daily production, not wafers per hour, since many wafer fabs are running nearly all the time at present.

ASML’s overarching goal is providing “affordable scaling,” Martin asserted, through what he called “holistic lithography.” This involves both immersion litho scanners and EUV machines, he said.

Martin offered a product roadmap over the next four years, concluding with manufacturing of semiconductors with 7nm features in 2018.

The ASML president acknowledged that the development of EUV has been halting over the years, while asserting that his company has made “major progress” with EUV. He said the EUV program represented “a grinding project, going on for 10 years.”

For all of EUV’s complications and travails, “nothing is impossible,” Martin told a packed auditorium at the Monterey Conference Center.

With many producers of photomasks in attendance at the conference, Martin promised, “We are not planning to make a significant change in mask infrastructure” for EUV. He added, “What you are investing today will be useful next year, and the year after that.”

Lithography: What are the alternatives to EUV?

Thursday, August 28th, 2014

By Pete Singer, Editor-in-Chief

EUV received a recent boost with IBM reporting good results on a 40W light source upgrade to its ASML NXE3300B scanner, at the EUV Center of Excellence in Albany. The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.  In the first 24 hours of operation after the upgrade, 637 wafer exposures were completed in normal production lot mode. Dan Corliss, the EUV Development Program Manager for IBM, called it a “watershed moment.”

Critics, most notably analyst Robert Maire of Semiconductor Advisors, said it was “not that much of a real increase in power and certainly no breakthrough, just incremental improvement.” He adds: “We still don’t have the reticle “ecosystem,” the resist and many other components to make for viable, commercial EUV production. We are still a very long way away and this does not change the view that EUV will not be implemented at 10nm.” The 10nm node is slated to go into production in late 2015/early 2016.

Yet EUV proponents remain optimistic. Kevin Cummings, the director of lithography at SEMATECH, said “It is good news indeed to hear that IBM in conjunction with ASML has met/exceeded their projected productivity. It is clear to this industry that the EUV LPP source was not meeting the desired schedule and the source improvements timelines were over promised. However this announcement give us some confidence that we are making progress against that schedule. In addition, this milestone is significant in that it allows the wafer throughput needed to continue EUVL HVM development. With the throughputs obtained on the scanner and the recent successes from SEMATECH on zero defect mask blanks and low-dose high-resolution resists now is an excellent time to take advantage of the Albany NY based capability to develop the materials and processes that will be needed for EUVL manufacturing.”

Luc Van den hove, president and CEO of imec, described EUV as a cost-effective lithography approach that is “absolutely needed.” In terms of imaging performance, imec has been characterizing some of the latest hardware together with ASML and have showed very good resolution performance of 13nm half pitch and 22nm contact holes. “With double patterning, we have even demonstrated 9nm half pitch,” Van den hove said. “Who would have thought a couple of years ago that this would be realizable with lithography?”

An Steegen, senior vice president of process technology at imec, said the ideal entry point for EUV is the 10nm node (or N10 using imec’s terminology). “If you look at the cost calculation, the best entry point for EUV is actually at N10 because you can replace triple patterning layers in immersion with a single patterning layer in EUV,” Steegen said. Since that will come relatively soon with early production occurring toward the end of 2015 and in early 2016, that means that likely the whole development phase will have already been built on immersion and multi-patterning. “Likely you will see on the most difficult levels, a swap, an introduction of EUV at the most critical levels later on in manufacturing for N10,” Steegen said.

Interestingly, industry-leader Intel has said that it will not use EUV for 14nm, and even sees a path to 10nm without EUV. At the Intel Developer’s Forum in 2012, Mark Bohr, director of Intel’s technology and manufacturing group said 10nm “would require quadruple patterning for some mask layers but it’s still economical.”

FIGURE 1. Multi-patterning can achieve sub-10nm dimensions. Source: Applied Materials.

FIGURE 2. Multi-patterning adds many process steps, and cost. Source: ASML.

FIGURE 1 shows that the use of spacers can enable sub-10nm dimensions without EUV. FIGURE 2 shows multi-patterning adds to process cost and complexity.

Earlier this year, at the SEMI Northeast Forum held in North Reading, MA, Patrick Martin, Senior Technology Director at Applied Materials, talked about scaling and the rising cost and complexity of patterning. “There’s a lot of talk in the industry about how scaling is dead,” he said. I think a lot of the discussions are if we look at the current architectures entitlements – finFET related technologies that scale to 7nm and 5nm, and the complexity associated with litho, driving those types of cost models, I would have to agree. But the argument is really going to be on architecture entitlement. How the devices are going to adapt to these pattern complexity limited challenges.”

Terry Lee, the chief marketing officer for the DSM business unit at Applied Materials says continued scaling will not be driven as much by lithography, but by 3D. “Scaling used to be enabled by lithography,” he said in a presentation at this year’s Semicon West. “What we’re seeing is the move to enable scaling using both materials and 3D device architectures.” 3D devices include FinFETs, 3D NAND DRAMs with buried word lines and bit lines. These devices represent “the drive to further scale on a third dimension versus scaling using lithography on a horizontal plane,” Lee said. Appled Materials recently introduced a several new products aimed at the 3D device market, including the Producer XP Precision CVD system.

“We’re really in a dilemma when it comes to semi-related production capability,” Martin said. The device features are much smaller than the wavelength that we’re using. We’re into these complex processing related technologies that require double patterning, triple patterning, multiple patterning. The great equalizer here is EUV. If we can ever get to EUV-related manufacturing capability, it gets us to a regime where the devices are relatively the same size as the wavelength of light. The problem is that it’s been delayed. The challenge is if it doesn’t hit 10nm, we’re looking at 7nm. If we start looking at the insertion opportunity for EUV at 7nm and 5nm, we’re now below wavelength. 13.5 nm is the wavelength of EUV. The complexities associated with double patterning come back into play,” Martin added.

The EUV mask challenge

The next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. According to Veeco’s Tim Pratt, Senior Director, Marketing, the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV. “Based on the yield today, the mask blank manufacturing capacity can’t produce enough mask blanks to support the ASML scanners that they’re planning to ship,” Pratt said. “ASML is going to be delivering some light source upgrades in the field and when those start happening, the effective total wafer throughput of EUV scanners in the field is going to multiply and there’s just not the supply of usable mask blanks to be able to support those.”

The requirement for 2015 is to have zero blank defects larger than 62nm. SEMATECH in 2012 reported work showing eight defects larger than 50nm. “A lot of progress being made but the elusive zero defects has not yet been hit,” Pratt said. Veeco, which is the sole supplier of EUV multilayer deposition tools, has plans to upgrade the existing Odyssey tool and launch a new platform in the 2017/2018 timeframe.

FIGURE 3. EUV masks are considerably more complicated than conventional photomasks. Source: Veeco.

FIGURE 3 shows an EUV mask, which is considerably more complicated than conventional photomasks.

What could derail the EUV ramp, according to Pratt, is a supply of defect-free mask blanks. “EUV is, despite many years and many dollars of investment, not yet in production. The two main gaps are the EUV light sources and the defects on the mask. As they start to make progress, people start to look more seriously at the list of things to worry about for EUV going to production.

The e-beam alternative

There are only a few alternatives to EUV and complex (and costly) mutli-patterning approaches: multi-e-beam (MEB), nanoimprint and directed self-assembly. Electron beam lithography with a single beam has been used for many years for mask writing and device prototyping, and tools available from a number of companies, such as Advantest, IMS, JEOL and Vistec.

Single-beam writing has never been able to compete with massively parallel optical systems in throughput and cost. Now, TSMC’s Burn Lin says that the time for e-beam lithography has arrived. Why? Digital electronics can affordably provide a gigabit per second data rate in a manageable space, enabling very high wafer throughput. Microelectrical mechanical systems and packaging techniques have advanced sufficiently to support a several order of magnitude increase in beam number and high-speed beam writing. And e-beam techniques generally offer higher resolution than optical systems. [1] Last year, TSMC and KLA-Tencor presented a reflective e-beam lithography (REBL) system that can potentially enable multiple-e-beam direct-write for high-volume manufacturing.

Multiple beam systems are also being developed by Multibeam Corp. (the well known David Lam is CEO), IMS and MAPPER. MAPPER was founded in 2000 by Professor Pieter Kruit and two of his recent graduates Marco Wieland and Bert Jan Kampherbeek.

What’s intriguing about e-beam direct write is that it could be used in conjunction with more conventional immersion lithography. Yan Borodovsky, Intel Corporation Sr. Fellow and Director of Advanced Lithography, calls it “complementary lithography.” He says that EBDW could be used instead of EUV to break the continuity of the grating made using 193i with pitch division. In addition to again maintaining the benefits of mature 193i on the critical layer, this solution has lower mask costs (no mask required for grating cutting and vias), and the escalating cost of the mask-making infrastructure is avoided.

He reported that EBDW could also be used instead of EUV for the complementary solution to break the continuity of the grating made using 193i with pitch division. In addition to again maintaining the benefits of mature 193i on the critical layer, this solution has lower mask costs (no mask required for grating cutting and vias), and the escalating cost of the mask-making infrastructure is avoided.

An organization that is focused on developing e-beam technology for mask writing and direct write is the E-beam Initiative (


Step and Flash Imprint Lithography (SFIL), a form of ultraviolet nanoimprint lithography (UV-NIL), is recognized for its resolution and patterning abilities. It is one of the few next generation lithography techniques capable of meeting the resolution requirements of future semiconductor devices. Austin-based Molecular Imprints, now a wholly owned subsidiary of Canon, has successfully commercialized the technology. Molecular Imprints invested $165 million over the last decade on platforms, materials, templates and applications.

In 2004, Canon began conducting research into nanoimprint technology to realize sub-20nm high-resolution processes began carrying out joint development with Molecular Imprints and a major semiconductor manufacturer in 2009. Canon says NIL offers such benefits as high-resolution performance, exceptional alignment accuracy and low cost. However, others report that many integration issues such as defectivity, throughput, and overlay must be resolved before SFIL can be used for leading-edge semiconductor high volume manufacturing.

DSA is very promising

Imec’s Van den hove described direct self-assembly (DSA) as “very promising” and Steegen said work there has largely focused on reducing defectivity. In DSA, resists that contain block copolymers are deposited on top of guiding structures. The self-directed nature of the process results in very regular patterns with very high resolution.

The trick with DSA is that it requires a double exposure to take away the random patterns at the edge of the device, and the resolution needed for this “cut mask” is also very high. “We’re convinced that it’s not a replacement for EUV or any high resolution lithography technique. We are very convinced it will be used in conjunction with EUV,” Van den hove said. “It certainly keeps the pressure on EUV very high.”

Steegen described DSA as a complimentary litho technique that is having quite some momentum. The process starts with a “relaxed” guiding pattern on your wafer.  Then, depending on the polymer length in the block copolymer, the space in between the guiding structure is replicated into multiple lines and spaces. “The defectivity of these materials are going to be key to bring the defects down. Our year end target is 60 defects/cm2 and this needs to go down even further next year,” she said.

Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” Steegen said. Imec is already looking at where DSA levels could be inserted into the logic N7 flow, with fins and spacers being primary targets. Steegen said the Metal1 level would be a challenge due to its irregular pattern. “That makes it not easy to be replaced with DSA, but we’re looking into techniques to do that,” she said.

Here’s how imec summed up DSA readiness:

• Good progress in material selection and integration flow optimization for line-multiplication down to 14nm, pattern transfer into bulk Si demonstrated.

• First templated DSA process available using SOG/SOC hard mask stack.

• Focus on defectivity reduction & understanding, currently at 350 defects/cm2, YE13 target 60 def/cm2

• Alignment and overlay strategy needs to be worked out

• First N7 implementation levels identified: Finfet (replace SADP EUV or SAQP 193i) and Via (replace EUV SP/DP or 193i LE3).


Hopes remain high for EUV, but long delays has caused attention to shift to possible alternatives. Multi-level patterning is costly but it works; Intel, for example, says it will soon have 14nm devices in production without using EUV. Mutli-ebeam work continue apace, and we could see a role in direct write e-beam in a complementary approach with conventional lithography. Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. Some new device structures, such as vertical NAND and FinFETs, take the pressure off of lithography, but create challenges in other process areas, such as deposition and etch.

The Week in Review: August 1, 2014

Friday, August 1st, 2014

Semiconductors providing wireless connectivity in health and fitness devices are set for solid double-digit growth in 2014 and beyond, especially as a clutch of wireless technologies make their way into a growing number of wearable devices, according to a new report from IHS Technology.

This week, IBM reported that its NXE3300B scanner, at the EUV Center of Excellence in Albany, recently completed a 40 Watt EUV light source upgrade.  The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.  In the first 24 hours of operation after the upgrade six hundred thirty seven wafer exposures were completed in normal production lot mode. Vivek Bakshi of EUV Litho, Inc. said that this is a watershed moment for EUV as it establishes the benchmark capability of the EUV source and scanner to support semiconductor technology node development.

Cambridge Nanotherm, a producer of semiconductor heatsink technology, this week announced that it has appointed semiconductor industry veteran Ralph Weir as its CEO. This follows just a few months after news of the initiation of its first production line, allowing the company to roll out its advanced nano-ceramic heat dissipation technology at high volumes to meet the growing needs of LED makers. Cambridge Nanotherm also announces the appointment of a new Business Development Director, Andrew Duncan, as well as ISO 9000 accreditation of its production line.

IHS Technology also reported that the number of smart cities worldwide will quadruple within a 12-year period that started last year, proliferating as local governments work with the private sector to cope with a multitude of challenges confronting urban centers. There will be at least 88 smart cities all over the world by 2025, up from 21 in 2013. While the combined Europe-Middle East-Africa region represented the largest number of smart cities last year, Asia-Pacific will take over the lead in 2025. In all, Asia-Pacific will account for 32 smart cities of the total in nine years’ time, Europe will have 31, and the Americas will contribute 25.

TriQuint Semiconductor, Inc., a RF solutions supplier and technology innovator, announced that it is the first gallium nitride (GaN) RF chip manufacturer to achieve Manufacturing Readiness Level (MRL) 9. This achievement means TriQuint’s GaN manufacturing processes have met full performance, cost and capacity goals, and that the company has the capability in place to support full rate production.

Research Alert: June 3, 2014

Tuesday, June 3rd, 2014

Georgia Tech research develops physics-based spintronic interconnect modeling for beyond-CMOS computing

Georgia Institute of Technology researchers collaborating with and sponsored by Intel Corporation through the Semiconductor Research Corporation (SRC) have developed a physics-based modeling platform that advances spintronics interconnect research for beyond-CMOS computing.

Spin-logic aims at reducing power consumption of electronic devices, thereby improving battery life and reducing energy consumption in computing for a whole range of electronic product applications from portable devices to data centers.

“After more than four decades of exponential growth in the performance of electronic integrated circuits, it is now apparent that improving the energy efficiency of computing is a primary challenge,” said Ian A. Young, a collaborator and co-author of the research and a Senior Fellow at Intel Corporation. “There is a global search for information processing elements that use computational state variables other than electronic charge, and these devices are being sought to bring in new functionalities and further lower the power dissipation in computers.”

One of the main motivations behind the search for a next-generation computing switch beyond CMOS (complementary metal oxide semiconductor) devices is to sustain the advancement of Moore’s Law. Nanomagnetic/spintronic devices provide a complementary option to electronics. The added functionality of this option includes the non-volatility of information on-chip, which is in essence a combination of logic and memory functions. However, to benefit from the increase in density of the on-chip devices, there has to be adequate connectivity among the switches—which is the focus of the Georgia Tech research.

Among the potential alternatives, devices based on nanoscale magnets in the field of spintronics have received special attention thanks to their advantages in terms of robustness and enhanced functionality. Magnets are non-volatile: their state remains even if the power to the circuit is switched off. Thus, the circuits do not consume power when not used—a very desirable property for modern tablets and smart phones.

One of the most important aspects of any new information processing element is how fast and power efficient they can communicate over an interconnect system with one another. In today’s CMOS chips, more energy is consumed communicating between transistor logic functions than actually processing of information. The Georgia Tech research has therefore focused on this important aspect of communicating between spin-logic devices and demonstrates that interconnects are an even more important challenge for beyond-CMOS switches.

To analyze spintronic interconnects, the Georgia Tech team and their Intel collaborators have developed compact models for spin transport in copper and aluminum—taking into account the scattering at wire surfaces and grain boundaries that become quite dominant at nanoscale dimensions. The research team has also developed compact models for the nanomagnet dynamic, electronic and spintronic transport through magnet to non-magnet interfaces, electric currents and spin diffusion. These models are all based on familiar electrical elements such as resistors and capacitors and can therefore be analyzed using standard circuit simulation tools such as SPICE.

New cost-effective nanoimprint lithography methodology improves ordering in periodic arrays from block copolymers

Block copolymers (BCPs) are the most attractive alternative to date for the fabrication of well-defined complex periodic structures with length scales below 100nm. Such small structures might be used in a wide range of technological applications but current available methods are very expensive, especially when those structures present length scales under 20nm.

A work led by the Institut Català de Nanociència i Nanotecnologia (ICN2) Phononic and Photonic Nanostructures Group suggests a new method to produce hexagonal periodic arrays with high fidelity while reducing time and costs. ICREA Research Professor Dr Clivia M. Sotomayor Torres and Dr Claudia Simão conducted, together with the authors listed below, a work published in a recent issue of Nanotechnology and featured cover article.

The methodology consists on in situ solvent-assisted nanoimprint lithography of block copolymers, a technique which combines a top-down approach – nanoimprint lithography – with a bottom-up one – self-assembled block copolymers (bottom-up). The process is assisted with solvent vapors to facilitate the imprint and simultaneous self-assembly of high Flory-Huggins parameter BCPs, the ones that yield sub-15nm size features, in what has been called solvent vapors assisted nanoimprint lithography (SAIL).

SAIL is a scalable technique which has shown its efficiency over a large area of up to four square inches wafers. The resulting sample was analysed using different methods, including field emission scanning electron microscopy (FE-SEM) and grazing-incidence small-angle x-ray scattering (GISAXS). The latter was performed at the Diamond synchrotron light source (UK) and allowed characterisation of structural features of the nanostructured polymer surfaces. It is the first time that GISAXS has been used to analyse a direct-nanoimprint BCP sample.

The results obtained with SAIL demonstrated an improvement in ordering of the nanodot lattice of up to 50%. It is a low cost, scalable and fast technique which brings self-assembled BCPs closer to their industrial application. These versatile materials are very interesting for applications such as storage devices, nano-electronics, low-k dielectrics or biochemical applications.

UT Dallas team creates flexible electronics that change shape inside body

Researchers from The University of Texas at Dallas and the University of Tokyo have created electronic devices that become soft when implanted inside the body and can deploy to grip 3-D objects, such as large tissues, nerves and blood vessels.

These biologically adaptive, flexible transistors might one day help doctors learn more about what is happening inside the body, and stimulate the body for treatments.

The research is one of the first demonstrations of transistors that can change shape and maintain their electronic properties after they are implanted in the body, said Jonathan Reeder BS ’12, a graduate student in materials science and engineering and lead author of the work.

“Scientists and physicians have been trying to put electronics in the body for a while now, but one of the problems is that the stiffness of common electronics is not compatible with biological tissue,” he said. “You need the device to be stiff at room temperature so the surgeon can implant the device, but soft and flexible enough to wrap around 3-D objects so the body can behave exactly as it would without the device. By putting electronics on shape-changing and softening polymers, we can do just that.”

Shape memory polymers developed by Dr. Walter Voit, assistant professor of materials science and engineering and mechanical engineering and an author of the paper, are key to enabling the technology.

The polymers respond to the body’s environment and become less rigid when they’re implanted. In addition to the polymers, the electronic devices are built with layers that include thin, flexible electronic foils first characterized by a group including Reeder in work published last year in Nature.

The Voit and Reeder team from the Advanced Polymer Research Lab in the Erik Jonsson School of Engineering and Computer Science fabricated the devices with an organic semiconductor but used adapted techniques normally applied to create silicon electronics that could reduce the cost of the devices.

“We used a new technique in our field to essentially laminate and cure the shape memory polymers on top of the transistors,” said Voit, who is also a member of the Texas Biomedical Device Center. “In our device design, we are getting closer to the size and stiffness of precision biologic structures, but have a long way to go to match nature’s amazing complexity, function and organization.”

The rigid devices become soft when heated. Outside the body, the device is primed for the position it will take inside the body.

During testing, researchers used heat to deploy the device around a cylinder as small as 2.25 millimeters in diameter, and implanted the device in rats. They found that after implantation, the device had morphed with the living tissue while maintaining excellent electronic properties.

“Flexible electronics today are deposited on plastic that stays the same shape and stiffness the whole time,” Reeder said. “Our research comes from a different angle and demonstrates that we can engineer a device to change shape in a more biologically compatible way.”

The next step of the research is to shrink the devices so they can wrap around smaller objects and add more sensory components, Reeder said.

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