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Lithography: What are the alternatives to EUV?

Thursday, August 28th, 2014

By Pete Singer, Editor-in-Chief

EUV received a recent boost with IBM reporting good results on a 40W light source upgrade to its ASML NXE3300B scanner, at the EUV Center of Excellence in Albany. The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.  In the first 24 hours of operation after the upgrade, 637 wafer exposures were completed in normal production lot mode. Dan Corliss, the EUV Development Program Manager for IBM, called it a “watershed moment.”

Critics, most notably analyst Robert Maire of Semiconductor Advisors, said it was “not that much of a real increase in power and certainly no breakthrough, just incremental improvement.” He adds: “We still don’t have the reticle “ecosystem,” the resist and many other components to make for viable, commercial EUV production. We are still a very long way away and this does not change the view that EUV will not be implemented at 10nm.” The 10nm node is slated to go into production in late 2015/early 2016.

Yet EUV proponents remain optimistic. Kevin Cummings, the director of lithography at SEMATECH, said “It is good news indeed to hear that IBM in conjunction with ASML has met/exceeded their projected productivity. It is clear to this industry that the EUV LPP source was not meeting the desired schedule and the source improvements timelines were over promised. However this announcement give us some confidence that we are making progress against that schedule. In addition, this milestone is significant in that it allows the wafer throughput needed to continue EUVL HVM development. With the throughputs obtained on the scanner and the recent successes from SEMATECH on zero defect mask blanks and low-dose high-resolution resists now is an excellent time to take advantage of the Albany NY based capability to develop the materials and processes that will be needed for EUVL manufacturing.”

Luc Van den hove, president and CEO of imec, described EUV as a cost-effective lithography approach that is “absolutely needed.” In terms of imaging performance, imec has been characterizing some of the latest hardware together with ASML and have showed very good resolution performance of 13nm half pitch and 22nm contact holes. “With double patterning, we have even demonstrated 9nm half pitch,” Van den hove said. “Who would have thought a couple of years ago that this would be realizable with lithography?”

An Steegen, senior vice president of process technology at imec, said the ideal entry point for EUV is the 10nm node (or N10 using imec’s terminology). “If you look at the cost calculation, the best entry point for EUV is actually at N10 because you can replace triple patterning layers in immersion with a single patterning layer in EUV,” Steegen said. Since that will come relatively soon with early production occurring toward the end of 2015 and in early 2016, that means that likely the whole development phase will have already been built on immersion and multi-patterning. “Likely you will see on the most difficult levels, a swap, an introduction of EUV at the most critical levels later on in manufacturing for N10,” Steegen said.

Interestingly, industry-leader Intel has said that it will not use EUV for 14nm, and even sees a path to 10nm without EUV. At the Intel Developer’s Forum in 2012, Mark Bohr, director of Intel’s technology and manufacturing group said 10nm “would require quadruple patterning for some mask layers but it’s still economical.”

FIGURE 1. Multi-patterning can achieve sub-10nm dimensions. Source: Applied Materials.

FIGURE 2. Multi-patterning adds many process steps, and cost. Source: ASML.

FIGURE 1 shows that the use of spacers can enable sub-10nm dimensions without EUV. FIGURE 2 shows multi-patterning adds to process cost and complexity.

Earlier this year, at the SEMI Northeast Forum held in North Reading, MA, Patrick Martin, Senior Technology Director at Applied Materials, talked about scaling and the rising cost and complexity of patterning. “There’s a lot of talk in the industry about how scaling is dead,” he said. I think a lot of the discussions are if we look at the current architectures entitlements – finFET related technologies that scale to 7nm and 5nm, and the complexity associated with litho, driving those types of cost models, I would have to agree. But the argument is really going to be on architecture entitlement. How the devices are going to adapt to these pattern complexity limited challenges.”

Terry Lee, the chief marketing officer for the DSM business unit at Applied Materials says continued scaling will not be driven as much by lithography, but by 3D. “Scaling used to be enabled by lithography,” he said in a presentation at this year’s Semicon West. “What we’re seeing is the move to enable scaling using both materials and 3D device architectures.” 3D devices include FinFETs, 3D NAND DRAMs with buried word lines and bit lines. These devices represent “the drive to further scale on a third dimension versus scaling using lithography on a horizontal plane,” Lee said. Appled Materials recently introduced a several new products aimed at the 3D device market, including the Producer XP Precision CVD system.

“We’re really in a dilemma when it comes to semi-related production capability,” Martin said. The device features are much smaller than the wavelength that we’re using. We’re into these complex processing related technologies that require double patterning, triple patterning, multiple patterning. The great equalizer here is EUV. If we can ever get to EUV-related manufacturing capability, it gets us to a regime where the devices are relatively the same size as the wavelength of light. The problem is that it’s been delayed. The challenge is if it doesn’t hit 10nm, we’re looking at 7nm. If we start looking at the insertion opportunity for EUV at 7nm and 5nm, we’re now below wavelength. 13.5 nm is the wavelength of EUV. The complexities associated with double patterning come back into play,” Martin added.

The EUV mask challenge

The next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. According to Veeco’s Tim Pratt, Senior Director, Marketing, the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV. “Based on the yield today, the mask blank manufacturing capacity can’t produce enough mask blanks to support the ASML scanners that they’re planning to ship,” Pratt said. “ASML is going to be delivering some light source upgrades in the field and when those start happening, the effective total wafer throughput of EUV scanners in the field is going to multiply and there’s just not the supply of usable mask blanks to be able to support those.”

The requirement for 2015 is to have zero blank defects larger than 62nm. SEMATECH in 2012 reported work showing eight defects larger than 50nm. “A lot of progress being made but the elusive zero defects has not yet been hit,” Pratt said. Veeco, which is the sole supplier of EUV multilayer deposition tools, has plans to upgrade the existing Odyssey tool and launch a new platform in the 2017/2018 timeframe.

FIGURE 3. EUV masks are considerably more complicated than conventional photomasks. Source: Veeco.

FIGURE 3 shows an EUV mask, which is considerably more complicated than conventional photomasks.

What could derail the EUV ramp, according to Pratt, is a supply of defect-free mask blanks. “EUV is, despite many years and many dollars of investment, not yet in production. The two main gaps are the EUV light sources and the defects on the mask. As they start to make progress, people start to look more seriously at the list of things to worry about for EUV going to production.

The e-beam alternative

There are only a few alternatives to EUV and complex (and costly) mutli-patterning approaches: multi-e-beam (MEB), nanoimprint and directed self-assembly. Electron beam lithography with a single beam has been used for many years for mask writing and device prototyping, and tools available from a number of companies, such as Advantest, IMS, JEOL and Vistec.

Single-beam writing has never been able to compete with massively parallel optical systems in throughput and cost. Now, TSMC’s Burn Lin says that the time for e-beam lithography has arrived. Why? Digital electronics can affordably provide a gigabit per second data rate in a manageable space, enabling very high wafer throughput. Microelectrical mechanical systems and packaging techniques have advanced sufficiently to support a several order of magnitude increase in beam number and high-speed beam writing. And e-beam techniques generally offer higher resolution than optical systems. [1] Last year, TSMC and KLA-Tencor presented a reflective e-beam lithography (REBL) system that can potentially enable multiple-e-beam direct-write for high-volume manufacturing.

Multiple beam systems are also being developed by Multibeam Corp. (the well known David Lam is CEO), IMS and MAPPER. MAPPER was founded in 2000 by Professor Pieter Kruit and two of his recent graduates Marco Wieland and Bert Jan Kampherbeek.

What’s intriguing about e-beam direct write is that it could be used in conjunction with more conventional immersion lithography. Yan Borodovsky, Intel Corporation Sr. Fellow and Director of Advanced Lithography, calls it “complementary lithography.” He says that EBDW could be used instead of EUV to break the continuity of the grating made using 193i with pitch division. In addition to again maintaining the benefits of mature 193i on the critical layer, this solution has lower mask costs (no mask required for grating cutting and vias), and the escalating cost of the mask-making infrastructure is avoided.

He reported that EBDW could also be used instead of EUV for the complementary solution to break the continuity of the grating made using 193i with pitch division. In addition to again maintaining the benefits of mature 193i on the critical layer, this solution has lower mask costs (no mask required for grating cutting and vias), and the escalating cost of the mask-making infrastructure is avoided.

An organization that is focused on developing e-beam technology for mask writing and direct write is the E-beam Initiative (www.ebeam.org).

Nanoimprint

Step and Flash Imprint Lithography (SFIL), a form of ultraviolet nanoimprint lithography (UV-NIL), is recognized for its resolution and patterning abilities. It is one of the few next generation lithography techniques capable of meeting the resolution requirements of future semiconductor devices. Austin-based Molecular Imprints, now a wholly owned subsidiary of Canon, has successfully commercialized the technology. Molecular Imprints invested $165 million over the last decade on platforms, materials, templates and applications.

In 2004, Canon began conducting research into nanoimprint technology to realize sub-20nm high-resolution processes began carrying out joint development with Molecular Imprints and a major semiconductor manufacturer in 2009. Canon says NIL offers such benefits as high-resolution performance, exceptional alignment accuracy and low cost. However, others report that many integration issues such as defectivity, throughput, and overlay must be resolved before SFIL can be used for leading-edge semiconductor high volume manufacturing.

DSA is very promising

Imec’s Van den hove described direct self-assembly (DSA) as “very promising” and Steegen said work there has largely focused on reducing defectivity. In DSA, resists that contain block copolymers are deposited on top of guiding structures. The self-directed nature of the process results in very regular patterns with very high resolution.

The trick with DSA is that it requires a double exposure to take away the random patterns at the edge of the device, and the resolution needed for this “cut mask” is also very high. “We’re convinced that it’s not a replacement for EUV or any high resolution lithography technique. We are very convinced it will be used in conjunction with EUV,” Van den hove said. “It certainly keeps the pressure on EUV very high.”

Steegen described DSA as a complimentary litho technique that is having quite some momentum. The process starts with a “relaxed” guiding pattern on your wafer.  Then, depending on the polymer length in the block copolymer, the space in between the guiding structure is replicated into multiple lines and spaces. “The defectivity of these materials are going to be key to bring the defects down. Our year end target is 60 defects/cm2 and this needs to go down even further next year,” she said.

Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” Steegen said. Imec is already looking at where DSA levels could be inserted into the logic N7 flow, with fins and spacers being primary targets. Steegen said the Metal1 level would be a challenge due to its irregular pattern. “That makes it not easy to be replaced with DSA, but we’re looking into techniques to do that,” she said.

Here’s how imec summed up DSA readiness:

• Good progress in material selection and integration flow optimization for line-multiplication down to 14nm, pattern transfer into bulk Si demonstrated.

• First templated DSA process available using SOG/SOC hard mask stack.

• Focus on defectivity reduction & understanding, currently at 350 defects/cm2, YE13 target 60 def/cm2

• Alignment and overlay strategy needs to be worked out

• First N7 implementation levels identified: Finfet (replace SADP EUV or SAQP 193i) and Via (replace EUV SP/DP or 193i LE3).

Conclusion

Hopes remain high for EUV, but long delays has caused attention to shift to possible alternatives. Multi-level patterning is costly but it works; Intel, for example, says it will soon have 14nm devices in production without using EUV. Mutli-ebeam work continue apace, and we could see a role in direct write e-beam in a complementary approach with conventional lithography. Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. Some new device structures, such as vertical NAND and FinFETs, take the pressure off of lithography, but create challenges in other process areas, such as deposition and etch.

The Week in Review: August 1, 2014

Friday, August 1st, 2014

Semiconductors providing wireless connectivity in health and fitness devices are set for solid double-digit growth in 2014 and beyond, especially as a clutch of wireless technologies make their way into a growing number of wearable devices, according to a new report from IHS Technology.

This week, IBM reported that its NXE3300B scanner, at the EUV Center of Excellence in Albany, recently completed a 40 Watt EUV light source upgrade.  The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.  In the first 24 hours of operation after the upgrade six hundred thirty seven wafer exposures were completed in normal production lot mode. Vivek Bakshi of EUV Litho, Inc. said that this is a watershed moment for EUV as it establishes the benchmark capability of the EUV source and scanner to support semiconductor technology node development.

Cambridge Nanotherm, a producer of semiconductor heatsink technology, this week announced that it has appointed semiconductor industry veteran Ralph Weir as its CEO. This follows just a few months after news of the initiation of its first production line, allowing the company to roll out its advanced nano-ceramic heat dissipation technology at high volumes to meet the growing needs of LED makers. Cambridge Nanotherm also announces the appointment of a new Business Development Director, Andrew Duncan, as well as ISO 9000 accreditation of its production line.

IHS Technology also reported that the number of smart cities worldwide will quadruple within a 12-year period that started last year, proliferating as local governments work with the private sector to cope with a multitude of challenges confronting urban centers. There will be at least 88 smart cities all over the world by 2025, up from 21 in 2013. While the combined Europe-Middle East-Africa region represented the largest number of smart cities last year, Asia-Pacific will take over the lead in 2025. In all, Asia-Pacific will account for 32 smart cities of the total in nine years’ time, Europe will have 31, and the Americas will contribute 25.

TriQuint Semiconductor, Inc., a RF solutions supplier and technology innovator, announced that it is the first gallium nitride (GaN) RF chip manufacturer to achieve Manufacturing Readiness Level (MRL) 9. This achievement means TriQuint’s GaN manufacturing processes have met full performance, cost and capacity goals, and that the company has the capability in place to support full rate production.

Research Alert: June 3, 2014

Tuesday, June 3rd, 2014

Georgia Tech research develops physics-based spintronic interconnect modeling for beyond-CMOS computing

Georgia Institute of Technology researchers collaborating with and sponsored by Intel Corporation through the Semiconductor Research Corporation (SRC) have developed a physics-based modeling platform that advances spintronics interconnect research for beyond-CMOS computing.

Spin-logic aims at reducing power consumption of electronic devices, thereby improving battery life and reducing energy consumption in computing for a whole range of electronic product applications from portable devices to data centers.

“After more than four decades of exponential growth in the performance of electronic integrated circuits, it is now apparent that improving the energy efficiency of computing is a primary challenge,” said Ian A. Young, a collaborator and co-author of the research and a Senior Fellow at Intel Corporation. “There is a global search for information processing elements that use computational state variables other than electronic charge, and these devices are being sought to bring in new functionalities and further lower the power dissipation in computers.”

One of the main motivations behind the search for a next-generation computing switch beyond CMOS (complementary metal oxide semiconductor) devices is to sustain the advancement of Moore’s Law. Nanomagnetic/spintronic devices provide a complementary option to electronics. The added functionality of this option includes the non-volatility of information on-chip, which is in essence a combination of logic and memory functions. However, to benefit from the increase in density of the on-chip devices, there has to be adequate connectivity among the switches—which is the focus of the Georgia Tech research.

Among the potential alternatives, devices based on nanoscale magnets in the field of spintronics have received special attention thanks to their advantages in terms of robustness and enhanced functionality. Magnets are non-volatile: their state remains even if the power to the circuit is switched off. Thus, the circuits do not consume power when not used—a very desirable property for modern tablets and smart phones.

One of the most important aspects of any new information processing element is how fast and power efficient they can communicate over an interconnect system with one another. In today’s CMOS chips, more energy is consumed communicating between transistor logic functions than actually processing of information. The Georgia Tech research has therefore focused on this important aspect of communicating between spin-logic devices and demonstrates that interconnects are an even more important challenge for beyond-CMOS switches.

To analyze spintronic interconnects, the Georgia Tech team and their Intel collaborators have developed compact models for spin transport in copper and aluminum—taking into account the scattering at wire surfaces and grain boundaries that become quite dominant at nanoscale dimensions. The research team has also developed compact models for the nanomagnet dynamic, electronic and spintronic transport through magnet to non-magnet interfaces, electric currents and spin diffusion. These models are all based on familiar electrical elements such as resistors and capacitors and can therefore be analyzed using standard circuit simulation tools such as SPICE.

New cost-effective nanoimprint lithography methodology improves ordering in periodic arrays from block copolymers

Block copolymers (BCPs) are the most attractive alternative to date for the fabrication of well-defined complex periodic structures with length scales below 100nm. Such small structures might be used in a wide range of technological applications but current available methods are very expensive, especially when those structures present length scales under 20nm.

A work led by the Institut Català de Nanociència i Nanotecnologia (ICN2) Phononic and Photonic Nanostructures Group suggests a new method to produce hexagonal periodic arrays with high fidelity while reducing time and costs. ICREA Research Professor Dr Clivia M. Sotomayor Torres and Dr Claudia Simão conducted, together with the authors listed below, a work published in a recent issue of Nanotechnology and featured cover article.

The methodology consists on in situ solvent-assisted nanoimprint lithography of block copolymers, a technique which combines a top-down approach – nanoimprint lithography – with a bottom-up one – self-assembled block copolymers (bottom-up). The process is assisted with solvent vapors to facilitate the imprint and simultaneous self-assembly of high Flory-Huggins parameter BCPs, the ones that yield sub-15nm size features, in what has been called solvent vapors assisted nanoimprint lithography (SAIL).

SAIL is a scalable technique which has shown its efficiency over a large area of up to four square inches wafers. The resulting sample was analysed using different methods, including field emission scanning electron microscopy (FE-SEM) and grazing-incidence small-angle x-ray scattering (GISAXS). The latter was performed at the Diamond synchrotron light source (UK) and allowed characterisation of structural features of the nanostructured polymer surfaces. It is the first time that GISAXS has been used to analyse a direct-nanoimprint BCP sample.

The results obtained with SAIL demonstrated an improvement in ordering of the nanodot lattice of up to 50%. It is a low cost, scalable and fast technique which brings self-assembled BCPs closer to their industrial application. These versatile materials are very interesting for applications such as storage devices, nano-electronics, low-k dielectrics or biochemical applications.

UT Dallas team creates flexible electronics that change shape inside body

Researchers from The University of Texas at Dallas and the University of Tokyo have created electronic devices that become soft when implanted inside the body and can deploy to grip 3-D objects, such as large tissues, nerves and blood vessels.

These biologically adaptive, flexible transistors might one day help doctors learn more about what is happening inside the body, and stimulate the body for treatments.

The research is one of the first demonstrations of transistors that can change shape and maintain their electronic properties after they are implanted in the body, said Jonathan Reeder BS ’12, a graduate student in materials science and engineering and lead author of the work.

“Scientists and physicians have been trying to put electronics in the body for a while now, but one of the problems is that the stiffness of common electronics is not compatible with biological tissue,” he said. “You need the device to be stiff at room temperature so the surgeon can implant the device, but soft and flexible enough to wrap around 3-D objects so the body can behave exactly as it would without the device. By putting electronics on shape-changing and softening polymers, we can do just that.”

Shape memory polymers developed by Dr. Walter Voit, assistant professor of materials science and engineering and mechanical engineering and an author of the paper, are key to enabling the technology.

The polymers respond to the body’s environment and become less rigid when they’re implanted. In addition to the polymers, the electronic devices are built with layers that include thin, flexible electronic foils first characterized by a group including Reeder in work published last year in Nature.

The Voit and Reeder team from the Advanced Polymer Research Lab in the Erik Jonsson School of Engineering and Computer Science fabricated the devices with an organic semiconductor but used adapted techniques normally applied to create silicon electronics that could reduce the cost of the devices.

“We used a new technique in our field to essentially laminate and cure the shape memory polymers on top of the transistors,” said Voit, who is also a member of the Texas Biomedical Device Center. “In our device design, we are getting closer to the size and stiffness of precision biologic structures, but have a long way to go to match nature’s amazing complexity, function and organization.”

The rigid devices become soft when heated. Outside the body, the device is primed for the position it will take inside the body.

During testing, researchers used heat to deploy the device around a cylinder as small as 2.25 millimeters in diameter, and implanted the device in rats. They found that after implantation, the device had morphed with the living tissue while maintaining excellent electronic properties.

“Flexible electronics today are deposited on plastic that stays the same shape and stiffness the whole time,” Reeder said. “Our research comes from a different angle and demonstrates that we can engineer a device to change shape in a more biologically compatible way.”

The next step of the research is to shrink the devices so they can wrap around smaller objects and add more sensory components, Reeder said.

The Week in Review: March 28, 2014

Friday, March 28th, 2014

Altera Corporation and Intel Corporation announced their collaboration on the development of multi-die devices that leverage Intel’s package and assembly capabilities and Altera’s leading-edge programmable logic technology. The collaboration is an extension of the foundry relationship between Altera and Intel, in which Intel is manufacturing Altera’s Stratix 10 FPGAs and SoCs using the 14nm Tri-Gate process. Altera’s work with Intel will enable the development of multi-die devices that efficiently integrates monolithic 14nm Stratix 10 FPGAs and SoCs with other advanced components, which may include DRAM, SRAM, ASICs, processors and analog components, in a single package.

Samsung introduced a new lineup of flip chip LED packages and modules offering enhanced design flexibility and a high degree of reliability. The new offerings, for use in leading-edge LED lighting such as LED bulbs, MR/PAR and downlights, will be available in the market during the second quarter of this year. Samsung’s new flip chip (FC) LED package and flip chip on module (FCOM) solutions feature highly efficient and versatile LED structures, created by flipping over blue LED chips and adhering phosphor film to each of them. Unlike conventional LED packages that dispense phosphor and then place a plastic mold over each chip, Samsung’s FC package technology can produce LED packages down to a chip-scale size without any mold, enabling more compact lighting fixture designs.

eInfochips, a semiconductor and product engineering company, this week launched design services for chips based on 16nm geometry. The comprehensive suite of services includes Netlist to GDSII, Sign-off, and Design for Testability. eInfochips is one of the few engineering services companies in the world capable of delivering 16nm chip designs which reduce a chip’s power consumption by half, while improving performance by one-third over 28nm technology.

SEMATECH announced this week that Particle Measuring Systems has joined SEMATECH to advance the development of nanoscale particle removal processes and cleaning technologies for next-generation wafers and devices. This collaboration will address many of the profound changes taking place in the semiconductor industry that are impacting fundamental aspects of process and equipment design, including integration of new materials and process technology for sub-20nm node manufacturing, next-generation lithography requirements.

CEA-Leti will demonstrate its new prototype for wireless high data rate Li-Fi (light fidelity) transmission at Light + Building 2014 in Frankfurt, Germany, March 30-April 4. The technology employs the high-frequency modulation capabilities of light-emitting diode (LED) engines used in commercial lighting. It achieves throughputs of up to 10Mb/s at a range of three meters, suitable for HD video streaming or Internet browsing, using light power of less than 1,000 lumens and with direct or even indirect lighting. With this first proof of concept and its expertise in RF communications, Leti forecasts data transmission rates in excess of 100Mb/s with traditional lighting based on LED lamps using this technology approach and without altering the high-performance lighting characteristics.

Research Alert: March 18, 2014

Tuesday, March 18th, 2014

Creating a graphene-metal sandwich to improve electronics

Researchers have discovered that creating a graphene-copper-graphene “sandwich” strongly enhances the heat conducting properties of copper, a discovery that could further help in the downscaling of electronics.

The work was led by Alexander A. Balandin, a professor of electrical engineering at the Bourns College of Engineering at the University of California, Riverside and Konstantin S. Novoselov, a professor of physics at the University of Manchester in the United Kingdom. Balandin and Novoselov are corresponding authors for the paper just published in the journal Nano Letters. In 2010, Novoselov shared the Nobel Prize in Physics with Andre Geim for their discovery of graphene.

In the experiments, the researchers found that adding a layer of graphene, a one-atom thick material with highly desirable electrical, thermal and mechanical properties, on each side of a copper film increased heat conducting properties up to 24 percent.

“This enhancement of copper’s ability to conduct heat could become important in the development of hybrid copper — graphene interconnects for electronic chips that continue to get smaller and smaller,” said Balandin, who in 2013 was awarded the MRS Medal from the Materials Research Society for discovery of unusual heat conduction properties of graphene.

Whether the heat conducting properties of copper would improve by layering it with graphene is an important question because copper is the material used for semiconductor interconnects in modern computer chips. Copper replaced aluminum because of its better electrical conductivity.

Surface characteristics influence cellular growth on semiconductor material

Changing the texture and surface characteristics of a semiconductor material at the nanoscale can influence the way that neural cells grow on the material.

The finding stems from a study performed by researchers at North Carolina State University, the University of North Carolina at Chapel Hill and Purdue University, and may have utility for developing future neural implants.

“We wanted to know how a material’s texture and structure can influence cell adhesion and differentiation,” says Lauren Bain, lead author of a paper describing the work and a Ph.D. student in the joint biomedical engineering program at NC State and UNC-Chapel Hill. “Basically, we wanted to know if changing the physical characteristics on the surface of a semiconductor could make it easier for an implant to be integrated into neural tissue – or soft tissue generally.”

The researchers worked with gallium nitride (GaN), because it is one of the most promising semiconductor materials for use in biomedical applications. They also worked with PC12 cells, which are model cells used to mimic the behavior of neurons in lab experiments.

In the study, the researchers grew PC12 cells on GaN squares with four different surface characteristics: some squares were smooth; some had parallel grooves (resembling an irregular corduroy pattern); some were randomly textured (resembling a nanoscale mountain range); and some were covered with nanowires (resembling a nanoscale bed of nails).

Very few PC12 cells adhered to the smooth surface. And those that did adhere grew normally, forming long, narrow extensions. More PC12 cells adhered to the squares with parallel grooves, and these cells also grew normally.

About the same number of PC12 cells adhered to the randomly textured squares as adhered to the parallel grooves. However, these cells did not grow normally. Instead of forming narrow extensions, the cells flattened and spread across the GaN surface in all directions.

More PC12 cells adhered to the nanowire squares than to any of the other surfaces, but only 50 percent of the cells grew normally. The other 50 percent spread in all directions, like the cells on the randomly textured surfaces.

“This tells us that the actual shape of the surface characteristics influences the behavior of the cells,” Bain says. “It’s a non-chemical way of influencing the interaction between the material and the body. That’s something we can explore as we continue working to develop new biomedical technologies.”

First methodology to analyze nanometer line pattern images

In the study, the researchers grew PC12 cells on GaN squares with four different surface characteristics: some squares were smooth; some had parallel grooves (resembling an irregular corduroy pattern); some were randomly textured (resembling a nanoscale mountain range); and some were covered with nanowires (resembling a nanoscale bed of nails).

Very few PC12 cells adhered to the smooth surface. And those that did adhere grew normally, forming long, narrow extensions. More PC12 cells adhered to the squares with parallel grooves, and these cells also grew normally.

About the same number of PC12 cells adhered to the randomly textured squares as adhered to the parallel grooves. However, these cells did not grow normally. Instead of forming narrow extensions, the cells flattened and spread across the GaN surface in all directions.

More PC12 cells adhered to the nanowire squares than to any of the other surfaces, but only 50 percent of the cells grew normally. The other 50 percent spread in all directions, like the cells on the randomly textured surfaces.

“This tells us that the actual shape of the surface characteristics influences the behavior of the cells,” Bain says. “It’s a non-chemical way of influencing the interaction between the material and the body. That’s something we can explore as we continue working to develop new biomedical technologies.”

Research Alert: March 4, 2014

Tuesday, March 4th, 2014

SRC and MIT extend high-resolution lithography

MIT researchers sponsored by Semiconductor Research Corporation have introduced new directed self-assembly (DSA) techniques that promise to help semiconductor manufacturers develop more advanced and less expensive components.

The MIT study demonstrates that complex patterns of lines, bends and junctions with feature sizes below 20nm can be made by block copolymer self-assembly guided by a greatly simplified template. This study explained how to design the template to achieve a desired pattern. Electron-beam lithography was used to produce the template serially, while the block copolymer filled in the rest of the pattern in a parallel process. This hybrid process can be five or more times faster than writing the entire pattern by electron beam lithography.

sembly to produce dense, high resolution patterns was proposed and demonstrated several years ago, but there was no systematic way to design templates to achieve a complex block copolymer pattern. The MIT study developed a simple way to design a template to achieve a specific block copolymer pattern over a large area. Although the work used electron-beam lithography to define the template, other methods such as photolithography with trimming could be used to produce the templates.

Block copolymer lithography is already on the semiconductor industry roadmap as directed self-assembly, but the process is still in its infancy. Although DSA patterning has been demonstrated on 300 millimeter wafers, these early trials used templates fabricated by photolithography with limited resolution and limited control of the feature geometry. The MIT process offers a path to far more complicated geometries using relatively simple templates. Next steps involve the research being shared with semiconductor companies for further studies.

How 19th century physics could change the future of nanotechnology

Researchers at the University of Cincinnati have found that their unique method of light-matter interaction analysis appears to be a good way of helping make better semiconductor nanowires.

“Semiconductor nanowires are one of the hottest topics in the nanoscience research field in the recent decade,” says Yuda Wang, a UC doctoral student. “Due to the unique geometry compared to conventional bulk semiconductors, nanowires have already shown many advantageous properties, particularly in novel applications in such fields as nanoelectronics, nanophotonics, nanobiochemistry and nanoenergy.”

Wang will present the team’s research “Transient Rayleigh Scattering Spectroscopy Measurement of Carrier Dynamics in Zincblende and Wurtzite Indium Phosphide Nanowires” at the American Physical Society (APS) meeting to be held March 3-7 in Denver. Nearly 10,000 professionals, scholars and students will attend the APS meeting to discuss new research from industry, universities and laboratories from around the world.

Key to this research is UC’s new method of Rayleigh scattering, a phenomenon first described in 1871 and the scientific explanation for why the sky is blue in the daytime and turns red at sunset. The researchers’ Rayleigh scattering technique probes the band structures and electron-hole dynamics inside a single indium phosphide nanowire, allowing them to observe the response with a time resolution in the femtosecond range – or one quadrillionth of a second.

JILA physicists discover “quantum droplet” in semiconductor

JILA physicists used an ultrafast laser and help from German theorists to discover a new semiconductor quasiparticle—a handful of smaller particles that briefly condense into a liquid-like droplet.

Quasiparticles are composites of smaller particles that can be created inside solid materials and act together in a predictable way. A simple example is the exciton, a pairing, due to electrostatic forces, of an electron and a so-called “hole,” a place in the material’s energy structure where an electron could be, but isn’t.

The new quasiparticle, described in the Feb. 27, 2014, issue of Nature and featured on the journal’s cover, is a microscopic complex of electrons and holes in a new, unpaired arrangement. The researchers call this a “quantum droplet” because it has quantum characteristics such as well-ordered energy levels, but also has some of the characteristics of a liquid. It can have ripples, for example. It differs from a familiar liquid like water because the quantum droplet has a finite size, beyond which the association between electrons and holes disappears.

Although its lifetime is only a fleeting 25 picoseconds (trillionths of a second), the quantum droplet is stable enough for research on how light interacts with specialized forms of matter.

The JILA team created the new quasiparticle by exciting a gallium-arsenide semiconductor with an ultrafast red laser emitting about 100 million pulses per second. The pulses initially form excitons, which are known to travel around in semiconductors. As laser pulse intensity increases, more electron-hole pairs are created, with quantum droplets developing when the exciton density reaches a certain level. At that point, the pairing disappears and a few electrons take up positions relative to a given hole. The negatively charged electrons and positively charged holes create a neutral droplet. The droplets are like bubbles held together briefly by pressure from the surrounding plasma.

The Week in Review: Nov. 22, 2013

Friday, November 22nd, 2013

GLOBALFOUNDRIES, Open-Silicon and Amkor Technology have jointly exhibited a functional system-on-chip (SoC) solution on a 2.5D silicon interposer featuring two 28nm logic chips, with embedded ARM processors. The jointly developed design is a test vehicle that showcases the benefits of 2.5D technology for mobile and low-power server applications. The companies recently demonstrated the functioning SoC at ARM TechCon in Santa Clara, CA.

North America-based manufacturers of semiconductor equipment posted $1.12 billion in orders worldwide in October 2013 (three-month average basis) and a book-to-bill ratio of 1.05, according to the October EMDS Book-to-Bill Report published this week by SEMI.   A book-to-bill of 1.05 means that $105 worth of orders were received for every $100 of product billed for the month. “Both equipment orders and billings improved in the October data, resulting in a book-to-bill ratio returning above parity,” said Denny McGuirk, president and CEO of SEMI.  ”Order activity is well above the figures reported one year ago and point towards on-going investments in advanced process technologies for NAND Flash, microprocessor, and foundry.”

Soraa, a developer of GaN on GaN LED technology, announced that it will open a new semiconductor fabrication plant in Buffalo, New York. In partnership with the State of New York, the company will construct a new state-of-the-art GaN on GaN LED fabrication facility that will employ hundreds of workers. The new facility is projected to be operational in 2015. Soraa currently operates an LED fabrication plant in Fremont, California, one of only a few in the US.

Dow Corning introduced new Dow Corning MS-2002 Moldable White Reflector Silicone at Strategies in Light Europe 2013. This highly reflective white material extends the excellent photo-thermal stability and high-moldability that typifies Dow Corning’s award-winning optical-grade Moldable Silicone family to the reflective elements of LED lamp and luminaire applications. Dow Corning MS-2002 Moldable White Reflector Silicone targets reflectivity as high as 98 percent to help further boost light output from LED devices, improve overall energy efficiency and prolong device reliability.

SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets, has successfully installed an ELP300 excimer laser stepper to support next generation advanced packaging and 3D IC laser debonding applications at the Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin. The ELP300 excimer laser platform is designed for high volume manufacturing and processing of 100mm to 300mm wafers.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, introduced the EVG PHABLE exposure system, which is designed specifically for manufacturing photonic components.  Leveraging EVG’s expertise in photolithography, the EVG PHABLE system incorporates a unique contactless lithography mask-based approach that enables full-field, high-resolution and cost-efficient micro- and nanopatterning of passive and active photonic components, such as patterned structures on light emitting diode (LED) wafers, in high-throughput production environments.

The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions

Thursday, September 19th, 2013

Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models, in turn, rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. While certain system input variables, such as scanner numerical aperture, can be empirically tuned to wafer CD data over a small range around the presumed set point, it can be dangerous to do so since CD errors can alias across multiple input variables. Therefore, many input variables for simulation are based upon designed or recipe-requested values or independent measurements. However, certain measurement methodologies, while precise, can be inaccurate. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total CD control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine with a simulation sensitivity study, the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD Bias values are based on state of the art mask manufacturing data and other variables changes are speculated, highlighting the need for improved metrology and awareness.

To download this white paper, click here.

EUV Flare And Proximity Modeling And Model-Based Correction

Thursday, May 16th, 2013

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. This paper focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based.

To view this white paper, click here.

Computational Lithography

Thursday, March 21st, 2013

Computational lithography has become an integral part of design since the 130 nm process node. New techniques continue to be developed to extend the steady node shrink year after year.

To read this white paper, click here.

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