By Jeff Chappell
By now, with the rise of China as a center of manufacturing, everyone in the chip industry has no doubt heard of the supposed Chinese curse, “May you live in interesting times.” It’s practically cliché. The thing is, the next two industry cycles may indeed prove interesting for the used equipment market.

At the moment, everyone is tired of interesting times, and those in the used equipment sector are no different. The current industry downturn has been one of the longest ones in recent memory for them.

It’s difficult to express how bad things have been in terms of numbers for the used chip equipment market. The sector is fragmented, and much of the buying and selling is between brokers—often for specific customers. But one thing is clear: Times have been tough.

“This has been the longest sustained downturn in the used equipment market in the 16 years that I’ve been in it,” said Julian Gates, managing director for AG Semiconductor Services. AG is one of the largest, if not the largest, suppliers of used semiconductor capital equipment and services in the industry.

“We’ve seen worse, but this one has been sustained for a long time and has had a real negative impact on everyone in the used equipment market,” Gates said. It is a sentiment voiced by others in the market, whether they’re based in the United States, China or Europe.

Even as some first-tier chipmakers are moving to add capacity, things are quiet among second-tier customers. “I haven’t heard of a second-tier scanner that was sold in the last three months,” remarked one sales executive from used equipment supplier SDI Fabsurplus LLC.

But there are signs of the proverbial light at the end of the tunnel. Just as there has been talk of capacity expansion in the chip industry, consequently there are signs the market for used equipment may be picking up. One of the few notable bright spots this spring for purveyors of refurbished semiconductor capital equipment and services has been in the packaging front, where 3D packaging and related newly-developing technologies are proving drivers in the chip industry as a whole. In terms of equipment, that means a need for wet processing, plating, physical vapor deposition (PVD), photolithography and etch equipment.

This technology-driven expansion is coupled with the fact that companies in the backend are also looking to move packaging and test operations to mainland China. The market for analog and power devices also has remained strong, as has demand for memory to some extent, all driven by consumer electronic devices. And all this has helped drive what business there is of late in the used equipment sector.

But as a whole the entire market, in terms of geography, is really quiet, used equipment providers say—even China, where the only projects of any notable size currently underway are being driven by the government, as opposed to the private sector. As one Fabsurplus sales executive tersely quipped of the Chinese market, “It’s not hot.”

But recently interest on the part of customers has picked up across much of the used chip equipment market. As one Shanghai-based equipment sales executive noted with regard to China and packaging, no one is doing through-silicon vias (TSVs) just yet, but everyone there is talking about it. Whether or not all this interest translates into actual orders in the latter half of the year remains to be seen. Historically, however, increased activity in the backend, i.e. packaging, usually presages a broader rebound, and used equipment vendors are cautiously optimistic.

“We are seeing definite signs of an uptick,” said AG Semi’s Gates. “For the first time in a year and a half, people are broadcasting their intent to invest. Our hope is that it will be sustained … and not just an initial hype that we see sometimes.”

He characterized this interest as potentially large expansions in Asia, Brazil and India, where companies are looking to invest in entirely new—to them, at least—manufacturing lines. North America and Europe are still quiet, he said, but these markets usually follow as interest builds elsewhere.

At least one used equipment company that is focused on the European market is anticipating an uptick of orders in Q4, however. Some European device makers are currently planning to convert fab lines to what is, for them, next-generation technology, said Tony McKie, CEO of memsstar.

UK-based memsstar is focused on the market for deposition and etch equipment and related support services for both semiconductor and microelectromechanical systems (MEMS) applications. McKie noted the company recently has done several wafer-size conversions for customers, upgrading fab lines from four- to six-inch wafer processing and from six- to eight-inch.

In terms of a Q4 uptick there are a number of standard pureplay semiconductor companies in Europe looking to place orders at the end of the year, but there has been keen interest in the MEMS market as well, not to mention power devices. “Right now we’re seeing quite a bit of interest in power applications,” McKie said, noting that European power device makers are seeing intense competition from Asian device makers at the moment.

Will used 300mm equipment represent strategic opportunities?
If the industry is on the edge of a current up-cycle, it also may precede interesting times in the next cycle, as the market for used 300mm equipment continues to develop. The market for refurbished 300mm tools is relatively small and new, compared to the used equipment market as a whole.

It’s also been busy, of late and will likely continue to be so. But refurbished 300mm tools are the sole province of first-tier IDMs and foundries, for the time being.

It’s no secret that capacity is tight at the leading edge and near-leading edge nodes, and yet companies need to shave costs wherever they can. This means demand for used 300mm tools at top-tier device makers—core systems that can be refitted or otherwise refurbished for other applications—has remained strong even as the market for used 200mm tools has been ghostly quiet for most of this year.

A primary example of this is financially beleaguered DRAM maker ProMOS’ sale of a 300mm fab in Taiwan earlier this year. Foundry giant GlobalFoundries snatched that up. “From what I’m seeing in their forecasts, GlobalFoundries is a major player,” said a FabSurplus sales executive. The foundry expects to buy some $150 million of 300mm tools and services in 2014, for both backend and frontend expansion in 300mm fab lines.

There just have not been any second tier chipmakers, be they IDMs or foundries, making a play or even expressing much interest in used 300mm tools—yet.

But what if there were? Could a second-tier chipmaker theoretically jump into a market dominated by first-tier players by upgrading a fabline with used 300mm equipment and consequently offer a cost-effective alternative product?

“If one of those second tier companies had decided to go after, say Promos facility … their cost of equipment capital would have been lower” than that of a company investing in a brand new fab line, said Gates. “We haven’t seen it happen, but that’s not to say it couldn’t. It’s really been the first-tier customers that have taken advantage of the 300mm equipment in the used equipment market,” he said, but noted that AG Semi has actually seen some tentative interest from second-tier customers.

Certainly it is a possible scenario for a European chipmaker. Memsstar’s McKie noted that European companies are well established and comfortable with manufacturing devices using refurbished 200mm tools; they would not be averse to adding 300mm capacity with used systems. The real issue is the availability of core manufacturing systems; as with Promos’ fab sale noted above, used 300mm tools tend to get bought up very quickly in today’s market.

So this scenario is highly unlikely in the current cycle—assuming that the industry is on the edge of an upturn. But it’s a distinct possibility in the next cycle. Perhaps with the low-power needs of the end market driving things such as finFETs in the front end and TSVs in the back end, there will be an opportunity for a second-tier player to jump into a market dominated by first-tier players as the 300mm market matures and more systems become available.

There is definitely interest on the packaging side for used 300mm tools, refurbished tool brokers report. Many 300mm packaging lines that utilize advanced technology will be moving from pilot lines into production in the next cycle. Could this be a strategic yet cost effective opportunity for a second-tier company?

It is speculation, to be sure, but one thing is certain: A growing market for 300mm tools will be a boon for used equipment providers. As markets mature, original equipment makers don’t always find it cost-effective to offer service and support for used equipment. This provides an opportunity not just to broker and sell used tools, but service and support for those tools as well. In terms of the 300mm market and the related manufacturing complexity found in the accompanying technology nodes, there likely will be a strong demand for refurbished and repurposed tools and accompanying support services in the next cycle.

“The used 300mm equipment market is really now just developing,” said Gates. “We’re really going to see it come into it’s own.”

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Serge Tedesco, lithography program manager at CEA-Leti; Laurent Pain, lithography lab manager at CEA-Leti; and Raluca Tiron, a senior scientist at CEA-Leti.

SMD: CEA-Leti has two major and separate programs, including one in directed self-assembly (DSA) and another in multi-beam e-beam. Let’s start with DSA. What is CEA-Leti doing in DSA?
Pain: For DSA, we have what we call the ‘Ideal’ program. We are developing 300mm processes. We have materials development with Arkema. Other partners include TEL and Sokudo. We are working with STMicroelectronics to transfer the technology from a process point of view. We are developing this capability for lab scaling to industry production.

SMD: What have you demonstrated with DSA?
Pain: We have demonstrated resolutions down to 18nm half-pitch, which is considered the 7nm logic node. We think we can extend PS-b-PMMA down to the 7nm node. The concept is to enable 7nm to 4nm resolutions with Arkema’s materials.

SMD: The big question is when do you think DSA will move into production?
Pain: From my point of view, it should be 10nm. You will start to see some demonstrations at 14nm.
Tedesco: You can ask me that in July. I still say 2014.

SMD: What are the challenges with DSA?
Pain: There will be some challenges in terms of defectivity and process maturity.
Tiron: For contact shrinks, the processes are here. It’s stable. That means you can absorb a lot of the variations with the block copolymers. But you don’t have pitch or density. If you move to contact doubling, you have the density. But you lose the process window stability. The placement of the contacts is also less certain. But what is important is now we have materials, processes and tracks. What we really need now is some real fabrication. The applications depend on the end-user. What we need is the end-users to tell us: ‘We need this and that and then move in that direction.’ That’s what is missing today.

SMD: What have you accomplished in your DSA process flow?
Tiron: We have implemented a process flow on a 300mm track, which comes from Sokudo. We have a complete DSA process cycle in one track. The track handles the brush coat and block copolymer coating. The track also has high temperature hot plates for block copolymer cure. We also worked with Sokudo to develop a PMMA removal process. We demonstrated different exposure treatments and solvents. What we are trying to do now is address contact hole shrinks and contact multiplication. With the polymers from Arkema, we are able to do resolutions from 20nm period, which means 10nm resolution, to 60nm period, which means 35nm resolution. Contact shrink is possible using both cylindrical and lamellar morphologies.

SMD: What about yield or defects?
Tiron: We have shown good uniformities with three sigma around 2nm. After the optimization of the process, we counted 6,800 divisional points on the wafer. We only found five missing contacts. By using block copolymers, we showed 99.93 % valid contacts on the wafer. This is just using PMMA.

SMD: Let’s move to multi-beam. What is CEA-Leti doing in multi-beam?
Pain: The second program is called Imagine. This program started last year. We have a partnership with (multi-beam e-beam vendor) Mapper Lithography. Other partners include Aselta, JSR, TOK, TSMC, Sokudo, Dow, STMicroelectronics, TEL and Mentor.

SMD: How far along is Mapper’s multi-beam tool?
Pain: The first machine will consist of 1,300 beams. The throughput is one wafer per hour. The tool will arrive the beginning of June. That’s targeted for the 14nm logic node. This machine will be interfaced with the Sokudo track. The first exposures will start in the last quarter of this year. Eventually, the target is to reach 16nm half-pitch. Our goal is to have 13,000 beams with the Mapper tool. We expect to scale the throughput from one wafer per hour to 10 wafers an hour. Then, we plan to push the resolutions down to 10nm half-pitch.

SMD: What is the cost-of-ownership for the Mapper tool?
Pain: The cost is 1 million euros for two wafers per hour. So in other words, that’s 5 million euros for 10 wafers per hour. Our eventual goal is to cluster 10 machines together. That’s 50 million euros for the cluster configuration.

SMD: Isn’t multi-beam taking longer than expected and behind schedule?
Pain: If you take the original roadmap, we are late. Some of the technical achievements have taken a long time.
Tedesco: One of the problems is there is a lack of support from the industry. It’s a shame that there is a lack of support, when you look at what’s being done on the EUV side. That’s one of the reasons that multi-beam is not mature yet. Of course, there is the technical aspect. TSMC, of course, is the one that is pushing this technology. But beyond TSMC, there is a lack of support. But I think the support will eventually come.

SMD: TSMC has stated it wants to do all layers with multi-beam. Is that practical or will multi-beam end up doing traditional direct-write applications like ASICs?
Tedesco: It could be a challenge to do all layers with multi-beam. But a maskless tool could be useful in terms of ASICs or prototyping. It’s ideal for the foundries. But the first applications for multi-beam will likely be contact holes and the cut layer.

SMD: How about STMicroelectronics? STMicroelectronics has been involved with direct-write for many years.
Tedesco: ST is a partner of Leti. So they are following Imagine very closely.

SMD: What about funding for multi-beam from the likes of Intel, GlobalFoundries and Samsung?
Tedesco: Good question. What we can say is that they are following us very closely. They know what we are doing. At this point, they are not part of the program.

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. This paper focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based.

To view this white paper, click here.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing for inspection systems and technology transfer at Ultratech. What follows are excerpts of that conversation.

SMD: From your vantage point, what are the challenges for lithography?
Allgair: Among the challenges are resolution and the interaction of the metrology with the resists we are trying to measure. Of course, the resist materials are getting thinner and thinner. And this creates its own set of challenges both from a resolution and an interaction point of view. Also, when moving to new materials, there is the measurement piece. As I mentioned before, we want more 2D and 3D information from the resists. In addition, we want to compare the resists versus what we did with the design. And we are trying to look for the defects. And with overlay, we are seeing challenges there, as well—everything from the sheer volume of the measurements we have to take, to the ability of the overlay targets to really predict what’s going on within the circuit itself. That frequently drives the need for more targets and with in-die targets. And that gets further complicated by the fact that your targets can be impacted by your processing, so you wind up having process interactions that are involved in the overlay target measurements. Somehow you need to take those interactions out to understand where your overlay is.
Heidrich: Litho is driving resolution, overlay and process effects. From each of those, from a CD point of view, we see OCD is the method of choice. Regardless of the techniques used, customers are dealing with measurements on more complex structures in a design. So the question is how many types of structures do you measure in production to track OPC corrections and other complex interactions, as well as additional complexity in the resist patterns themselves? You could end up seeing a double pattern litho resist or other type of litho resist. For overlay, there is a data explosion. The data is going up. At the same time, target size is going down.
Newcomb: Edge inspection is an area of interest. There is a need to combine your wafer inspection and edge inspection and do multi-analysis and multi-channel inspection. Regarding the resists, customers are seeing interactions, for example, in the CD-SEM and e-beam. This is making it difficult to make good and accurate measurements. In the past, it was all about beam alignment, emission and spot size in order to make a measurement for a via hole as one example. Now, in litho, that resist has a charge and creates an electric field that directly impacts the ability to make those critical measurements.
Shetty: As the device sizes are shrinking, the overlay budgets are shrinking. Right now, at 20nm and 16nm, the overlay budget is around 10nm or 8nm. But because of all the issues the customers are having, such as EUV implementation, customers are going with unique schemes like double patterning and triple patterning. What happens is that 10nm budget gets cut by half or one-third. So every part of the overlay budget gets impacted. There are three parts of the overlay budget. There is one that is coming from the overlay tool from the scanner. The second one is coming from the reticle. The third one is coming from the wafer itself. These are wafer-based distortions that the scanner can’t fix. Regarding the overlay tool, traditional tools like Archer and others measure the overlay. As the device sizes are shrinking, the targets are behaving more and more differently than the devices themselves. Customers are left with two choices. Either they can increase the number of targets on the wafer and then take a hit on throughput and have higher costs. Or, they can find a different way to measure these wafers. For example, by using limited targets on the wafer, they will not get all of the information they need for the scanner to fix the wafer.

SMD: What about finFETs?
Newcomb: 3D structures like finFETs not only require more metrology and inspection steps, but they involve a lot more complexity. You are not just looking at the information in the x, y, and z axis, but also at the atomic level of x, y and z. You are asking things like how does that device come together? What is the structure of that device? Does it meet the specs? We are starting to see some interesting interactions with existing process tools types, whether they are across the edge or wet cleaning. When you use existing technologies, and try to build 3D structures, you are getting defect signatures that we’ve never seen before from net Vdd perspective. You also have all of these defectivity models coming forward and you have to deal with them.
Allgair: Going to 3D has created numerous challenges for us. We see tenfold measurement problems as we go to 3D. A lot of things you see in 2D tend to get amplified as we go to these 3D structures. In an x, y and z matrix, you need to ask: ‘The atoms are there, but are they the ones you want? Are they electrically active or not?’ We are trying to use the same tooling that we currently have available. You will see the CD-SEM, OCD, and the overlay tools you are familiar with. With finFETs, we can do some things, such as CD, height, profile, spacer, and thickness. Some of these applications can be done using scatterometry or CD-SEM or a combination of that data set. Then, we see some real challenges when it comes to compositional analysis. In finFET devices, we’ve got compositional measurements like SiGe with a percentage of germanium and a percentage of boron on a 3D structure. That’s a very complex measurement. Finally, we try and do measurements on test structures. The test structures don’t always mimic what’s actually taking place on your device. That really adds to the complexity of trying to manufacture finFETs in a stable manner.

SMD: What are some of the issues with stacked 2.5D and 3D devices?
Newcomb: As we turn to the 3D packaging world, and we think about stacked memory or memory on logic, we have techniques like traditional optical inspection. Although it will be important for 3D packaging and 3D ICs, you have to be concerned about a whole new class of things like sub-monolayer metallic contamination within the device area. If these wafers need to be thin, and I need to expose the TSVs, I start seeing copper defectivity and sub-monolayer issues. Now, I am trying to stack multiple known-good die. As we package these known-good die in 3D structures, and if you have one mistake like sub-monolayer copper residue, that will make multiple known-good die no longer any good.
Heidrich: Plus, you hand off a known good wafer to someone and then you need to integrate it. In effect, you are doing double metrology and double inspection. And then in the process itself, there is a lot of complexity we address in terms of TSVs. Metrology and inspection for that whole flow must be addressed for cost, performance and reliability.
Allgair: If I look at the 3D TSV side, the idea of stacking structures has created a need for new tools. We have been looking at new techniques, which should work out reasonably well. We are making pretty good progress.

By Mark LaPedus
At last year’s SPIE Advanced Lithography conference, Christopher Bencher, a member of the technical staff at Applied Materials, said the buzz surrounding directed self-assembly (DSA) technology resembled the fervor generated at the famous Woodstock rock concert in 1969.

This was clearly evident from the tumultuous and free-flowing movement that threatened the status quo over the potential use of DSA, an alternative patterning technology that enables fine pitches through the use of block copolymers.

A year later, DSA has joined the lithography establishment. Amazingly, within a short time span, DSA has moved from a mere curiosity item into the R&D mode at GlobalFoundries, IBM, Intel, Samsung and TSMC. “Companies are taking DSA seriously,” said Bencher, a DSA expert. “If you compared it to last year, we are now in the pre-competitive stage with DSA. The people in DSA have all grown up and are now wearing suits and ties.”

For some time, most chipmakers have kept their DSA efforts shrouded in secrecy. At the recent SPIE event, however, chipmakers finally provided the first glimpse of their initial work and results.

Based on the early findings, DSA still has a way to go before it moves into IC production. Chipmakers are just getting their arms around the problems. And they are still experimenting with an assortment of fab tools, flows, chemistries and design methodologies.

Still, the initial findings are also promising, providing a clue to where DSA is heading. For example, using DSA, Intel demonstrated 28nm structures. Separately, GlobalFoundries devised 28nm fins with DSA. IBM developed a silicon-on-insulator (SOI) DSA flow. And Samsung may have found the path towards sub-20nm DRAMs.

It’s still unclear when DSA will reach production. The projections range from the 14nm to 7nm nodes. “If you ask different people, you will get different answers,” said Joy Cheng, a research staff member at IBM.

DSA: From the lab to the fab?
DSA is not a next-generation lithography (NGL) tool per se, but rather it is a complementary and double-patterning scheme. DSA is also disruptive and threatens the status quo, because the process isn’t dependent on traditional and costly lithography. Many of the key processing steps are conducted in an existing wafer track system.

There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

In theory, DSA is attractive because it could reduce the overall cost of lithography. And compared to EUV, DSA requires less R&D funding.

“We don’t need billions of dollars,” said Ralph Dammel, chief technology officer for AZ Electronic Materials, a supplier of materials for DSA and other applications. “Materials development is inherently cheaper than tool development. The current funding is probably adequate to get the industry going for the 14nm node with DSA. If we’re talking about high chi polymers, which will be needed for the 10nm node and beyond, the industry should think about different funding mechanisms. But even so, we are not talking about huge sums.”

Meanwhile, over the last year, Albany Nanotech, CEA-Leti and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations. “Basically, DSA is still in the R&D stage,” said Charles Pieczulewski, director of strategic marketing for Sokudo, a wafer track supplier. “The industry is still working through the bugs with the materials.”

Going forward, the challenge is to bring DSA into the IC design and production phases. “The main challenge is device integration,” said Ben Rathsack, strategic marketing and technology manager at Tokyo Electron Ltd., the world’s largest wafer track supplier.

Last year, Applied’s Bencher listed defectivity as the top challenge for DSA, followed in order by registration, design flexibility and positional accuracy. For 2013, positional accuracy—or the ability to align the block copolymers in the proper place—has moved to the biggest challenge for DSA, Bencher said.

Bencher expects memory makers will be the early adopters for DSA, followed by logic and foundry vendors. The prediction is based on the ability to generate IC designs using DSA. “You hear people saying: ‘We need a whole design ecosystem to enable DSA.’ That might be true for logic, but these are the last people that would implement DSA. This is because you need the most flexible designs in logic,” Bencher said. “Memory makers don’t really need that whole design ecosystem. They need maybe 1% of the EDA ecosystem, compared to the logic people.”

Currently, there are several design approaches for DSA. One idea is using 1D gridded arrays, but the problems are obvious. “Designers don’t want to be restricted to having contacts only on a grid or vias on a grid,” Bencher said.

Another concept is laying down a sea of holes or fins on a pattern. “In the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which ones you want to keep and which ones you want to get rid of. But the problem is that the aerial image can be very sloppy,” he said.

And in another approach, Stanford University is developing an arbitrary design methodology for DSA using an alphabet soup of characters. In this approach, positional accuracy with the contact holes is the biggest challenge.

Chipmakers tip DSA efforts
Design is just one of the many challenges facing silicon foundries with DSA. For example, GlobalFoundries has set up a DSA R&D line at Albany Nanotech. Using chemical epitaxy, the company demonstrated three-stack, 28nm silicon fin structures. It also is experimenting with a graphoepitaxy flow.

“The advantage for using chemical epitaxy is that there is no loss for aerial density,” said Richard Farrell, a principal engineer at GlobalFoundries. “The advantage in working with graphoepitaxy is that it involves a relatively simple process. Some of the challenges that we face for graphoepitaxy is the translation of the edge roughness into the DSA pattern itself. For line/space, we need temperatures above 200 degrees. This has additional constraints on the lithographic performance of the resists.”

Bringing up DSA in a fab is another issue. “First, we have to deal with fab-compatibility in DSA processing,” he said. “There are contamination issues. In pattern transfer, we need to think about balance reflectivity and the use of planarization.”

Despite the challenges, chipmakers are moving full speed ahead with DSA—and for good reason. For example, NAND flash vendors are pushing 193nm immersion and multi-patterning to the limits, but suppliers are in dire need of a new solution. “EUV lithography and double patterning are widely known (to handle) sub-20nm patterning,” said Jaewoo Nam, a lithography engineer at Samsung, at the recent SPIE conference. “But EUV has some limitations. The pattern resolution for EUV is 16nm only. The cost is huge. Double patterning is also very complicated.”

Using DSA, Samsung is exploring the possibility of developing DRAMs at 18nm. Samsung’s initial goal with DSA is to devise 20nm contact holes. In a DSA R&D line, the company has implemented a graphoepitaxy flow using block PS-b-PMMA materials. With a proprietary treatment process, Samsung has improved the CD distribution by 28%, Nam said.

Like Samsung, Intel also is bullish about DSA. “DSA sparks off a dozen different ideas,” said Sam Sivakumar, a fellow and director of lithography at Intel. The possible applications for DSA include contact holes, vias, and the back-end-of-the-line (BEOL) flow, he said.

Intel is conducting its DSA R&D at IMEC. Last year, IMEC set up a 300mm DSA R&D line, which consists of TEL’s track systems. Using the University of Wisconsin flow, Intel devised a three-layer, 28nm stack. The stack includes an interconnect, via and a metal 1 layer.

Intel started with staggered contact hole arrays on a grid at 50nm to 55nm. After the pattern transfer process, the holes were reduced to 26nm to 22nm, representing a 35% shrink. With a blended DSA formula from JSR, Intel obtained the targeted resolutions with good results, said Todd Younkin, a lithography materials researcher at Intel. However, the results were less conclusive with traditional block copolymers, which are provided by both AZ Electronic Materials and Dow.

Another R&D organization, CEA-Leti, last year set up a 300mm DSA pilot line, which uses Sokudo’s track systems. Using PS-b-PMMA from Arkema and a graphoepitaxy process flow, CEA-Leti achieved resolutions from 35nm to 10nm, said Raluca Tiron, a senior scientist at CEA-Leti. “We showed good uniformity with three sigma around 2nm,” she said. “After the optimization of the process, we counted 6,800 divisional points on the wafer. We only found five missing contacts.”

PS-b-PMMA is expected to hit the wall at 10nm, meaning the industry must develop next-generation high chi DSA materials. Others see it differently. “We think we can extend PS-b-PMMA down to the 7nm node,” said Laurent Pain, lithography lab manager at CEA-Leti.

Another player, IBM, is involved in several different DSA efforts. In one effort, IBM demonstrated a larger-pitch 42nm flow, which could one day enable the development of smaller chips based on SOI. In this experiment, IBM used both the Almaden and University of Wisconsin flows, which enabled 42nm and 28nm resolutions. “If we can do self-assembly at 42nm, we can do assembly at smaller pitches,” said Chi-Chun Liu, a research staff member at IBM.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss the trends in lithography with Mark Melliar-Smith, president and chief executive of Molecular Imprints Inc. (MII), a supplier of nanoimprint lithography tools.

SMD: How do you view the IC industry now?
Melliar-Smith: It’s truly incredible work that this industry continues to do. The industry will see its way for the next 10 years. But to some extent, there are storm clouds on the horizon. This incredible complexity eventually looks like it may get a little out of control. We have to see what happens.

SMD: What will drive the demand for ICs in the future?
Melliar-Smith: There is a never-ending demand for more complex capabilities coming from the consumer. For example, there is an increasing amount of memory that needs to be stored in the cloud or on a mobile system. In addition, there is an enormous demand for bandwidth.

SMD: Why are lithography costs soaring out of control?
Melliar-Smith: We are in an era of increasing complexity and cost. The complexity comes in two varieties. The first complexity comes in the restrictions placed on the designers. That makes the designs less efficient and more difficult. The other part of the complexity comes just from the fact that you are starting to do double patterning. There are more steps to do it all. The complexity, of course, always comes with increased costs.

SMD: So is lithography heading for a train wreck?
Melliar-Smith: If I take a larger view of lithography, I could charge lithography the extraneous costs, including the inefficiencies of designs. Now, you are getting to the point where the productivity is beginning to come off the tracks in terms of how many millions of transistors per dollar I get. It’s not a train wreck, but it’s more of a challenge to really get the same learning curves we had before.

SMD: Any comments on EUV?

Melliar-Smith: EUV is a very difficult technology. I admire the people and what they’ve been able to do. The challenges get exponentially more difficult every year it’s late.  It’s been so delayed now that the dimensions that people want to use it for are down to well below 20nm. And at that point, you have a tough problem. The number of photons is much less than what you have at 193nm. It’s like by a factor of 30 less. So you have these very energetic photons flying in and the chemical debris goes into different directions. So it is not easy to solve that problem at 15nm. You also worry about shot noise and line-edge roughness.

SMD: What is the progress of nanoimprint lithography?
Melliar-Smith: We are actually making good progress. Obviously, as you know, if you want to go in and turn over the existing litho technology in today’s fabs, then that’s probably the toughest challenge you could have. People are justifiably conservative. The reason why we are getting a lot of traction now is that the benefits are becoming very noticeable.

SMD: What are the benefits of nanoimprint?
Melliar-Smith: First of all, we have no wavelength imaging issues. So, we can do single imprints or single patterning down towards 10nm. Second, we have far fewer design rule restrictions. We are not in the position of giving a design rule book that is like a telephone book, with all of the things you can’t do. We also don’t use high-speed photo chemistry to image. If you are imaging on a wafer, you are shining this image down and must do some chemistry on a resist. But as you get to smaller and smaller features, the problem gets tougher. So you get shot noise and line-edge roughness problems. We don’t have any of this. We bring the potential for much lower cost.

SMD: What markets are you targeting in semiconductors?
Melliar-Smith: Our target for initial production would be the memory space, particularly flash. The resolution requirements are the most extreme.

SMD: Toshiba is one of your customers. Is Toshiba in NAND production using nanoimprint yet?

Melliar-Smith: No. They are not in production yet. You have to ask them what their plans are. But clearly, they see the potential for the technology. In the memory space, people don’t talk very much about what they are doing. It’s hard to get our customers to stand up and champion us publicly.

SMD: The knock on nanoimprint is defectivity, overlay and throughput. What’s the latest on that?

Melliar-Smith: The long pole in the tent has always been defectivity. In the last couple of years, we’ve made huge progress. We are now down to the point where we believe our defectivity is close enough, that there is significant consideration for production in memory using nanoimprint. The advantage in memory, of course, is that you have redundancy built into the device. So the acceptable defect level is much higher than it is in logic. We believe the defect issues, and the ability to make 1X masks, looks like they are well under way for a solution.

SMD: What are the other challenges?
Melliar-Smith: The only challenge we’ve got is to make these very high-resolution masks. At present, the electron-beam pattern generators that write our masks are resolution limited to about 25nm, which is not enough.

SMD: What are the solutions?

Melliar-Smith: There were a couple of papers from SPIE. One is from IMS, which is developing a multi-beam mask writer. IMS is going to bring out a 12nm beta tool in 2015. The other one is from DNP. They showed results using double patterning on the mask to imprint a mask. You do all of the expensive patterning on the master mask. And then you use the master to create a replicate mask. And then you use a replicate mask in the factory. The cost of the master mask is irrelevant in the cost-of-ownership. DNP showed 15nm master masks made by double patterning.

SMD: You are also targeting the 450mm market. You sold a 450mm nanoimprint tool to Intel, right?
Melliar-Smith: We had a 450mm tool, which was billed and accepted by a customer. The customer wants to accelerate the transition to 450mm. To do that, they’ve got to provide patterned wafers to companies like Lam, Applied and TEL.

SMD: MII also has been talking about the disk drive industry. Nanoimprint is targeted for the shift towards bit-patterned media. What’s the status on that?
Melliar-Smith: Given the dynamics of that industry like consolidation and other things, the (disk drive makers) have actually slowed their density roadmap down. So that opportunity for us has been pushed out a couple of years. It’s a matter of if and not when. Hitachi, Seagate and Western Digital all have programs with patterned media using nanoimprint.

SMD: What other markets are you looking at?

Melliar-Smith: Another area we are interested in is working with the polarizers in flat-panel displays. They use polarizers in front of the light source and after the switching matrix. Today, they use organic film polarizers. They’ve known for a long time that a so-called wide-grid polarizer is a better polarizer. That’s an aluminum film on the glass, which is etched into 15nm lines and spaces. It has better transmission. That solution plays to our strengths.

By Mark LaPedus
Amid ongoing delays and setbacks, extreme ultraviolet (EUV) lithography and multi-beam e-beam have both missed the 10nm logic node. So for the present, chipmakers must take the brute force route at 10nm by using 193nm immersion with multiple patterning.

Now, it’s time to hit the reset button. For the 7nm node, chipmakers currently are lining up the lithographic competition. As before, with perhaps a slightly different twist, the candidates are EUV, multi-beam and the old standby, 193nm immersion with multiple patterning.

The same candidates also are competing for next-generation DRAM and NAND production. Nanoimprint is vying for a spot in NAND. But another option, directed self-assembly (DSA), could change the entire landscape if chipmakers can bring the technology from the lab to the fab.

Based on the delays with EUV, chipmakers could end up using 193nm with multiple patterning at 7nm. But they also are shuddering at the thought, as the costs and complexities for multiple patterning are enormous.

At 7nm, IC makers would prefer to use EUV or maskless for the critical or cut layers. But after a series of ongoing delays with these next-generation lithography (NGL) candidates, lithographers clearly are frustrated and beginning to run out of patience. “I am not happy with the progress of EUV,” said Burn Lin, vice president of research and development at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). “I am also not happy with the progress of maskless, but it is making progress.”

Lin, considered the father of immersion lithography, is the industry’s biggest proponent for multi-beam e-beam. In addition, TSMC has installed an EUV scanner and recently invested in ASML to jumpstart technology. Intel and Samsung also have invested in ASML.

EUV or bust?
For now, chipmakers hope to put EUV in pilot production at the 10nm logic and next-generation memory nodes. At 7nm, EUV remains the leading NGL candidate, with maskless running a distant second. TSMC still has EUV and maskless running neck-and-neck, although both technologies could be used in production for different applications.

To date, the progress with EUV is mixed. ASML Holding’s production-worthy EUV scanner, the NXE:3300B, is ready to roll. The scanner has a numerical aperture (NA) of 0.33 and a resolution of 22nm (half-pitch). ASML plans to ship the first NXE:3300B in the second quarter of 2013, but the throughputs are far less than previously advertised.

The throughput issues are due to the source, which is being developed by Cymer. The development of the EUV source has been “more difficult than what we anticipated,” said David Brandt, senior director of EUV marketing and business development at Cymer, which recently was acquired by ASML.

Last year, Cymer promised to ship a 100 Watt source by the end of 2012. So far, in the lab, Cymer has demonstrated the ability to generate 40 Watts and 50 Watts of EUV power. A 55 Watt source translates to an EUV throughput of 43 wafers an hour.

Cymer’s EUV source is based on laser-produced plasma (LPP) technology. In LPP, plasma is generated by a laser pulse hitting a target. The source also makes use of a pre-pulse laser and a master-oscillator power amplifier (MOPA), which will help generate more EUV power.

By the end of 2013, Cymer hopes to ship an 80 Watt source with a MOPA upgrade, enabling an EUV throughput of 58 wafers per hour. By 2015, ASML hopes to ship an EUV scanner with a 250 Watt source, which translates to a throughput of 126 wafers an hour.

Two other vendors, Gigaphoton and Xtreme, are racing against Cymer to deliver a 250 Watt EUV source. So far, Gigaphoton has achieved an EUV light output equivalent to a maximum of 20 Watts, said Yuji Minegishi, manager of the sales division for the company.

By 2015 or so, the IC industry is expected to be at the 10nm node. EUV is a 13.5nm wavelength technology, meaning chipmakers must use multiple pattering with EUV. With self-aligned double patterning (SADP), ASML’s NXE:3300B has demonstrated resolutions down to 9nm.

But if EUV is used in conjunction with double patterning, the EUV scanner itself will require twice the source power than before—or about 500 Watts, contends TSMC’s Lin. However, to deal with the resists, Yan Borodovsky, a senior fellow and director of advanced lithography at Intel, recently said that EUV source power needs to be in the range of 1,000 Watts.

Another way to extend EUV is by moving to higher NAs. For example, with an NA of 0.45, an EUV scanner can print 9.5nm feature sizes, but the image contrast drops, according to Zeiss. To address that problem, the current 4X magnification scheme can be increased to 6X or 8X.

Current EUV scanners with 4X magnification support standard 6-inch photomasks. A 0.45 NA lens with 6X magnification may improve EUV resolutions, but in some cases, that solution may require the photomask industry to move to a new and larger 9-inch mask size. In other words, photomask tool makers must develop new equipment.

“I don’t think we should give up on 4X just yet,” said Harry Levinson, senior fellow and manager of strategic lithography technology at GlobalFoundries, at the recent SPIE conference. “We may be able to extend 4X a bit. Maybe for a later node, we can go for more of these radical changes, such as larger format masks and higher lens reductions.”

Still, Levinson urged the industry to explore the idea of moving toward 9-inch masks, a move that is less painful than some might think. To support 9-inch reticles, the optics and other critical parts of a photomask tool will not need to be re-engineered, but vendors will need to develop new handling systems, he said.

In another scenario, EUV with 8X magnification could support 6-inch masks, but scanning would be done in a smaller field size. “You put this all together and we get less than half the throughput at 8X than 4X,” he said. “This is not an attractive situation.”

Beam me up
Amazingly, multi-beam e-beam or maskless lithography has seen more delays than EUV. Summarizing the state of multi-beam, Serge Tedesco, lithography program manager at CEA-Leti, said: “It’s a shame. There is a lack of support from the industry, when you compare it to the EUV side. This is one of the reasons why the technology is not mature yet.”

In 2002, for example, Mapper Lithography claimed that within three years it would ship its 13,000-beam tool for the 45nm node. As it turned out, Mapper’s initial production tool, which only will consist of 1,300 beams, won’t ship until the end of 2013.

Two other vendors, KLA-Tencor and Multibeam, are separately developing multi-beam tools. In another major move, Golden Gate Capital, a venture capital firm, recently sold its e-beam company, Vistec, to two different companies.

In one transaction, Raith recently acquired Vistec’s Gaussian e-beam unit, called Vistec Lithography. Vistec Lithography continues to specialize in conventional direct-write applications in the aerospace and military arena.

In a separate move, the Heidenhain Group recently acquired Vistec’s variable shaped beam (VSB) e-beam unit. That operation, Vistec Electron Beam, sells a single-beam e-beam tool based on VSB technology. It also is working on a multi-beam tool based on a variant of VSB called multi-shape beam (MSB), said Ines Stolberg, manager of strategic marketing at Vistec Electron Beam.

Given that MSB is based on proven VSB technology, Vistec Electron Beam may have an advantage over rival multi-beam approaches, said Hans Pfeiffer, principal of HCP Consulting. “This has a greater chance for success,” Pfeiffer said.

Multi-beam’s future still remains unclear, as only two entities, CEA-Leti and TSMC, are basically propping up and supporting the entire industry. CEA-Leti recently launched the Imagine Program, a multinational consortium aimed to bring maskless into production.

TSMC is working with both KLA-Tencor and Mapper. For years, KLA-Tencor has been developing what it calls Reflective Electron Beam Lithography (REBL). REBL makes use of a six-wafer rotary stage and a linear column. The 75-100-KeV design also consists of a CMOS-based digital pattern generator module, a 4,096 x 247 pixel array unit that enables more than 1 million beams at full current.

When operating with the rotary stage, REBL has demonstrated the ability to print 120nm half-pitch resolutions, a modest effort at best. In a static mode, the tool demonstrated 28nm resolutions, said Thomas Gubiotti of KLA-Tencor. A high-throughput version of REBL is due out in 2015.

Rival Mapper is developing a multi-beam tool, which is supposed to consist of 13,260 beams with sub-25nm resolutions. However, the first production tool, dubbed the Matrix 1.1, will consist of only 1,300 beams and a throughput of 1 wafer an hour, according to CEA-Leti. In June, CEA-Leti is expected to receive one of the first Matrix 1.1 tools. First exposures for the Matrix 1.1 are slated for the fourth quarter of 2013.

By 2015 or 2016, the overall goal is to cluster 10 Matrix systems together, enabling an overall throughput of 100 wafers an hour. In terms of the cost-of-ownership (COO), the Matrix runs €1 million for a system with a throughput of 2 wafers per hours, €5 million for 10 wafers an hour, and $50 million euros for a 10-cluster unit.

Computational lithography has become an integral part of design since the 130 nm process node. New techniques continue to be developed to extend the steady node shrink year after year.

To read this white paper, click here.

Probing Lithography
The Imperial College London and Ilmenau University of Technology have made some advances in the development of scanning probe lithography. Claiming resolutions down to 5nm and beyond, the technology combines the best of high-resolution scanning probe and nanoimprint lithography.

Sometimes called dip pen lithography, scanning probe lithography utilizes the same nanoprobe used in an atomic force microscope (AFM). The AFM is used to pattern nanometer-scale features. The AFM also enables the direct write of features into calixarene molecular resist. Then, researchers use a confined, development-less resist removal process via emission of low-energy electrons. An AFM post-imaging process is used for final in-situ inspection.

Researchers demonstrated a tiny pattern written in 10nm 4M1AC6 resists, with 40V bias voltage and 30nC/cm line dose. With the technology, scanning probe lithography could be a candidate for the production of finFETs with silicon nanowires at 10nm resolutions.

Figure 1. (a) Development-less, positive-tone closed-loop scanning probe lithography (SPL) on calixarene-based molecular glass resist, using self-actuating, piezoresistive scanning probes. (b) Scanning electron microscopy image of a corner pattern written in 10nm-thick 4M1AC6 resist, with 40V bias voltage and 30nC/cm line dose.4(c) Atomic force microscopy image of lithographic test features written with 30V bias voltage and a line dose of 32nC/cm (broad lines) and 20nC/cm (small lines), respectively. The image was taken directly after lithography with the same cantilever. Source: SPIE

Researchers also see applications in the development of quantum-effect devices, such as single-electron transistors and quantum-dot structures. Using a combination of lithography and material morphology, researchers have fabricated room-temperature single-electron transistors using e-beams and silicon nanocrystals at about 10nm in size.

DSA Hard Drives
Sputtering has been one of the main techniques to enable magnetic media on today’s hard disk drives. The next round of high-capacity drives could be based on an entirely new technology, including bit-patterned media (BPM) or heat-assisted magnetic recording (HAMR).

HGST, formerly Hitachi Global Storage Technologies, continues to explore the development of BPM. Now owned by Western Digital, HGST has combined directed self-assembly (DSA) and nanoimprint lithography to create large areas of dense patterns of magnetic islands at 10nm widths. In partnership with Molecular Imprints, a nanoimprint lithography vendor, HGST has devised dense patterns of magnetic islands in about 100,000 circular tracks.

Self-assembling molecules, called block copolymers, are composed of segments that repel each other. In self-assembly, a pre-pattern or guide is developed. After polymer patterns are created, a process called line doubling is implemented. This makes the tiny features even smaller, creating two separate lines where one existed before.

The patterns are then converted into templates for nanoimprinting. HGST has combined self-assembling molecules, line doubling and nanoimprinting to make rectangular features as small as 10nm in a circular arrangement. When extended to an entire disk, the nanoimprinting process is expected to create more than 1 trillion discrete magnetic islands.

“We made our ultra-small features without using any conventional photolithography,” said Tom Albrecht, an HGST fellow, on the company’s Web site. “With the proper chemistry and surface preparations, we believe this work is extendible to ever-smaller dimensions.”

Pellicle Island
For years, photomask makers have used a pellicle to protect a mask from particle contamination. Used in the production of today’s photomasks in optical lithography, a pellicle is a thin film material that is stretched on a frame.

One of the problems with extreme ultraviolet (EUV) lithography is that the technology lacks a pellicle. This means that particles could invade an EUV mask, thereby disrupting the photomask flow and threatening the overall viability of EUV. In fact, EUV generally requires a defect-free mask to enable the technology.

To solve the problem, ASML Holding has begun the development of pellicles for EUV masks. There are two possible types of pellicles for EUV masks—grid-supported and free standing. ASML is focusing on the free-standing approach, which itself consists of two materials options—polysilicon and a silicon/molybdenum/niobium multilayer. See slide 26 here.

To make the technology viable, an EUV pellicle must have a transmission rate at 90%. At present, ASML has achieved a transmission rate at 87%. In a simulated test, the pellicle was subjected to a 250 Watt source. “The results are promising,” said Luigi Scaccabarozzi, a research scientist at ASML “There was no damage to the (EUV scanner).”

—Mark LaPedus

By Mark LaPedus
It’s the worst-kept secret in the industry. Extreme ultraviolet (EUV) lithography has missed the initial stages of the 10nm logic and 1xnm NAND flash nodes.

Chipmakers hope to insert EUV by the latter stages of 10nm or by 7nm, but vendors are not counting on EUV in the near term and are preparing their back-up plans. Barring a breakthrough with EUV or other technology, IC makers will likely use today’s 193nm immersion with multiple patterning at 14nm, 10nm and perhaps beyond. “10nm will be optical,” said Ajit Manocha, chief executive of GlobalFoundries. “We have evidence that we can do 7nm with immersion.”

GlobalFoundries, for one, is laying the groundwork if EUV is ready by 10nm. “We are keeping our ground rules migrate-able to EUV,” added Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries.

Chipmakers are keeping their options open for good reason—extending optical comes with a penalty. The shift from single patterning at 28nm to multiple patterning at 20nm is projected to increase lithography costs by up to 56%, according to Barclays Capital. Consequently, the overall cost-per-transistor curve is in danger of slowing or derailing.

Lithographers, who seem to achieve miracles when the chips are down, are determined to stay on Moore’s Law. “The cost of processing might go up with multiple patterning, but cost-per-transistor does not,” said Yan Borodovsky, a senior fellow and director of advanced lithography at Intel.

The ability to stay on the critical cost-per-transistor curve puts enormous pressure on the lithographic supply chain, which includes the EDA houses, materials suppliers, mask shops, and tool vendors. In response, Nikon is quietly shipping a faster scanner for 10nm. Lithographers also may resort to some new patterning tricks. The wild card is directed self-assembly (DSA), an alternative lithography technology that makes use of block copolymers to enable fine pitches.

EUV woes
For years, there have been fears that optical lithography would run out of gas, prompting the need for a new next-generation lithography (NGL). EUV emerged as the leading NGL candidate. The other NGLs, maskless and nanoimprint, are also in the hunt.

EUV, a soft X-ray using 13.5nm technology, is attractive because it keeps the industry on a single-exposure path. But EUV has encountered several delays due to the lack of adequate power sources, defect-free photomasks and photoresists.

The current throughput for ASML’s EUV tools is less than 10 wafers an hour (wph). At one time, ASML hoped to ship an EUV scanner with a 150-watt source by mid-2012. A 150-watt source equates to a more acceptable throughput of 69 wph.

Recently, the 150-watt source was delayed again and pushed out to mid-2014. The source is being developed by Cymer, which itself is being acquired by ASML. Separately, Intel, Samsung and TSMC have recently invested in ASML to help fund ASML’s efforts in EUV and 450mm.

ASML is still targeting EUV for mass production in 2014, but the industry isn’t taking any chances and will extend 193nm immersion—at a price. On average, there are 37 lithography layers processed for 32nm/28nm chips, according to Barclays. Of those, there are 14 critical layers processed using 193nm immersion scanners.

In total, there are 38 lithography exposures at 32nm/28nm, 15 of which are immersion exposures, with only one multiple patterning step in the flow, according to Barclays. In terms of lithography equipment costs at 32nm/28nm, a foundry spends an estimated $17 million per 1,000 wafer starts per month (wspm).

In comparison, there are 40 lithography layers for at 22nm/20nm chips, 19 of which are critical layers. In total, there are 52 lithography exposures at 22nm/20nm, 31 of which are immersion exposures with 11 multiple patterning steps. All told, a foundry is expected to spend $27 million per 1,000 wspm in lithography costs, according to the firm.

Lithography steps and costs will soar at 14nm and beyond. In response, chipmakers already are prepared for the dreaded multiple patterning era. NAND flash vendors, for example, are using a multiple patterning technique called sidewall image transfer (SIT), sometimes called self-aligned double patterning.

In logic, vendors have or will implement one of the various flavors of multiple patterning: SIT, litho-etch-litho-etch (LELE) or self-aligned vias. Intel, for one, is embracing a concept called complementary lithography, which involves an SIT flow. Other logic vendors are following a similar path with various nuances.

Today, Intel is using 193nm immersion with multiple patterning at 22nm, with plans to extend that to 14nm. At 22nm, Intel’s processors are based on finFETs. “For the 22nm node, our fin is finer than what can be done with simple patterning. It’s done with pitch division. We still stay on an historical cost-per-transistor trend,” said Intel’s Borodovsky. “Our 14nm technology is also pitch-divided technology. We project our cost-per-transistor will remain on the trend.”

For 11nm, Intel is looking at quintuple exposure. As part of the process, there are two steps, gratings and line cuts, to pattern designs. Using 193nm immersion, the first exposure is used to make the gratings. The remaining four exposures are used to cut the pitch-divided lines.

To perform the cut step, Intel is evaluating several options: 193nm immersion; DSA, EUV; or direct-write e-beam. So far, there is no clear winner—193nm immersion is challenging, but DSA, EUV and maskless are not ready for mass production.

“I believe we can extend (193nm immersion) for many years,” Borodovsky said. “We also have a dual wave lithography roadmap. It means we will extend existing technology as long as possible. And we will bring in new technology when it is available and affordable.”

Using NGL has some advantages over optical. “If we use EUV, we will use one mask to do the gratings and another mask to break those continuities. If we use direct write, we don’t use any masks,” he said.

Another technology, DSA, potentially could extend 193nm lithography beyond 10nm. As before, the challenges for DSA are defects and the lack of a design infrastructure. The new gap for DSA is non-destructive metrology as a means to inspect the morphologies in the patterns.

DSA materials providers have said DSA would be ready at 10nm, but there are signs the technology may get pushed out. For example, IBM is targeting DSA for 7nm, said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM.

“DSA is making progress,” said Intel’s Borodovsky. “But let’s say we use DSA. If you look at a SEM, you look at the top. Everything may appear perfect. But the cylinders could also change their shapes from top to bottom. You have to have a cross section. So, it’s very difficult to do a cross section of 15nm holes or cylinders. You can do complicated X-ray metrology. For this, you need a synchrotron source, which is not practical.”

Etch is another roadblock. Some of the cylinder morphologies in DSA structures are uniform while others are not. “Some would etch to the bottom. You might also have cylinders that are etched in the wrong place. That’s an edge-placement error,” he added.

The solutions
Until NGL is ready, chipmakers are stuck. “I don’t think the industry has given up on EUV. EUV will be in play, but it will be in limited use,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “But for 10nm, almost all logic vendors are looking at immersion technology. Customers are even looking at extending immersion beyond 10nm.”

To keep up with the increase in multiple patterning steps, ASML and Nikon are shipping faster scanners. Nikon, for one, has begun shipping the NSR-622D, a 193nm immersion scanner for the 10nm node. The tool has a throughput of 200 wph. In addition, Nikon is also developing a separate 193nm immersion tool for the 450mm wafer size.

Besides lithography scanners, there is an urgent need for new and faster e-beams in photomask production. Mask making itself is quickly turning into a fine and precise art. In quadruple patterning, for example, the patterns must be split into four masks.

“One mask has to be perfect in terms of CD uniformity, linearity and defects. The other three masks have to be exactly the same,” said Amitabh Sabharwal, general manager for mask etch products at Applied Materials. “When you start going down to the 16nm node, the CD uniformity targets become very, very tight. We’re talking in the range of 1nm. And on top of that, the defect levels might be very tight. Your systematic uniformity has to be zero. Essentially, everything must be flat.”

Looking into his crystal ball, lithography expert Chris Mack predicts that the industry will embrace new design methodologies such as 1D layouts. “We will see more interaction between lithography and design,” Mack said. “The reality of what we can accomplish lithographically will have more influence on the way designs are implemented. In fact, this might not be a bad thing. The switch from arbitrary designs to more (1D-like layouts) is turning out to have less impact on chip area than many people expected. And they are lithographically friendly.”

The industry also will embrace complementary lithography or hybrid approaches. “There is no doubt in my mind that optical will go forever,” he said. “But I do think there is a possibility of hybrid lithographic approaches that are optimized for specific types of patterns. Complementary lithography is a powerful technique and makes the most sense. All of the (NGLs) have a lot of potential, but they are not being developed in the timeline the industry needs.”