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Logic Densities Advance at IEDM 2017

Monday, December 18th, 2017

By Dave Lammers

The 63rd International Electron Devices Meeting brought an optimistic slant to transistor density scaling. While some critics have declared the death of Moore’s Law, there was little evidence of that — on the density front at least — at the IEDM, held Dec. 2-6 in San Francisco.

And an Intel engineering manager gave a presentation at IEDM that took a somewhat optimistic view of EUV lithography readiness, auguring further patterning improvements, starting with contacts and vias.

GlobalFoundries, which is skipping the 10nm node, presented its 7nm logic technology, expects to move into manufacturing in mid-2018. John Pellerin, vice president of global R&D, said the foundry has worked closely with its two lead customers, AMD and IBM, to define a high-performance-computing 7nm logic technology that achieves a 2.8X improvement of routed logic density compared with its 14nm technology.

Pellerin said the current 7nm process of record (POR) delivers “the right mix of performance, power, and area (PPA),” adding that GlobalFoundries plans to bring in EUV patterning at an undefined later point in the 7+ generation for further improvements.

Contact Over Active Gate

Chris Auth, director of advanced transistor development at Intel Corp., described a 10nm logic technology that sharply increased the transistor density compared with the 14nm generation, partly due to a contact-over-active-gate (COAG) architecture. The 10nm ring oscillator performance was improved by 20 percent compared with the comparable 14nm test vehicle.

Chris Auth, who presented Intel’s 10nm technology paper at IEDM, was surrounded by questioners following the presentation.

Auth said the COAG approach was a key contributor to Intel’s ability to increase its transistor density by 2.7 times over the company’s previous generation, to 100 million transistors per square millimeter of silicon. While the traditional approach puts the contact via over the isolation area, COAG places the contact via directly over the gate. Auth said the approach does require a second etch stop layer and other process complexities, but contributes “a sizable 10 percent reduction in area.” Elimination of the dummy gate for cell boundary isolation, and the use of cobalt at three layers (see related story), also contributed.

While there has been much hand wringing in the industry over the costs involved with multi-level patterning, Auth didn’t appear phased by it. Intel used a self-aligned quad patterning (SAQP) scheme to create fins with a tight pitch. The SAQP approach required two sacrificial layers, with lithography defining the first large pattern and four additional steps to remove the spacers and create the final lines and spaces.

The Intel 10nm fins are 46nm in height.

The SAQP approach starts by exposing a 130nm line, depositing the two spacers, halving the pattern to 68nm, and again to 34nm. “It is a grating and cut process similar to what we showed at 22nm, except it is SAQP instead of SADP,” using patterning to form a grating of fins, and cutting the ends of the fins with a cut mask.

“There were no additional lithography steps required. The result was fins that are tighter, straighter, and taller, with better drive current and matching” than Intel’s 14nm-generation fins, he said. Intel continued to use self-aligned double patterning (SADP) for M 2-5, and for gate patterning.

GlobalFoundries — which has been in production for 18 months with the 14nm process used by AMD, IBM, and others — plans to ramp its 7nm logic generation starting in mid-2018. The 7nm high-density SRAM cell measures .0269 um2, slightly smaller than TSMC’s published 7nm cell, while Intel reported a .0312 um2 cell size for its 10nm process.

Intel argues that the traditional way of calculating density improvements needs to be replaced with a metric that combines NAND and scan flip-flop densities. (Source: Intel)

GlobalFoundries chief technology officer Gary Patton said, “all of us are in the same zip code” when it comes to SRAM density. What is increasingly important is how the standard cells are designed to minimize the track height and thereby deliver the best logic cell technology to designers, Patton said.

EUV Availability Needs Improvements

Britt Turkot, senior principal engineer at Intel, discussed the readiness of EUV lithography at an IEDM session, giving a cautiously bullish report. With any multi-patterning solution for leading-edge silicon, including etch and CMP steps, placement error is the biggest challenge. With quad patterning, Turkot said multiple masks are involved, creating “compounded alignment errors.”

EUV has its own challenges, including significant secondary ions from the EUV photons. The key challenge for much of the decade, source power, seems to be partially resolved. “We are confident that the 250 Watts of source power needed for volume manufacturing will be ready once the field tools are upgraded,” she said.

Pellicles may be another challenge, with ASML expected to have a polysilicon-based pellicle ready in time for EUV production. However, she said a polysilicon membrane “does give quite a hit to the transmissivity” of the mask. “The transmissivity impact is quite significant,” she acknowledged during the Q&A period following her talk.

Intel has succeeded in repairing some mask defects, Turkot said, and implements pattern shifting so that other defects do not impinge on the patterned wafer.

Asked by a member of the audience about EUV availability or up-time, Turkot said “one day, availability can be great,” and less than good on other days, with “long unscheduled downs.” Intel is predicting 88 percent availability next year, she said in response to a question.

Pellicle Needed for Wiring Layers

Scotten Jones, president of semiconductor cost consultancy IC Knowledge (Boston), said companies may be able to get by without a pellicle for EUV patterning of contacts and via layers late next year. However, a pellicle will be needed for patterning the lower-level wiring layers, absorbing 10-15 percent of the photons and impacting EUV patterning throughput accordingly.

“Companies can do the contacts and vias without a pellicle, but doing the metal layers will required a pellicle and that means that a ton of work still needs to be done. And then at 5nm, the dose you need for the resist goes up dramatically,” Jones said, adding that while it will take some time for ASML to roll out the 250 W source, “they should be able to do it.”

GlobalFoundries will take possession of its second EUV scanner in December 2017, while Intel is believed to own four EUV systems.

Pellerin said GlobalFoundries defined the ground rules for its 7nm process so that the foundry can do a phased implementation of EUV without causing its customers “design discontinuity, bringing a benefit to design costs.”

John Pellerin, v.p. of R&D, said GlobalFoundries plans a phased implementation of EUV without “design discontinuity.”

The foundry will first do the hole levels and then move into the tight-pitch metal levels as mask defectivity improves. “The mask ecosystem needs to evolve,” Pellerin said.

Cost-per-Function on Track

In a keynote speech at IEDM, Lisa Su, the CEO of Advanced Micro Devices, said over the last 10 years the semiconductor industry has succeeded in doubling transistor density every 2-2.4 years. But she said the performance gains have been much smaller. “We are making progress, but it is taking a tremendous amount of work,” said Su, who received a best paper award at the IEDM 25 years earlier.

About 40 percent of the CPU performance improvement now comes from pure process technology, Su said, while the remainder comes from better microarchitectures, power management, and integration of system components such as an on-chip memory controller. While instructions per cycle are increasing at a 7 percent annual clip, Su said “the tricks have run out.”

Overall, the leading semiconductor companies seem to continue to make progress on transistor density. And costs per transistor may also be on track. Kaizad Mistry, co-director of logic technology development at Intel, contends that with its Intel’s 10nm process Intel’s per-transistor costs are actually better than the historical  curve.

Jones said the IC Knowledge cost analysis of TSMC’s processes indicates TSMC also is hewing to historical improvements on the per-transistor cost front. However, the foundries are catching up to Intel.

Intel Cadence Lagging

“What really strikes me is that Intel brought out its 45nm process in 2007, 32nm in 2009, and 22nm in 2011, but then it took three years to do 14nm. We are about to be in the year 2018, and Intel still doesn’t have its 10nm process done. It is a very nice process, but it is not out yet, and TSMC’s 7nm process is ramping right now. By the time Intel gets to 7nm, the foundries may be at 3nm. GlobalFoundries skipped a generation but is ramping its 7nm next year. All will have processes competitive to Intel at the same time, or even earlier,” Jones said.

While foundries such as GlobalFoundries, Samsung, and TSMC may be able to quickly offer advanced logic platforms, the wider semiconductor industry faces design cost challenges, Jones said. “Yes, the cost-per-transistor is going down, and that’s nice, but the cost of a design with finFETs is in the 100-million-dollar range. Intel can do it, but many smaller companies can’t afford to design with FinFETs.”

That is why both GlobalFoundries and Samsung are offering FD-SOI based platforms that use planar transistors, reducing design costs.

“The Internet of Things market is going to be nine million things, at relatively low volumes. IoT companies are finding it hard to justify the cost of a FinFET design, but with the cheaper design costs, SOI gives them an economical path,” Jones said.

Deep Learning Joins Process Control Arsenal

Friday, December 8th, 2017

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By David Lammers

At the 2017 Advanced Process Control (APC 2017) conference, several companies presented implementations of deep learning to find transistor defects, align lithography steps, and apply predictive maintenance.

The application of neural networks to semiconductor manufacturing was a much-discussed trend at the 2017 APC meeting in Austin, starting out with a keynote speech by Howard Witham, Texas operations manager for Qorvo Inc. Witham said artificial intelligence has brought human beings to “a point in history, for our industry and the world in general, that is more revolutionary than a small, evolutionary step.”

People in the semiconductor industry “need to take what’s out there and figure out how to apply it to your own problems, to figure out where does the machine win, and where does the brain still win?” Witham said.

At Seagate Technology, a small team of engineers stitched together largely packaged or open source software running on a conventional CPU to create a convolution neural network (CNN)-based tool to find low-level device defects.

In an APC paper entitled Automated Wafer Image Review using Deep Learning, Sharath Kumar Dhamodaran, an engineer/data scientist based at Seagate’s Bloomington, Minn. facility, said wafers go through several conventional visual inspection steps to identify and classify defects coming from the core manufacturing process. The low-level defects can be identified by the human eye but are prone to misclassification due to the manual nature of the inspections.

Each node in a convolutional layer takes a linear combination of the inputs from nodes in the previous layer, and then applies a nonlinearity to generate an output and pass it to nodes in the next layer. Source: Seagate

“Some special types of low-level defects can occur anywhere in the device. While we do have visual inspections, mis-classifications are very common. By using deep learning, we can solve this issue, achieve higher levels of confidence, and lower mis-classification rates,” he said.

CNNs, Hadoop, and Apache

The deep learning system worked well but required a fairly extensive training cycle, based on a continuously evolving set of training images. The images were replicated from an image server into an Apache HBASE table on a Hadoop cluster. The HBASE table was updated every time images were added to the image server.

To improve the neural network training steps, the team artificially created zoomed-in copies of the same image to enlarge the size of the training set. This image augmentation, which came as part of a software package, was used so that the model did not see the same image twice, he said.

“Our goal was to demonstrate the power of our models, so we did no feature engineering and only minimal pre-processing,” Dhamodaran said.

A Convolution Neural Network (CNN)

Neural networks are trained with many processing layers, which is where the term deep learning comes from. The CNN’s processing layers are sensitive to different features, such as edges, color, and other attributes. This heterogeneity “is exploited to construct sophisticated architectures in which the neurons and layers are connected, and plays a primary role in determining the network’s ability to produce meaningful results,” he said.

The model was trained initially with about 7,000 images over slightly less than six hours on a conventional CPU. “If training the model had been done on a high-performance GPU, it would have taken less than a minute for several thousand images,” Dhamodaran said.

The team used commercially available software, writing code in Python and using Ubuntu, Tensorflow, Keras and other data science packages.

After the deep learning system was put into use, the rate of false negatives on incoming images was excellent. Dhamodaran said the defect classification process was much better than the manual system, with 95 percent of defects correctly classified and the remaining five percent mis-classifications. With the manual system, images were correctly classified only 60 percent of the time.

“None of the conventional machine learning models could do what deep learning could do. But deep learning has its own limitations. Since it is a neural network it is a black box. Process engineers in a manufacturing setting would like to know ‘How does this classification happen?’ That is quite challenging.”

The team created a dashboard so that when an unseen defect occurs the system can incorporate feedback from the operator, feedback which can be incorporated in the next training cycle, or used to create the training set for different processes.

The project involved fewer than six people, and took about six months to put all the pieces together. The team deployed the system on a workstation in the fab, achieving better-than-acceptable decision latency during production.

While Dhamodaran said future implementations of deep learning can be developed in a shorter time, building on what the team learned in the first implementation. He declined to detail the number of features that the initial system dealt with.

Seagate engineer Tri Nguyen, a co-author, said future work involves deploying the deep learning system to more inspection steps. “This system doesn’t do anything but image processing, and the classification is good or bad. But even with blurry images, the system can achieve a high level of confidence. It frees up time and allow operators to do some root cause analysis,” Nguyen said.

Seagate engineers Tri Nguyen and Sharath Kuman Dhamodaran developed a deep learning tool for wafer inspection that sharply reduced mis-classifications.

Python, Keras, TensorFlow

Jim Redman, president of consultancy Ergo Tech (Santa Fe, N.M.), presented deep learning work done with a semiconductor manufacturer to automate lithography alignment. Redman was unabashedly positive about the potential of neural networks for chip manufacturing applications. The movement toward deep learning, he said, “really started” from the date — 9 November 2015 – when the TensorFlow software, developed within the Google Brain group, was released under an Apache 2.0 open source license.

Other tools have further eased the development of deep learning applications, Redman added, including Keras, a high-level neural network API, written in Python and capable of running on top of TensorFlow, for enabling fast experimentation.

In just the last year or so, the application of neural networks in the chip industry has made “huge advances,” Redman said, arguing that deep learning is “a wave that is coming. It is a transformative technology that will have a transformative effect on the semiconductor industry.”

In image processing and analysis, what is difficult to do with conventional techniques often can be handled more easily by neural networks. “The beauty of neural networks is that you can take training sets and teach the model something by feeding in known data. You train the model with data points, and then you feed in unknown data.”

While Redman’s work involved lithography alignment, he said “there is no reason the same learning shouldn’t apply to etch tools or electroplaters. It is the basically the same model.”

Less Code, Lower Costs

Complex FDC modeling can involve Ph.ds with domain expertise, while deep learning can involve models with “30-40 lines of Python code,” he said, noting that the “minimal number of lines of code translates to lower costs.”

Humans, including engineers, are not adapted to look for small details in hundreds or thousands of metrology images or SPC charts. “Humans don’t do that well. Engineers still see what they want to see. We should let computers do that. When it comes to wafer analysis and log files, it is getting too complex (for human analysis). The question now is: Can we leverage these advances in machine learning to solve our problems?”

After training a model to detect distortions for a particular stepper, based on just 35 lines of Python code, Redman said the model provided “an extremely good match between the predicted values and the actual values. We have a model that lines up exactly. It is so good it is almost obscene.”

Redman said similar models could be applied to make sure etchers or electroplating machines were performing to expectations. And he said models can be continuously trained, using incoming flows of data to improve the model itself, rather than thinking of training as distinct from the application of the system.

“Most people talk about the training phase, but in fact we can train continuously. We run data through a model, and we can feed that back into the model, using the new data to continuously train,” he said.

Machine Learning for Predictive Maintenance

Benjamin Menz, of Bosch Rexroth (Lohr am Main, Germany), addressed the challenge of how to apply machine learning to predictive maintenance.

To monitor a machine’s vibration, temperature threshold, power signal, and other signals, companies have developed model-based rules to answer the question: Will it break in the next couple of days? Metz said

“Machine learning can do this in a very automatic way. You don’t need tons of data to train the network, perhaps fifty measurements. A very nice example is a turning machine. The network learned very quickly that the tool is broken, even though the human cannot see it. The new approach is clearly able to see a drop in the health index, and stop production,” he said.

EUV Leads the Next Generation Litho Race

Friday, October 20th, 2017

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As previously reported by Solid State Technology, the eBeam Initiative recently reported the results of its lithography perceptions and mask-makers’ surveys. After the survey results were presented at the 2017 Photomask Technology Symposium, Aki Fujimura, CEO of D2S, the managing company sponsor of the eBeam Initiative, spoke with Solid State Technology about the survey results and current challenges in advanced lithography.

The Figure shows the consensus opinions of 75 luminaries from 40 companies who provided inputs to the perceptions survey regarding which Next-Generation Lithography (NGL) technologies will be used in volume manufacturing over the next few years. “We don’t want to interpret these data too much, but at the same time the information should be representative because people will be making business decisions based on this,” said Fujimura.

Figure 1

Confidence in Extreme Ultra-Violet (EUV) lithography is now strong, with 79 percent of respondents predicting it will be used in HVM by the end of 2021, a huge increase from 33 percent just three years ago. Another indication of aggregate confidence in EUVL technology readiness is that only 7 percent of respondents thought that “actinic mask inspection” would never be used in manufacturing, significantly reduced from 22 percent just last year.

“Asking luminaries is very meaningful, and obviously the answers are highly correlated with where the industry will be spending on technologies,” explained Fujimura. “The predictability of these sorts of things is very high. In particular in an industry with confidentiality issue, what people ‘think’ is going to happen typically reflects what they know but cannot say.”

Fujimura sees EUVL technology receiving most of the investment for next-generation lithography (NGL), “Because EUV is a universal technology. Whether you’re a memory or logic maker it’s useful for all applications. Whereas nano-imprint is only useful for defect-resistant designs like memory.”

Vivek Bakshi’s recent blog post details the current status of EUVL technology evolution. With practical limits on the source-power, many organization are looking at ways to increase the sensitivity of photoresist so as to increases the throughput of EUVL processes. Unfortunately, the physics and chemistry of photoresists means that there are inherent trade-offs between the best Resolution and Line-width-roughness (LWR) and Sensitivity, termed the “RLS triangle”.

The Critical Gases and Materials Group (CGMG) of SEMI held a recent webinar in which Greg MacIntyre, Imec’s director of patterning, discussed the inherent tradeoffs within the RLS triangle when attempting to create the smallest possible features with a single lithographic exposure. Since the resist sensitivity directly correlates to the maximum throughput of the lithographic exposure tool, there are various tricks used to improve the resolution and roughness at a given sensitivity:  optimized underlayer reflections for exposures, smoothing materials for post-develop, and hard-masks for etch integration.

Mask-Making Metrics

The business dynamics of making photomasks provides leading indicators of the IC fab industry’s technology directions. A lot of work has been devoted to keeping mask write times consistent compared with last year, while the average complexity of masks continues to increase with Reticle Enhancement Technologies (RET) to extend the resolution of optical lithography. Even with write times equal, the average mask turn-around time (TAT) is significantly greater for more critical layers, approaching 12 days for 7nm- to 10nm-node masks.

“A lot of the increase in mask TAT is coming from the data-preparation time,” explained Fujimura. “This is important for the economics and the logistics of mask shops.” The weighted average of mask data preparation time reported in the survey is significantly greater for finer masks, exceeding 21 hours for 7nm- to 10nm-nodes. Data per mask continues to increase; the most dense mask now averages 0.94 TB, and the most dense mask single mask takes 2.2 TB.

—E.K.

EUVL Materials Readiness for HVM

Friday, June 2nd, 2017

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By Ed Korczynski, Sr. Technology Editor

Extreme-Ultra-Violet Lithography (EUVL)—based on ~13.5nm wavelength EM waves bouncing off mirrors in a vacuum—will finally be used in commercial IC fabrication by Intel, Samsung, and TSMC starting in 2018. In a recent quarterly earning calls ASML reported a backlog of orders for 21 EUVL tools. At the 2017 SPIE Advanced Lithography conference, presentations detailed how the source and mask and resist all are near targets for next year, while the mask pellicle still needs work. Actinic metrology for mask inspection still remains a known expensive issue to solve.

Figure 1 shows minimal pitch line/space grids and contact-hole arrays patterned with EUVL at global R&D hub IMEC in Belgium, as presented at the recent 2017 IMEC Technology Forum. While there is no way with photolithography to escape the trade-offs of the Resolution/Line-Width-Roughness/Sensitivity (RLS) triangle, patterning at the leading edge of possible pitches requires application-specific etch integration. The bottom row of SEMs in this figure all show dramatic improvements in LWR through atomic-scale etch and deposition treatments to patterned sidewalls.

Fig.1: SEM plan-view images of minimum pitch Resolution and Line-Width-Roughness and Sensitivity (RLS) for both Chemically-Amplified Resist (CAR) and Non-Chemically-Amplified Resist (NCAR, meaning metal-oxide solution from Inpria) formulations, showing that excessive LWR can be smoothed by various post-lithography deposition/etch treatments. (Source: IMEC)

ASML has recently claimed that as an indication of continued maturity, ASML’s NXE:33×0 steppers have now collectively surpassed one million processed wafers to date, and only correctly exposed wafers were included in the count. During the company’s 1Q17 earnings call, it was reported that three additional orders for NXE:3400B steppers were received in Q1 adding  to a total of 21 in backlog, worth nearly US$2.5B.

At $117M each NXE:3400B, assuming 10 years useful life it costs $32,000 each day and assuming 18 productive hours/day and 80 wafers/hour then it costs $22 per wafer-pass just for tool depreciation. In comparison, a $40M argon-fluoride immersion (ArFi) stepper over ten years with 21 available hours/day and 240 wafers/hour costs $2.2 per wafer-pass for depreciation. EUVL will always be an expensive high-value-add technology, even though a single EUVL exposure can replace 4-5 ArFi exposures.

Fabs that delay use of EUVL at the leading edge of device scaling will instead have to buy and facilitize many more ArFi tools, demanding more fab space and more optical lithography gases. SemiMD spoke with Paul Stockman, Linde Electronics’ Head of Market Development, about the global supply of specialty neon and xenon gas blends:  “Xenon is only a ppm level component of the neon-blend for Kr and Ar lasers, so there should be no concerns with Xenon supply for the industry. In our modeling we’ve realized the impact of multi-patterning on gas demand, and we’ve assumed that the industry would need multi-patterning in our forecasts.” said Stockman.

“From the Linde perspective, we manage supply carefully to meet anticipated customer demand,” reminded Stockman. “We recently added 40 million liters of neon capacity in the US, and continue to add significant supply with partners so that we can serve our customers regardless of the EUV scenario.” (Editor’s note: reported by SemiMD here.)

At SPIE Advanced Lithography 2017, SemiMD discussed multi-patterning process flows with Uday Mitra and Regina Freed of Applied Materials. “We need a lot of materials engineering now,” explained Freed. “We need new gap-fills and hard-masks, and we may need new materials for selective deposition. Regarding the etch, we need extreme selectivity with no damage, and ability to get into the smallest features to take out just one atomic layer at a time.”

Reminding us that IC fabs must be risk-averse when considering technology options, Mitra (formerly with Intel) commented, “You don’t do a technology change and a wafer size change at the same time. That’s how you risk manage, and you can imagine with something like EUVL that customers will first use it for limited patterning and check it out.”

Figure 2 lists the major issues in pattern-transfer using plasma etch tools, along with the process variables that must be controlled to ensure proper pattern fidelity. Applied Materials’ Sym3 etch chamber features hardware that provides pulsed energy at dual frequencies along with low residence time of reactant byproducts to allow for precise tuning of process parameters no matter what chemistry is needed.

Fig.2: Patterning issues and associated etch process variables which can be used for control thereof. (Source: Applied Materials)

Andrew Grenville, CEO of resist supplier Inpria, in an exclusive interview with SemiMD, commented on the infrastructure readiness for EUVL volume production. “We are building up our pilot line facility in Corvallis, Oregon. The timing for that is next year, and we are putting in place plans to continue to scale up the new materials at the same times as the quality control systems such as functional QC.” The end-users ask for quality control checks of more parameters, putting a burden on suppliers to invest in more metrology tools and even develop new measurement techniques. Inpria’s resist is based on SnOx nanoparticles, which provide for excellent etch resistance even with layers as thin as 20nm, but required the development of a new technique to measure ppb levels of trace metals in the presence of high tin signals.

“We believe that there is continued opportunity for improvement in the overall patterning performance based on the ancillaries, particularly in simplifying the under-layers. One of the core principles of our material is that we’re putting the ‘resist’ back in the resist,” enthused Grenville. “We can show the etch contrast of our material can really improve the Line-Width Roughness of the patterns because of what you can do in etch, and it’s not merely smoothing the resist. We can substantially improve the outcome by engineering the stack and the etch recipe using completely different chemistry than could be used with chemically-amplified resist.”

The 2017 EUVL Workshop (2017 International Workshop on EUV Lithography) will be held June 12-15 at The Center for X-ray Optics (CXRO) at Lawrence Berkeley National Laboratory in Berkeley, CA. This workshop, now in its tenth year, is focused on the fundamental science of EUV Lithography (EUVL). Travel and hotel information as well as on-line registration is available at https://euvlitho.com/.

[DISCLOSURE:  Ed Korczynski is also Sr. Analyst for TECHCET responsible for the Critical Materials Report (CMR) on Photoresists, Extensions & Ancillaries.]

—E.K.

Lithographic Stochastic Limits on Resolution

Monday, April 3rd, 2017

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By Ed Korczynski, Sr. Technical Editor

The physical and economic limits of Moore’s Law are being approached as the commercial IC fab industry continues reducing device features to the atomic-scale. Early signs of such limits are seen when attempting to pattern the smallest possible features using lithography. Stochastic variation in the composition of the photoresist as well as in the number of incident photons combine to destroy determinism for the smallest devices in R&D. The most advanced Extreme Ultra-Violet (EUV) exposure tools from ASML cannot avoid this problem without reducing throughputs, and thereby increasing the cost of manufacturing.

Since the beginning of IC manufacturing over 50 years ago, chip production has been based on deterministic control of fabrication (fab) processes. Variations within process parameters could be controlled with statistics to ensure that all transistors on a chip performed nearly identically. Design rules could be set based on assumed in-fab distributions of CD and misalignment between layers to determine the final performance of transistors.

As the IC fab industry has evolved from micron-scale to nanometer-scale device production, the control of lithographic patterning has evolved to be able to bend-light at 193nm wavelength using Off-Axis Illumination (OAI) of Optical-Proximity Correction (OPC) mask features as part of Reticle Enhancement Technology (RET) to be able to print <40nm half-pitch (HP) line arrays with good definition. The most advanced masks and 193nm-immersion (193i) steppers today are able to focus more photons into each cubic-nanometer of photoresist to improve the contrast between exposed and non-exposed regions in the areal image. To avoid escalating cost and complexity of multi-patterning with 193i, the industry needs Extreme Ultra-Violet Lithography (EUVL) technology.

Figure 1 shows Dr. Britt Turkot, who has been leading Intel’s integration of EUVL since 1996, reassuring a standing-room-only crowd during a 2017 SPIE Advanced Lithography (http://spie.org/conferences-and-exhibitions/advanced-lithography) keynote address that the availability for manufacturing of EUVL steppers has been steadily improving. The new tools are close to 80% available for manufacturing, but they may need to process fewer wafers per hour to ensure high yielding final chips.

Figure 1. Britt Turkot (Intel Corp.) gave a keynote presentation on "EUVL Readiness for High-Volume Manufacturing” during the 2017 SPIE Advanced Lithography conference. (Source: SPIE)

The KLA-Tencor Lithography Users Forum was held in San Jose on February 26 before the start of SPIE-AL; there, Turcot also provided a keynote address that mentioned the inherent stochastic issues associated with patterning 7nm-node device features. We must ensure zero defects within the 10 billion contacts needed in the most advanced ICs. Given 10 billion contacts it is statistically certain that some will be subject to 7-sigma fluctuations, and this leads to problems in controlling the limited number of EUV photons reaching the target area of a resist feature. The volume of resist material available to absorb EUV in a given area is reduced by the need to avoid pattern-collapse when aspect-ratios increase over 2:1; so 15nm half-pitch lines will generally be limited to just 30nm thick resist. “The current state of materials will not gate EUV,” said Turkot, “but we need better stochastics and control of shot-noise so that photoresist will not be a long-term limiter.”

TABLE:  EUVL stochastics due to scaled contact hole size. (Source: Intel Corp.)

CONTACT HOLE DIAMETER 24nm 16nm
INCIDENT EUV PHOTONS 4610 2050
# ABSORBED IN AREAL IMAGE 700 215

From the LithoGuru blog of gentleman scientist Chris Mack (http://www.lithoguru.com/scientist/essays/Tennants_Law.html):

One reason why smaller pixels are harder to control is the stochastic effects of exposure:  as you decrease the number of electrons (or photons) per pixel, the statistical uncertainty in the number of electrons or photons actually used goes up. The uncertainty produces line-width errors, most readily observed as line-width roughness (LWR). To combat the growing uncertainty in smaller pixels, a higher dose is required.

We define a “stochastic” or random process as a collection of random variables (https://en.wikipedia.org/wiki/Stochastic_process), and a Wiener process (https://en.wikipedia.org/wiki/Wiener_process) as a continuous-time stochastic process in honor of Norbert Wiener. Brownian motion and the thermally-driven diffusion of molecules exhibit such “random-walk” behavior. Stochastic phenomena in lithography include the following:

  • Photon count,
  • Photo-acid generator positions,
  • Photon absorption,
  • Photo-acid generation,
  • Polymer position and chain length,
  • Diffusion during post-exposure bake,
  • Dissolution/neutralization, and
  • Etching hard-mask.

Figure 2 shows the stochastics within EUVL start with direct photolysis and include ionization and scattering within a given discrete photoresist volume, as reported by Solid State Technology in 2010.

Figure 2. Discrete acid generation in an EUV resist is based on photolysis as well as ionization and electron scattering; stochastic variations of each must be considered in minimally scaled areal images. (Source: Solid State Technology)

Resist R&D

During SPIE-AL this year, ASML provided an overview of the state of the craft in EUV resist R&D. There has been steady resolution improvement over 10 years with Photo-sensitive Chemically-Amplified Resists (PCAR) from 45nm to 13nm HP; however, 13nm HP needed 58 mJ/cm2, and provided DoF of 99nm with 4.4nm LWR. The recent non-PCAR Metal-Oxide Resist (MOR) from Inpria has been shown to resolve 12nm HP with  4.7 LWR using 38 mJ/cm2, and increasing exposure to 70 mJ/cm2 has produced 10nm HP L/S patterns.

In the EUVL tool with variable pupil control, reducing the pupil fill increases the contrast such that 20nm diameter contact holes with 3nm Local Critical-Dimension Uniformity (LCDU) can be done. The challenge is to get LCDU to <2nm to meet the specification for future chips. ASML’s announced next-generation N.A. >0.5 EUVL stepper will use anamorphic mirrors and masks which will double the illumination intensity per cm2 compared to today’s 0.33 N.A. tools. This will inherently improve the stochastics, when eventually ready after 2020.

The newest generation EUVL steppers use a membrane between the wafer and the optics so that any resist out-gassing cannot contaminate the mirrors, and this allow a much wider range of materials to be used as resists. Regarding MOR, there are 3.5 times more absorbed photons and 8 times more electrons generated per photon compared to PCAR. Metal hard-masks (HM) and other under-layers create reflections that have a significant effect on the LWR, requiring tuning of the materials in resist stacks.

Default R&D hub of the world imec has been testing EUV resists from five different suppliers, targeting 20 mJ/cm2 sensitivity with 30nm thickness for PCAR and 18nm thickness for MOR. All suppliers were able to deliver the requested resolution of 16nm HP line/space (L/S) patterns, yet all resists showed LWR >5nm. In another experiment, the dose to size for imec’s “7nm-node” metal-2 (M2) vias with nominal pitch of 53nm was ~60mJ/cm2. All else equal, three times slower lithography costs three times as much per wafer pass.

—E.K.

Edge Placement Error Control in Multi-Patterning

Thursday, March 2nd, 2017

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By Ed Korczynski, Sr. Technical Editor

SPIE Advanced Lithography remains the technical conference where the leading edge of minimum resolution patterning is explored, even though photolithography is now only part of the story. Leading OEMs continue to impress the industry with more productive ArFi steppers, but the photoresist suppliers and the purveyors of vacuum deposition and etch tools now provide most of the new value-add. Tri-layer-resist (TLR) stacks, specialty hard-masks and anti-reflective coatings (ARC), and complex thin-film depositions and etches all combine to create application-specific lithography solutions tuned to each critical mask.

Multi-patterning using complementary lithography—using argon-fluoride immersion (ArFi) steppers to pattern 1D line arrays plus extreme ultra-violet (EUV) tools to do line cuts—is under development at all leading edge fabs today. Figure 1 shows that edge placement error (EPE) in lines, cut layers, and vias/contacts between two orthogonal patterned layers can result in shorts and opens. Consequently, EPE control is critical for yield within any multi-patterning process flow, including litho-etch-litho-etch (LELE), self-aligned double-patterning (SADP) and self-aligned quadruple-patterning (SAQP).

Fig.1: Plan view schematic of 10nm half-pitch vertical lines overlaid with lower horizontal lines, showing the potential for edge-placement error (EPE). (Source: Y. Borodovsky, SPIE)

Happening the day before the official start of SPIE-AL, Nikon’s LithoVision event featured a talk by Intel Fellow and director of lithography hardware solutions Mark Phillips on the big picture of how the industry may continue to pattern smaller IC device features. Regarding the timing of Intel’s planned use of EUV litho technology, Phillips re-iterated that, “It’s highly desirable for the 7nm node, but we’ll only use it when it’s ready. However, EUVL will remain expensive even at full productivity, so 193i and multi-patterning will continue to be used. In particular we’ll need continued improvement in the 193i tools to meet overlay.”

Yuichi Shibazaki— Nikon Fellow and the main architect of the current generation of Nikon steppers—explained that the current generation of 193i steppers, featuring throughputs of >200 wafers per hour, have already been optimized to the point of diminishing returns. “In order to improve a small amount of performance it requires a lot of expense. So just improving tool performance may not decrease chip costs.” Nikon’s latest productivity offering is a converted alignment station as a stand-alone tool, intended to measure every product wafer before lithography to allow for feed-forward tuning of any stepper; cost and cost-of-ownership may be disclosed after the first beta-site tool reaches a customer by the end of this year.

“The 193 immersion technology continues to make steady progress, but there are not as many new game-changing developments,” confided Michael Lercel, Director of Strategic Marketing for ASML in an exclusive interview with SemiMD. “A major theme of several SPIE papers is on EPE, which traditionally we looked at as dependent upon CD and overlay. Now we’re looking at EPE in patterning more holistically, with need to control the complexity with different error-variables. The more information we can get the more we can control.”

At LithoVision this year, John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—discussed the challenges of controlling variability in multi-layer patterning. “A key challenge is predicting and then mitigating total EPE control,” reminded Sturtevant. “We’ve always paid attention to it, but the budgets that are available today are smaller than ever. Edge-placement is very important ” At the leading edge, there are multiple steps within the basic litho flow that induce proximity/local-neighbor effects which must be accounted for in EDA:  mask making, photoresist exposure, post-exposure bake (PEB), pattern development, and CD-SEM inspection (wherein there is non-zero resist shrinkage).

Due to the inherent physics of EUV lithography, as well as the atomic-scale non-uniformities in the reflective mirrors focusing onto the wafer, EUV exposure tools show significant variation in exposure uniformities. “For any given slit position there can be significant differences between tools. In practice we have used a single model of OPC for all slit locations in all scanners in the fab, and that paradigm may have to change,” said Sturtevant. “It’s possible that because the variation across the scanner is as much as the variation across the slit, it could mean we’ll need scanner-specific cross-slit computational lithography.” More than 3nm variation has been seen across 4 EUVL steppers, and the possible need for tool-specific optical proximity correction (OPC) and source-mask optimization (SMO) would be horrible for managing masks in HVM.

Thin Films Extend Patterning Resolution

Applied Materials has led the industry in thin-film depositions and etches for decades, and the company’s production proven processing platforms are being used more and more to extend the resolution of lithography. For SADP and SAQP MP, there are tunable unit-processes established for sidewall-spacer depositions, and chemical downstream etching chambers for mandrel pull with extreme material selectivity. CVD of dielectric and metallic hard-masks when combined with highly anisotropic plasma etching allows for device-specific and mask-specific pattern transfers that can reduce the line width/edge roughness (LWR/LER) originally present in the photoresist. Figure 2 from the SPIE-AL presentation “Impact of Materials Engineering on Edge Placement Error” by Regina Freed, Ying Zhang, and Uday Mitra of Applied Materials, shows LER reduction from 3.4 to 1.3 nm is possible after etch. The company’s Sym3 chamber features very high gas conductance to prevent etch byproducts from dissociation and re-deposition on resist sidewalls.

Fig.2: 3D schematics (top) and plan view SEM images (bottom) showing that control of plasma parameters can tune the byproducts of etch processes to significantly reduce the line-width roughness (LWR) of minimally scaled lines. (Source: Applied Materials)

TEL’s new SAQP spacer-on-spacer process builds on the work shown last year, using oxide as first spacer and TiO2 as second spacer. Now TEL is exploring silicon as the mandrel, then silicon-nitride as the first spacer, and titanium-oxide as second spacer. This new flow can be tuned so that all-dry etch in a single plasma etch chamber can be used for the final mandrel pull and pattern transfer steps.

Coventor’s 3D modeling software allows companies to do process integration experiments in virtual space, allowing for estimation of yield-losses in pattern transfer due to variations in side-wall profiles and LER. A simulation of 9 SRAM cells with 54 transistors shows that photoresist sidewall taper angle determines both the size and the variability of the final fins. The final capacitance of low-k dielectric in dual-damascene copper metal interconnects can be simulated as a function of the initial photoresist profile in a SAQP flow.

—E.K.

High-NA EUV Lithography Investment

Monday, November 28th, 2016

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By Ed Korczynski, Sr. Technical Editor

As covered in a recent press release, leading lithography OEM ASML invested EUR 1 billion in cash to buy 24.9% of ZEISS subsidiary Carl Zeiss SMT, and committed to spend EUR ~760 million over the next 6 years on capital expenditures and R&D of an entirely new high numerical aperture (NA) extreme ultra-violet (EUV) lithography tool. Targeting NA >0.5 to be able to print 8 nm half-pitch features, the planned tool will use anamorphic mirrors to reduce shadowing effects from nanometer-scale mask patterns. Clever design and engineering of the mirrors could allow this new NA >0.5 tool to be able to achieve wafer throughputs similar to ASML’s current generation of 0.33 NA tools for the same source power and resist speed.

The Numerical Aperture (NA) of an optical system is a dimensionless number that characterizes the range of angles over which the system can accept or emit light. Higher NA systems can resolve finer features by condensing light from a wider range of angles. Mirror surfaces to reflect EUV “light” are made from over 50 atomic-scale bi-layers of molybdenum (Mo) and silicon (Si), and increasing the width of mirrors to reach higher NA increases the angular spread of the light which results in shadows within patterns.

In the proceedings of last year’s European Mask and Lithography Conference, Zeiss researchers reported on  “Anamorphic high NA optics enabling EUV lithography with sub 8 nm resolution” (doi:10.1117/12.2196393). The abstract summarizes the inherent challenges of establishing high NA EUVL technology:

For such a high-NA optics a configuration of 4x magnification, full field size of 26 x 33 mm² and 6’’ mask is not feasible anymore. The increased chief ray angle and higher NA at reticle lead to non-acceptable mask shadowing effects. These shadowing effects can only be controlled by increasing the magnification, hence reducing the system productivity or demanding larger mask sizes. We demonstrate that the best compromise in imaging, productivity and field split is a so-called anamorphic magnification and a half field of 26 x 16.5 mm² but utilizing existing 6’’ mask infrastructure.

Figure 1 shows that ASML plans to introduce such a system after the year 2020, with a throughput of 185 wafers-per-hour (wph) and with overlay of <2 nm. Hans Meiling, ASML vice president of product management EUV, in an exclusive interview with Solid State Technology explained why >0.5 NA capability will not be upgradable on 0.33 NA tools, “the >0.5NA optical path is larger and will require a new platform. The anamorphic imaging will also require stage architectural changes.”

Fig.1: EUVL stepper product plans for wafers per hour (WPH) and overlay accuracy include change from 0.33 NA to a new >0.5 NA platform. (Source: ASML)

Overlay of <2 nm will be critical when patterning 8nm half-pitch features, particularly when stitching lines together between half-fields patterned by single-exposures of EUV. Minimal overlay is also needed for EUV to be used to cut grid lines that are initially formed by pitch-splitting ArFi. In addition to the high NA set of mirrors, engineers will have to improve many parts of the stepper to be able to improve on the 3 nm overlay capability promised for the NXE:3400B 0.33 NA tool ASML plans to ship next year.

“Achieving better overlay requires improvements in wafer and reticle stages regardless of NA,” explained Meiling. “The optics are one of the many components that contribute to overlay. Compare to ArF immersion lithography, where the optics NA has been at 1.35 for several generations but platform improvements have provided significant overlay improvements.”

Manufacturing Capability Plans

Figure 2 shows that anamorphic systems require anamorphic masks, so moving from 0.33 to >0.5 NA requires re-designed masks. For relatively large chips, two adjacent exposures with two different anamorphic masks will be needed to pattern the same field area which could be imaged with lower resolution by a single 0.33 NA exposure. Obviously, such adjacent exposures of one layer must be properly “stitched” together by design, which is another constraint on electronic design automation (EDA) software.

Fig.2: Anamorphic >0.5 NA EUVL system planned by ASML and Zeiss will magnify mask images by 4x in the x-direction and 8x in the y-direction. (Source: Carl Zeiss SMT)

Though large chips will require twice as many half-field masks, use of anamorphic imaging somewhat reduces the challenges of mask-making. Meiling reminds us that, “With the anamorphic imaging, the 8X direction conditions will actually relax, while the 4X direction will require incremental improvements such as have always been required node-on-node.”

ASML and Zeiss report that ideal holes which “obscure” the centers of mirrors can surprisingly allow for increased transmission of EUV by each mirror, up to twice that of the “unobscured” mirrors in the 0.33 NA tool. The holes allow the mirrors to reflect through each-other, so they all line up and reflect better. Theoretically then each >0.5 NA half-field can be exposed twice as fast as a 0.33 NA full-field, though it seems that some system throughput loss will be inevitable. Twice the number of steps across the wafer will have to slow down throughput by some percent.

White two stitched side-by-side >0.5 NA EUVL exposures will be challenging, the generally known alternatives seem likely to provide only lower throughputs and lower yields:

*   Double-exposure of full-field using 0.33 NA EUVL,

*   Octuple-exposure of full-field using ArFi, or

*   Quadruple-exposure of full-field using ArFi complemented by e-beam direct-writing (EbDW) or by directed self-assembly (DSA).

One ASML EUVL system for HVM is expected to cost ~US$100 million. As presented at the company’s October 31st Investor Day this year, ASML’s modeling indicates that a leading-edge logic fab running ~45k wafer starts per month (WSPM) would need to purchase 7-12 EUV systems to handle an anticipated 6-10 EUV layers within “7nm-node” designs. Assuming that each tool will cost >US$100 million, a leading logic fab would have to invest ~US$1 billion to be able to use EUV for critical lithography layers.

With near US$1 billion in capital investments needed to begin using EUVL, HVM fabs want to be able to get productive value out of the tools over more than a single IC product generation. If a logic fab invests US$1 billion to use 0.33 NA EUVL for the “7nm-node” there is risk that those tools will be unproductive for “5nm-node” designs expected a few years later. Some fabs may choose to push ArFi multi-patterning complemented by another lithography technology for a few years, and delay investment in EUVL until >0.5 NA tools become available.

—E.K.

Multibeam Patents Direct Deposition & Direct Etch

Monday, November 14th, 2016

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By Ed Korczynski, Sr. Technical Editor

Multibeam Corporation of Santa Clara, California recently announced that its e-beam patent portfolio—36 filed and 25 issued—now includes two innovations that leverage the precision placement of electrons on the wafer to activate chemical processes such as deposition and etch. As per the company’s name, multi-column parallel processing chambers will be used to target throughputs usable for commercial high-volume manufacturing (HVM) though the company does not yet have a released product. These new patents add to the company’s work in developing Complementary E-Beam Lithography (CEBL) to reduce litho cost, Direct Electron Writing (DEW) to enhance device security, and E-Beam Inspection (EBI) to speed defect detection and yield ramp.

The IC fab industry’s quest to miniaturize circuit features has already reached atomic scales, and the temperature and pressure ranges found on the surface of our planet make atoms want to move around. We are rapidly leaving the known era of deterministic manufacturing, and entering an era of stochastic manufacturing where nothing is completely determined because atomic placements and transistor characteristics vary within distributions. In this new era, we will not be able to guarantee that two adjacent transistors will function the same, which can lead to circuit failures. Something new is needed. Either we will have to use new circuit design approaches that require more chip area such as “self-healing” or extreme redundancy, or the world will have to inspect and repair transistors within the billions on every HVM chip.

In an exclusive interview with Solid State Technology, David K. Lam, Multibeam Chairman, said, “We provide a high-throughput platform that uses electron beams as an activation mechanism. Each electron-beam column integrates gas injectors, as well as sensors, which enable highly localized control of material removal and deposition. We can etch material in a precise location to a precise depth. Same with deposition.” Lam (Sc.D. MIT) was the founder and first CEO of Lam Research where he led development and market penetration of the IC fab industry’s first fully automated plasma etch system, and was inducted into the Silicon Valley Engineering Hall of Fame in 2013.

“Precision deposition using miniature-column charged particle beam arrays” (Patent #9,453,281) describes patterning of IC layers by either creating a pattern specified by the design layout database in its entirety or in a complementary fashion with other patterning processes. Reducing the total number of process steps and eliminating lithography steps in localized material addition has the dual benefit of reducing manufacturing cycle time and increasing yield by lowering the probability of defect introduction. Furthermore, highly localized, precision material deposition allows for controlled variation of deposition rate and enables creation of 3D structures such as finFETs and NanoWire (NW) arrays.

Deposition can be performed using one or more multi-column charged particle beam systems using chemical vapor deposition (CVD) alone or in concert with other deposition techniques. Direct deposition can be performed either sequentially or simultaneously by multiple columns in an array, and different columns can be configured and/or optimized to perform the same or different material depositions, or other processes such as inspection and metrology.

“Precision substrate material removal using miniature-column charged particle beam arrays” (Patent #9,466,464) describes localized etch using activation electrons directed according to the design layout database so that etch masks are no longer needed. Figure 1 shows that costs are reduced and edge placement accuracy is improved by eliminating or reducing errors associated with photomasks, litho steps, and hard masks. With highly localized process control, etch depths can vary to accommodate advanced 3D device structures.

Fig.1: Comparison of (LEFT) the many steps needed to etch ICs using conventional wafer processing and (RIGHT) the two simple steps needed to do direct etching. (Source: Multibeam)

“We aren’t inventing new etch chemistries, precursors or reactants,” explained Lam. “In direct etch, we leverage developments in reactive ion etching and atomic layer etch. In direct deposition, we leverage work in atomic layer deposition. Several research groups are also developing processes specifically for e-beam assisted etch and deposition.”

The company continues to invent new hardware, and the latest critical components are “kinetic lens” which are arrangements of smooth and rigid surfaces configured to reflect gas particles. When fixed in position with respect to a gas injector outflow opening, gas particles directed at the kinetic lens are collimated or redirected (e.g., “focused”) towards a wafer surface or a gas detector. Generally, surfaces of a kinetic lens can be thought of as similar to optical mirrors, but for gas particles. A kinetic lens can be used to improve localization on a wafer surface so as to increase partial pressure of an injected gas in a target area. A kinetic lens can also be used to increase specificity and collection rate for a gas detector within a target frame.

Complementary Lithography

Complementary lithography is a cost-effective variant of multi-patterning where some other patterning technology is used with 193nm ArF immersion (ArFi) to extend the resolution limit of the latter. The company’s Pilot™ CEBL Systems work in coordination with ArFi lithography to pattern cuts (of lines in a “1D lines-and-cuts” layout) and holes (i.e., contacts and vias) with no masks. These CEBL systems can seamlessly incorporate multicolumn EBI to accelerate HVM yield ramps, using feedback and feedforward as well as die-to-database comparison.

Figure 2 shows that “1D” refers to 1D gridded design rule. In a 1D layout, optical pattern design is restricted to lines running in a single direction, with features perpendicular to the 1D optical design formed in a complementary lithography step known as “cutting”. The complementary step can be performed using a charged particle beam lithography tool such as Multibeam’s array of electrostatically-controlled miniature electron beam columns. Use of electron beam lithography for this complementary process is also called complementary e-beam lithography, or CEBL. The company claims that low pattern-density layers such as for cuts, one multi-column chamber can provide 5 wafers-per-hour (wph) throughput.

Fig.2: Complementary E-Beam Lithography (CEBL) can be used to “cut” the lines within a 1D grid array previously formed using ArF-immersion (ArFi) optical steppers. (Source: Multibeam)

Direct deposition can be used to locally interconnect 1D lines produced by optical lithography. This is similar in design principle to complementary lithography, but without using a resist layer during the charged particle beam phase, and without many of the steps required when using a resist layer. In some applications, such as restoring interconnect continuity, the activation electrons are directed to repair defects that are detected during EBI.

—E.K.

D2S Releases 4th-Gen IC Computational Design Platform

Friday, September 30th, 2016

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By Ed Korczynski, Sr. Technical Editor

D2S (www.design2silicon.com) recently released the fourth generation of its computational design platform (CDP), which enables extremely fast (400 Teraflops) and precise simulations for semiconductor design and manufacturing. The new CDP is based on NVIDIA Tesla K80 GPUs and Intel Haswell CPUs, and is architected for 24×7 cleanroom production environments. To date, 14 CDPs across four platform generations are in use by customers around the globe, including six of the latest fourth generation. In an exclusive interview with SemiMD, D2S CEO Aki Fujimura stated, “Now that GPUs and CPUs are fast-enough, they can replace other hardware and thereby free up engineering resources to focus on adding value elsewhere.”

Mask data preparation (MDP) and other aspects of IC design and manufacturing require ever-increasing levels of speed and reliability as the data sets upon which they must operate grow larger and more complex with each device generation. The Figure shows a mask needed to print arrays of sub-wavelength features includes complex curvilinear shapes which must be precisely formed even though they do not print on the wafer. Such sub-resolution assist features (SRAF) increase in complexity and density as the half-pitch decreases, so the complexity of mask data increases far more than the density of printed features.

Sub-wavelength lithography using 193nm wavelength requires ever-more complex masks to repeatably print ever smaller half-pitch (HP) features, as shown by (LEFT) a typical mask composed of complex nested curves and dots which do not print (RIGHT) in the array of 32nm HP contacts/vias represented by the small red circles. (Source: D2S)

GPUs, which were first developed as processing engines for the complex graphical content of computer games, have since emerged as an attractive option for compute-intensive scientific applications due in part to their ability to run many more computing threads (up to 500x) compared to similar-generation CPUs. “Being able to process arbitrary shapes is something that mask shops will have to do,” explained Fujimura. “The world could go 193nm or EUV at any particular node, but either way there will be more features and higher complexity within the features, and all of that points to GPU acceleration.”

The D2S CDP is engineered for high reliability inside a cleanroom manufacturing environment. A few of the fab applications where CDPs are currently being used include:

  • model-based MDP for leading-edge designs that require increasingly complex mask shapes,
  • wafer plane analysis of SEM mask images to identify mask errors that print, and
  • inline thermal-effect correction of eBeam mask writers to lower write times.

“The amount of design data required to produce photomasks for leading-edge chip designs is increasing at an exponential rate, which puts more pressure on mask writing systems to maintain reasonable write times for these advanced masks. At the same time, writing these masks requires higher exposure doses and shot counts, which can cause resist proximity heating effects that lead to mask CD errors,” stated Noriaki Nakayamada, group manager at NuFlare Technology. “D2S GPU acceleration technology significantly reduces the calculation time required to correct these resist heating effects. By employing a resist heating correction that includes the use of the D2S CDP as an OEM option on our mask writers, NuFlare estimates that it can reduce CD errors by more than 60 percent, and reduce write times by more than 20 percent.”

In the E-beam Initiative 2015 survey, the most advanced reported mask-set contained >100 masks of which ~20% could be considered ‘critical’. The just released 2016 survey disclosed that the most complex single-layer mask design written last year required 16 TB of data, however platforms like D2S’ CDP have been used to accelerate writing such that the average reported write times have decreased to a weighted average of 4 hours. Meanwhile, the longest reported mask write time decreased from 72 to 48 hours.

Molecular Modeling of Materials Defects for Yield Recovery

Monday, March 21st, 2016

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By Ed Korczynski, Sr. Technical Editor

New materials are being integrated into High Volume Manufacturing (HVM) of semiconductor ICs, while old materials are being extended with more stringent specifications. Defects within materials cause yield losses in HVM fabs, and engineers must identify the specific source of an observed defect before corrective steps can be taken. Honeywell Electronic Materials has been using molecular modeling software provided by Scienomics to both develop new materials and to modify old materials. Modeling allowed Honeywell to uncover the origin of subtle solvation-based film defects within Bottom Anti-Reflective Coatings (BARC) which were degrading yield in a customer’s lithographic process module.

Scienomics sponsored a Materials Modeling and Simulations online seminar on February 26th of this year, featuring Dr. Nancy Iwamoto of Honeywell discussing how Scienomics software was used to accelerate response to a customer’s manufacturing yield loss. “This was a product running at a customer line,” explained Iwamoto, “and we needed to find the solution.” The product was a Bottom Anti-Reflective Coating (BARC) organo-silicate polymer delivered in solution form and then spun on wafers to a precise thickness.

Originally observed during optical inspection by fab engineers as 1-2 micron sized vague spots in the BARC, the new defect type was difficult to see yet could be correlated to lithographic yield loss. The defects appeared to be discrete within the film instead of on the top surface, so the source was likely some manner of particle, yet filters did not capture these particles.

The filter captured some particles rich in silicon, as well as other particles rich in carbon. Sequential filtration showed that particles were passing through impossibly small pores, which suggested that the particles were built of deformable gel-like phases. The challenge was to find the material handling or processing situation, which resulted in thermodynamically possible and kinetically probable conditions that could form such gels.

Fig: Materials Processes and Simulations (MAPS) gives researchers access to visualization and analysis tools in a single user interface together with access to multiple simulation engines. (Source: Scienomics)

Molecular modeling and simulation is a powerful technique that can be used for materials design, functional upgrades, process optimization, and manufacturing. The Figure shows a dashboard for Scienomics’ modeling platform. Best practices in molecular modeling to find out-of-control parameters in HVM include a sequential workflow:

  • Build correct models based on experimental observables,
  • Simulate potential molecular structures based on known chemicals and hierarchical models,
  • Analyze manufacturing variabilities to identify excursion sources, and
  • Propose remedy for failure elimination.

Honeywell Electronic Materials researchers had very few experimental observables from which to start:  phenomenon is rare (yet effects yield), not filterable, yet from thermodynamic hydrolysis parameters it must be quasi-stable. Re-testing of product and re-examination of Outgoing Quality Control (OQC) data at the Honeywell production site showed that the molecular weight of the product was consistent with the desired distribution. There was also an observed BARC thickness increase of ~1nm on the wafer associated with the presence of these defects.

Using the modeling platform, Honeywell looked at the solubility parameters for different small molecular chains off of known-branched back-bone centers. Gel-like agglomerations could certainly be formed under the wrong conditions. Once the agglomerations form, they are not very stable so they can probably dis-aggregate when being forced through a filter and then re-aggregate on the other side.

What conditions could induce gel formation? After a few weeks of modeling, it was determined that temperature variations had the greatest influence on the agglomeration, and that variability was strongest at the ~250°K recommended for storage. Storage at 230°K resulted in measurably worse agglomeration, and any extreme in heating/cooling ramp rate tended to reduce solubility.

Molecular modeling was used in a forensic manner to find that the root cause of gel-like defects was related to thermal history:

*   Thermodynamics determined the most likely oligomers that could agglomerate,

*   Temperature-dependent solubility models determined which particles would reach wafers.

Because of the on-wafer BARC thickness increase of ~1nm, fab engineers could use all of the molecular modeling information to trace the temperature variation to bottles installed in the lithographic track tool. The fab was able to change specifications for the storage and handling of the BARC bottles to bring the process back into control.

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