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Posts Tagged ‘lithography’

The Week in Review: March 28, 2014

Friday, March 28th, 2014

Altera Corporation and Intel Corporation announced their collaboration on the development of multi-die devices that leverage Intel’s package and assembly capabilities and Altera’s leading-edge programmable logic technology. The collaboration is an extension of the foundry relationship between Altera and Intel, in which Intel is manufacturing Altera’s Stratix 10 FPGAs and SoCs using the 14nm Tri-Gate process. Altera’s work with Intel will enable the development of multi-die devices that efficiently integrates monolithic 14nm Stratix 10 FPGAs and SoCs with other advanced components, which may include DRAM, SRAM, ASICs, processors and analog components, in a single package.

Samsung introduced a new lineup of flip chip LED packages and modules offering enhanced design flexibility and a high degree of reliability. The new offerings, for use in leading-edge LED lighting such as LED bulbs, MR/PAR and downlights, will be available in the market during the second quarter of this year. Samsung’s new flip chip (FC) LED package and flip chip on module (FCOM) solutions feature highly efficient and versatile LED structures, created by flipping over blue LED chips and adhering phosphor film to each of them. Unlike conventional LED packages that dispense phosphor and then place a plastic mold over each chip, Samsung’s FC package technology can produce LED packages down to a chip-scale size without any mold, enabling more compact lighting fixture designs.

eInfochips, a semiconductor and product engineering company, this week launched design services for chips based on 16nm geometry. The comprehensive suite of services includes Netlist to GDSII, Sign-off, and Design for Testability. eInfochips is one of the few engineering services companies in the world capable of delivering 16nm chip designs which reduce a chip’s power consumption by half, while improving performance by one-third over 28nm technology.

SEMATECH announced this week that Particle Measuring Systems has joined SEMATECH to advance the development of nanoscale particle removal processes and cleaning technologies for next-generation wafers and devices. This collaboration will address many of the profound changes taking place in the semiconductor industry that are impacting fundamental aspects of process and equipment design, including integration of new materials and process technology for sub-20nm node manufacturing, next-generation lithography requirements.

CEA-Leti will demonstrate its new prototype for wireless high data rate Li-Fi (light fidelity) transmission at Light + Building 2014 in Frankfurt, Germany, March 30-April 4. The technology employs the high-frequency modulation capabilities of light-emitting diode (LED) engines used in commercial lighting. It achieves throughputs of up to 10Mb/s at a range of three meters, suitable for HD video streaming or Internet browsing, using light power of less than 1,000 lumens and with direct or even indirect lighting. With this first proof of concept and its expertise in RF communications, Leti forecasts data transmission rates in excess of 100Mb/s with traditional lighting based on LED lamps using this technology approach and without altering the high-performance lighting characteristics.

Research Alert: March 18, 2014

Tuesday, March 18th, 2014

Creating a graphene-metal sandwich to improve electronics

Researchers have discovered that creating a graphene-copper-graphene “sandwich” strongly enhances the heat conducting properties of copper, a discovery that could further help in the downscaling of electronics.

The work was led by Alexander A. Balandin, a professor of electrical engineering at the Bourns College of Engineering at the University of California, Riverside and Konstantin S. Novoselov, a professor of physics at the University of Manchester in the United Kingdom. Balandin and Novoselov are corresponding authors for the paper just published in the journal Nano Letters. In 2010, Novoselov shared the Nobel Prize in Physics with Andre Geim for their discovery of graphene.

In the experiments, the researchers found that adding a layer of graphene, a one-atom thick material with highly desirable electrical, thermal and mechanical properties, on each side of a copper film increased heat conducting properties up to 24 percent.

“This enhancement of copper’s ability to conduct heat could become important in the development of hybrid copper — graphene interconnects for electronic chips that continue to get smaller and smaller,” said Balandin, who in 2013 was awarded the MRS Medal from the Materials Research Society for discovery of unusual heat conduction properties of graphene.

Whether the heat conducting properties of copper would improve by layering it with graphene is an important question because copper is the material used for semiconductor interconnects in modern computer chips. Copper replaced aluminum because of its better electrical conductivity.

Surface characteristics influence cellular growth on semiconductor material

Changing the texture and surface characteristics of a semiconductor material at the nanoscale can influence the way that neural cells grow on the material.

The finding stems from a study performed by researchers at North Carolina State University, the University of North Carolina at Chapel Hill and Purdue University, and may have utility for developing future neural implants.

“We wanted to know how a material’s texture and structure can influence cell adhesion and differentiation,” says Lauren Bain, lead author of a paper describing the work and a Ph.D. student in the joint biomedical engineering program at NC State and UNC-Chapel Hill. “Basically, we wanted to know if changing the physical characteristics on the surface of a semiconductor could make it easier for an implant to be integrated into neural tissue – or soft tissue generally.”

The researchers worked with gallium nitride (GaN), because it is one of the most promising semiconductor materials for use in biomedical applications. They also worked with PC12 cells, which are model cells used to mimic the behavior of neurons in lab experiments.

In the study, the researchers grew PC12 cells on GaN squares with four different surface characteristics: some squares were smooth; some had parallel grooves (resembling an irregular corduroy pattern); some were randomly textured (resembling a nanoscale mountain range); and some were covered with nanowires (resembling a nanoscale bed of nails).

Very few PC12 cells adhered to the smooth surface. And those that did adhere grew normally, forming long, narrow extensions. More PC12 cells adhered to the squares with parallel grooves, and these cells also grew normally.

About the same number of PC12 cells adhered to the randomly textured squares as adhered to the parallel grooves. However, these cells did not grow normally. Instead of forming narrow extensions, the cells flattened and spread across the GaN surface in all directions.

More PC12 cells adhered to the nanowire squares than to any of the other surfaces, but only 50 percent of the cells grew normally. The other 50 percent spread in all directions, like the cells on the randomly textured surfaces.

“This tells us that the actual shape of the surface characteristics influences the behavior of the cells,” Bain says. “It’s a non-chemical way of influencing the interaction between the material and the body. That’s something we can explore as we continue working to develop new biomedical technologies.”

First methodology to analyze nanometer line pattern images

In the study, the researchers grew PC12 cells on GaN squares with four different surface characteristics: some squares were smooth; some had parallel grooves (resembling an irregular corduroy pattern); some were randomly textured (resembling a nanoscale mountain range); and some were covered with nanowires (resembling a nanoscale bed of nails).

Very few PC12 cells adhered to the smooth surface. And those that did adhere grew normally, forming long, narrow extensions. More PC12 cells adhered to the squares with parallel grooves, and these cells also grew normally.

About the same number of PC12 cells adhered to the randomly textured squares as adhered to the parallel grooves. However, these cells did not grow normally. Instead of forming narrow extensions, the cells flattened and spread across the GaN surface in all directions.

More PC12 cells adhered to the nanowire squares than to any of the other surfaces, but only 50 percent of the cells grew normally. The other 50 percent spread in all directions, like the cells on the randomly textured surfaces.

“This tells us that the actual shape of the surface characteristics influences the behavior of the cells,” Bain says. “It’s a non-chemical way of influencing the interaction between the material and the body. That’s something we can explore as we continue working to develop new biomedical technologies.”

Research Alert: March 4, 2014

Tuesday, March 4th, 2014

SRC and MIT extend high-resolution lithography

MIT researchers sponsored by Semiconductor Research Corporation have introduced new directed self-assembly (DSA) techniques that promise to help semiconductor manufacturers develop more advanced and less expensive components.

The MIT study demonstrates that complex patterns of lines, bends and junctions with feature sizes below 20nm can be made by block copolymer self-assembly guided by a greatly simplified template. This study explained how to design the template to achieve a desired pattern. Electron-beam lithography was used to produce the template serially, while the block copolymer filled in the rest of the pattern in a parallel process. This hybrid process can be five or more times faster than writing the entire pattern by electron beam lithography.

sembly to produce dense, high resolution patterns was proposed and demonstrated several years ago, but there was no systematic way to design templates to achieve a complex block copolymer pattern. The MIT study developed a simple way to design a template to achieve a specific block copolymer pattern over a large area. Although the work used electron-beam lithography to define the template, other methods such as photolithography with trimming could be used to produce the templates.

Block copolymer lithography is already on the semiconductor industry roadmap as directed self-assembly, but the process is still in its infancy. Although DSA patterning has been demonstrated on 300 millimeter wafers, these early trials used templates fabricated by photolithography with limited resolution and limited control of the feature geometry. The MIT process offers a path to far more complicated geometries using relatively simple templates. Next steps involve the research being shared with semiconductor companies for further studies.

How 19th century physics could change the future of nanotechnology

Researchers at the University of Cincinnati have found that their unique method of light-matter interaction analysis appears to be a good way of helping make better semiconductor nanowires.

“Semiconductor nanowires are one of the hottest topics in the nanoscience research field in the recent decade,” says Yuda Wang, a UC doctoral student. “Due to the unique geometry compared to conventional bulk semiconductors, nanowires have already shown many advantageous properties, particularly in novel applications in such fields as nanoelectronics, nanophotonics, nanobiochemistry and nanoenergy.”

Wang will present the team’s research “Transient Rayleigh Scattering Spectroscopy Measurement of Carrier Dynamics in Zincblende and Wurtzite Indium Phosphide Nanowires” at the American Physical Society (APS) meeting to be held March 3-7 in Denver. Nearly 10,000 professionals, scholars and students will attend the APS meeting to discuss new research from industry, universities and laboratories from around the world.

Key to this research is UC’s new method of Rayleigh scattering, a phenomenon first described in 1871 and the scientific explanation for why the sky is blue in the daytime and turns red at sunset. The researchers’ Rayleigh scattering technique probes the band structures and electron-hole dynamics inside a single indium phosphide nanowire, allowing them to observe the response with a time resolution in the femtosecond range – or one quadrillionth of a second.

JILA physicists discover “quantum droplet” in semiconductor

JILA physicists used an ultrafast laser and help from German theorists to discover a new semiconductor quasiparticle—a handful of smaller particles that briefly condense into a liquid-like droplet.

Quasiparticles are composites of smaller particles that can be created inside solid materials and act together in a predictable way. A simple example is the exciton, a pairing, due to electrostatic forces, of an electron and a so-called “hole,” a place in the material’s energy structure where an electron could be, but isn’t.

The new quasiparticle, described in the Feb. 27, 2014, issue of Nature and featured on the journal’s cover, is a microscopic complex of electrons and holes in a new, unpaired arrangement. The researchers call this a “quantum droplet” because it has quantum characteristics such as well-ordered energy levels, but also has some of the characteristics of a liquid. It can have ripples, for example. It differs from a familiar liquid like water because the quantum droplet has a finite size, beyond which the association between electrons and holes disappears.

Although its lifetime is only a fleeting 25 picoseconds (trillionths of a second), the quantum droplet is stable enough for research on how light interacts with specialized forms of matter.

The JILA team created the new quasiparticle by exciting a gallium-arsenide semiconductor with an ultrafast red laser emitting about 100 million pulses per second. The pulses initially form excitons, which are known to travel around in semiconductors. As laser pulse intensity increases, more electron-hole pairs are created, with quantum droplets developing when the exciton density reaches a certain level. At that point, the pairing disappears and a few electrons take up positions relative to a given hole. The negatively charged electrons and positively charged holes create a neutral droplet. The droplets are like bubbles held together briefly by pressure from the surrounding plasma.

The Week in Review: Nov. 22, 2013

Friday, November 22nd, 2013

GLOBALFOUNDRIES, Open-Silicon and Amkor Technology have jointly exhibited a functional system-on-chip (SoC) solution on a 2.5D silicon interposer featuring two 28nm logic chips, with embedded ARM processors. The jointly developed design is a test vehicle that showcases the benefits of 2.5D technology for mobile and low-power server applications. The companies recently demonstrated the functioning SoC at ARM TechCon in Santa Clara, CA.

North America-based manufacturers of semiconductor equipment posted $1.12 billion in orders worldwide in October 2013 (three-month average basis) and a book-to-bill ratio of 1.05, according to the October EMDS Book-to-Bill Report published this week by SEMI.   A book-to-bill of 1.05 means that $105 worth of orders were received for every $100 of product billed for the month. “Both equipment orders and billings improved in the October data, resulting in a book-to-bill ratio returning above parity,” said Denny McGuirk, president and CEO of SEMI.  ”Order activity is well above the figures reported one year ago and point towards on-going investments in advanced process technologies for NAND Flash, microprocessor, and foundry.”

Soraa, a developer of GaN on GaN LED technology, announced that it will open a new semiconductor fabrication plant in Buffalo, New York. In partnership with the State of New York, the company will construct a new state-of-the-art GaN on GaN LED fabrication facility that will employ hundreds of workers. The new facility is projected to be operational in 2015. Soraa currently operates an LED fabrication plant in Fremont, California, one of only a few in the US.

Dow Corning introduced new Dow Corning MS-2002 Moldable White Reflector Silicone at Strategies in Light Europe 2013. This highly reflective white material extends the excellent photo-thermal stability and high-moldability that typifies Dow Corning’s award-winning optical-grade Moldable Silicone family to the reflective elements of LED lamp and luminaire applications. Dow Corning MS-2002 Moldable White Reflector Silicone targets reflectivity as high as 98 percent to help further boost light output from LED devices, improve overall energy efficiency and prolong device reliability.

SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets, has successfully installed an ELP300 excimer laser stepper to support next generation advanced packaging and 3D IC laser debonding applications at the Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin. The ELP300 excimer laser platform is designed for high volume manufacturing and processing of 100mm to 300mm wafers.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, introduced the EVG PHABLE exposure system, which is designed specifically for manufacturing photonic components.  Leveraging EVG’s expertise in photolithography, the EVG PHABLE system incorporates a unique contactless lithography mask-based approach that enables full-field, high-resolution and cost-efficient micro- and nanopatterning of passive and active photonic components, such as patterned structures on light emitting diode (LED) wafers, in high-throughput production environments.

The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions

Thursday, September 19th, 2013

Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models, in turn, rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. While certain system input variables, such as scanner numerical aperture, can be empirically tuned to wafer CD data over a small range around the presumed set point, it can be dangerous to do so since CD errors can alias across multiple input variables. Therefore, many input variables for simulation are based upon designed or recipe-requested values or independent measurements. However, certain measurement methodologies, while precise, can be inaccurate. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total CD control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine with a simulation sensitivity study, the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD Bias values are based on state of the art mask manufacturing data and other variables changes are speculated, highlighting the need for improved metrology and awareness.

To download this white paper, click here.

EUV Flare And Proximity Modeling And Model-Based Correction

Thursday, May 16th, 2013

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. This paper focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based.

To view this white paper, click here.

Computational Lithography

Thursday, March 21st, 2013

Computational lithography has become an integral part of design since the 130 nm process node. New techniques continue to be developed to extend the steady node shrink year after year.

To read this white paper, click here.

A Call To Action: How 20nm Will Change IC Design

Thursday, February 21st, 2013

The 20nm process node represents a turning point for the electronics industry. While it brings tremendous power, performance and area advantages, it also comes with new challenges in such areas as lithography, variability, and complexity. The good news is that these become manageable challenges with 20nm-aware EDA tools when they are used within end-to-end, integrated design flows based on a “prevent, analyze, and optimize” methodology.

To download this white paper, click here.

EUV OPC For 56nm Metal Pitch

Thursday, October 18th, 2012

For the logic generations of the 15 nm node and beyond, the printing of pitches at 64nm and below are needed. For EUV lithography to replace ArF-based multi-exposure techniques, it is required to print these patterns in a single exposure process. The k1 factor is roughly 0.6 for 64nm pitch at an NA of 0.25, and k1  0.52 for 56nm pitch. These k1 numbers are of the same order at which model based OPC was introduced in KrF and ArF lithography a decade or so earlier. While we have done earlier work that used model-based OPC for the 22nm node test devices using EUV,1 we used a simple threshold model without further resist model calibration. For 64 nm pitch at an NA of 0.25, the OPC becomes more important, and at 56nm pitch it becomes critical. For 15 nm node lithography, we resort to a full resist model calibration using tools that were adapted from conventional optical lithography. We use a straight shrink 22 nm test layout to assess post-OPC printability.

To read more, click here.

A Hybrid Model/Pattern-Based OPC Approach For Improved Consistency And TAT

Thursday, September 20th, 2012

As the technology advances, OPC run time turns to be a big concern, and a great deal of our effort is directed toward speeding up the litho operations. In addition, the OPC simulation consistency sometimes deteriorates, which is a critical issue—especially for anchor features. On the other hand, full-chip designs usually comprise large arrays of basic cells, used by OPC engineers to tune OPC recipes, which is evident for instance for memory design and processor chips. The model-based OPC technique is not necessary for such designs, provided that the equivalent mask shapes for one cell of these arrays are already known.

In this work, we introduce a combined approach using model- and pattern-based OPC. Pattern matching is used to extract regions from full chips that match the basic designs stored in pre-created libraries. When matching occurs, the OPC solution stored in these libraries is used and populated across matched areas. Special treatment for large array boundaries is applied due to proximity effects. Model-based OPC is used for the rest of the chip. This approach has two main advantages. First, simulation consistency is greatly improved because the OPC solution for standard cells is known. And second, pattern matching is a DRC-based tool, and thus it is very fast compared to litho operations and hence TAT is further enhanced.

To download this white paper, click here.