Posts Tagged ‘Intel’
By Jeff Dorsch, contributing editor
The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium in San Jose, Calif.
Extreme-ultraviolet lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing.
On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.
There are other lithography technologies being discussed at the conference, of course. They are bit players in the drama, so to speak, although there is a lot of discussion and buzz about directed self-assembly technology this week.
ASML broke big news on Tuesday morning, reporting that Taiwan Semiconductor Manufacturing was able to expose more than 1,000 wafers in one day this year with ASML’s NXE:3300B EUV system. “During a recent test run on an NXE:3300B EUV system we exposed 1,022 wafers in 24 hours with sustained power of over 90 watts,” Anthony Yen, TSMC’s director of research and development, said at SPIE.
While ASML was obviously and justifiably proud of this milestone, after achieving its 2014 goal of producing 500 wafers per day, it cautioned that more development remains for EUV technology.
“The test run at TSMC demonstrates the capability of the NXE:3300B scanner, and moves us closer to our stated target of sustained output of 1,000 wafers per day in 2015,” ASML’s Hans Meiling, vice president service and product marketing EUV, said in a statement. “We must continue to increase source power, improve system availability, and show this result at multiple customers over multiple days.”
The day before, Cymer announced the first shipment of its XLR 700ix light source, which is said to improver scanner throughput and process stability for manufacturing chips with 14-nanometer features. The company also debuted DynaPulse as an upgrade option for its OnPulse customers. The XLR 700ix and DynaPulse together are said to offer better on-wafer critical dimension uniformity and provide stable on-wafer performance.
Another revelation at SPIE is that SK Hynix has been working with the NXE:3300, too, and is pleased with the system’s capabilities. According to Chang-Moon Lim, who spoke Monday morning, SK Hynix was recently able to expose 1,670 wafers over three days, with uptime of 86.3 percent over that period.
“Progress has been significant on various aspects, which should not be overshadowed by the delay of [light] sources,” he said of ASML’s EUV systems.
The Korean chipmaker is exploring how it could work without pellicles on the EUV reticle, Lim noted. ASML has been developing a pellicle, made with polycrystalline silicon, in cooperation with Intel and others.
Nikon Precision and other Nikon subsidiaries didn’t issue any press releases at SPIE. The companies presented much information at Sunday’s LithoVision 2015 event, held at the City National Civic auditorium, across the street from the San Jose Convention Center, where SPIE Advanced Lithography is staged.
On offer at the Nikon conference was the claimed superiority of 193i immersion lithography equipment to EUV systems for the 14nm, 7nm and future process nodes. Donis Flagello, Nikon Research Corp. of America’s president, CEO, and chief operating officer, emphasized that message on Tuesday morning with an invited paper on “Evolving optical lithography without EUV.”
Nikon’s champion machine is the NSR-S630D immersion scanner, which was touted throughout the LithoVision event. The system is capable of exposing 250 wafers per hour, according to Nikon’s Yuichi Shibazaki.
Ryoichi Kawaguchi of Nikon told attendees, “EUV lithography needs more stability and improvement.” He also brought up the topic of manufacturing on 450-millimeter wafers, which has mostly gone ignored in the lithography competition. Nikon will ship a 450mm system this spring to the Global 450 Consortium in Albany, N.Y., Kawaguchi said. The bigger substrates could provide “an alternative option to reduce cost,” he added.
Erik Byers of Micron Technology observed, “EUV is not a panacea.”
Which lithography technology will prevail in high-volume manufacturing? The question may not be definitively answered for some time.
Scott McGregor, President and CEO of Broadcom, sees some major changes for the semiconductor industry moving forward, brought about by rising design and manufacturing costs. Speaking at the SEMI Industry Strategy Symposium (ISS) in January, McGregor said the cost per transistor was rising after the 28nm, which he described as “one of the most significant challenges we as an industry have faced.” Pete Singer reports.
Matthew Hogan, Mentor Graphics writes a tongue-in-cheek blog about IP, saying chip designers need only to merely insert the IP into the IC design and make the necessary connections. Easy-peasey! Except…robust design requires more than verifying each separate block—you must also verify that the overall design is robust. When you are using hundreds of IPs sourced from multiple suppliers in a layout, how do you ensure that the integration of all those IPs is robust and accurate?
Dick James, Senior Analyst at Chipworks IEDM blogs that Monday was FinFET Day. He highlights three finFET papers, by TSMC, Intel, and IBM.
A research team led by folks at Cornell University (along with University of California, Berkeley; Tsinghua University; and Swiss Federal Institute of Technology in Zurich) have discovered how to make a single-phase multiferroic switch out of bismuth ferrite (BiFeO3) as shown in an online letter to Nature. Ed Korczynski reports.
SEMI praised the bipartisan effort in the United States Congress to pass the Revitalize American Manufacturing and Innovation (RAMI) Act as part of the year-end spending package. Since its introduction in August 2013, SEMI has been a champion and leading voice in support of the bill that would create public private partnerships to establish institutes for manufacturing innovation.
Phil Garrou takes a look at some of the key presentations at the 2014 IEEE 3DIC Conference recently held in Cork, Ireland.
Adele Hars writes that there were about 40 SOI-based papers presented at IEDM. In Part 1 of ASN’s IEDM coverage, she provides a rundown of the top SOI-based advanced CMOS papers.
Karen Lightman of the MEMS Industry Group says power is the HOLY GRAIL to both the future success of wearables and IoT/Everything. Power reduction and management through sensor fusion, power generation through energy harvesting as well as basic battery longevity. It became very clear from conversations at the MIG conference as well as in talking with folks on the CES show floor that the issue of power is the biggest challenge and opportunity facing us now.
In order to keep pace with Moore’s Law, semiconductor market leaders have had to adopt increasingly challenging technology roadmaps, which are leading to new demands on electronic materials (EM) product quality for leading-edge chip manufacturing. Dr. Atul Athalye, Head of Technology, Linde Electronics, discusses the challenges.
By Ed Korczynski, Sr. Technical Editor
In another example of the old one-liner that “all that is old is new again,” the old technique of solid-source doping is being used by Intel for a critical process step in so-called “14nm node” finFET manufacturing. In the 7th presentation in the 3rd session of this year’s IEDM, a late news paper written by 52 co-authors from Intel titled “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588m2 SRAM Cell Size” disclosed that solid source doping was used under the fins.
As reported by Dick James of Chipworks in his blog coverage of IEDM this year, the fins have a more vertical profile compared to the prior “22nm node” and are merely 8nm wide (Fig. 1). Since Intel is still using bulk silicon wafers instead of silicon-on-insulator (SOI), to prevent leakage through the substrate these 8nm fins required a new process to make punch-through stopper junctions, and the new sub-fin doping technique uses solid glass sources. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over the prior node, and Idlin by 30% for NMOS and 38% for PMOS.
Solid glass sources of boron (B) and phosphorous (P) dopants have been used for decades in the industry. In a typical application, a lithographically defined silicon-nitride hard-mask protects areas from a blanket deposition in a tube furnace of an amorphous layer containing the desired dopant. Additional annealing before stripping off the dopant layer allows for an additional degree of freedom in activating dopants and forming junctions.
In recent years, On Semiconductor published how solid-source doping on the sidewalls of Vertical DMOS transistors enable a highly phosphorous doped path for the drain current to be brought back to the silicon surface. The company shows that phosphorous-oxy-chloride (POCl) and phospho-silicate glass (PSG) sources can both be used to form heavily doped junctions 1-2 microns deep.
The challenge for solid-source doping of 8nm wide silicon fins is how to scale processes that were developed for 1-2 microns to be able to form repeatable junctions 1-2 nm in scale. Self-aligned lithographic techniques could be used to mask the tops of fins, and various glass sources could be used. It is likely that ultra-fast annealing is needed to form stable ultra-shallow junctions.
Intel is notoriously protective of process Intellectual Property (IP) and so has almost certainly ensured that any equipment and materials suppliers who work on the solid-source doping process sign Non-Disclosure Agreements (NDA) with amendments that forbid acknowledging signing the NDA itself, so it is pointless to directly ask for any further details at this point. However, slides from John Borland’s recent presentation at the NCCAVS Junction Technology Users Group meeting provide a great overview of the publicly available information on finFET junction formation, and include the following:
…higher dopant activation can be realized at low temperatures if the junction is amorphous and recrystalized by using SPE (solid phase epitaxy) recrystalization of the junction as also shown in the data by Intel.
Also seen at IEDM this year in the 7th presentation of the Advanced Process Modules section, Taiwanese researchers—National Nano Device Laboratories, National Chiao Tung University, and National Cheng Kung University—joined with Californian consultants—Current Scientific, Evans Analytical Group—to show “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing.” They claim an ideal subthreshold swing (~60 mV/dec) at a high doping level. Poly-Si n & p JLFinFETs (W/L=10/20 nm) with SDP experimentally exhibit superior gate control (Ion/Ioff >10E6) and improved device variation.
By Jeff Dorsch, Contributing Editor
At the 60th annual International Electron Devices Meeting this week in San Francisco, there was much buzz about the 14-nanometer FinFET papers being presented by IBM and Intel. Those papers were the subject of a press release two months in advance.
Getting less attention at IEDM 2014 were the papers on sensors, microelectromechanical systems (MEMS) devices and bio-MEMS. This technology generates fewer headlines, although it is present in smartphones, fitness trackers, and many other electronic products.
Monday afternoon, December 15, saw the first MEMS-related papers presented at the conference, on nanoelectromechanical systems (NEMS) and energy harvesters. Donald Gardner of Intel, an IEEE Fellow, presented a paper on “Integrated On-Chip Energy Storage Using Porous-Silicon Electrochemical Capacitors,” which was supported by research at Florida International University and the University of Turku.
Gardner described how porous-silicon nanostructures were synthesized and passivated with titanium nitride through atomic-level deposition or with carbon through chemical vapor deposition. These coatings helped keep the porous silicon from oxidizing, he explained.
These electrochemical capacitors, an alternative to batteries, produced with the porous silicon could be used in energy harvesting and some applications in energy storage, according to the authors of the paper.
Session 8 of the IEDM conference also included a paper authored by France’s Institute of Electronics, Microelectronics and Nanotechnology (IEMN) and STMicroelectronics, “Fabrication of Integrated Micrometer Platform for Thermoelectric Measurements.” Maciej Haras presented the paper. He noted that 55 percent to 60 percent of energy used is released as waste heat. Harvesting energy from such heat could be a significant source of power generation in the future.
“Thermoelectricity is quite unpopular on the market,” Haras noted. Toxic materials, such as antimony, bismuth, lead, and tellurium, could be replaced by silicon, germanium or silicon germanium (SiGe) could to produce CMOS-compatible thermoelectrics, he said.
In energy conversion efficiency, silicon that is only 10 nanometers thick is 10 times more efficient than bulk silicon, Haras said.
Session 15 on Tuesday morning, December 16, was devoted to “Graphene Devices, Biosensors and Photonics.” This session featured some of the longest paper titles at the conference, such as “An Ultra-Sensitive Resistive Pressure Sensor Based on the V-Shaped Foam-like Structure of Laser-Scribed Graphene,” “A Semiconductor Bio-electrical Platform with Addressable Thermal Control for Accelerated Bioassay Development,” and “Label-Free Optical Biochemical Sensor Realized by a Novel Low-Cost Bulk-Silicon-based CMOS Compatible 3-Dimensional Optoelectronic IC (OEIC) Platform.”
Other papers were more direct, with shorter titles, such as “Flexible, Transparent Single-Layer Graphene Earphone,” which was about exactly that, and “An Integrated Tunable Laser Using Nano-Silicon-Photonic Circuits.”
Coming up on Tuesday afternoon is Session 22, devoted to MEMS and resonator technology, with six papers scheduled.
The nuts and bolts of MEMS and NEMS technology can be quite esoteric, yet such devices are crucial to the future of electronics.
By Jeff Dorsch, Contributing Editor
The presentations at this week’s 3D Architectures in Semiconductor Integration and Packaging conference could be summed up in a famous Facebook status: “It’s complicated.”
They also could be summed up in one word: Progress.
This year has seen tremendous progress in implementation of 3DIC technology, according to speakers at the 11th annual conference, held in Burlingame, Calif. Those who have been touting and tracking 3D chips for years are looking forward to the 2015 introduction of Intel’s Xeon Phi “Knights Landing” processor for high-performance computing, which will incorporate the Hybrid Memory Cube technology in the same package as the CPU.
Activities began Wednesday, December 10, with a preconference symposium on “2.5/3D-IC Design Tools and Flows” and “3D Integration: 3D Process Technology.” Bill Martin of E-System Design kicked off the program with a presentation on path finding, a topic addressed several times over the next two days. He emphasized that preparing for a chip design project, such as choosing the right tools, is as important as the design and implementation phases when it comes to embracing 3DIC technology.
John Ferguson of Mentor Graphics later said there is “an infrastructure problem” in the semiconductor industry when it comes to process design kits (PDKs) for 2.5D and 3D chips. Taiwan Semiconductor Manufacturing has collaborated with Mentor and other leading suppliers of electronic design automation tools to offer PDKs to TSMC foundry customers, yet the next step must be taken to have outsourced semiconductor assembly and test contractors provide packaging PDKs.
Phil Garrou, a senior consultant for Yole Developpement, said 2014 has witnessed significant progress in implementation of 3DIC technology. “We no longer need to prove performance,” he said. “The remaining issue is cost.”
Several speakers addressed the topic of the Internet of Things and how it involves 3DICs on the first day of the conference. Steven Schulz of the Silicon Integration Initiative (Si2) said 3D chip designers should think of their products not as system-on-a-chip devices, but system-on-a-stack.
Yole’s Rozalia Beica said predictions that the Internet of Things market will be worth trillions of dollars in 2022 are “overoptimistic” and that “optimism is higher than current investment.” Yole looks for the market in IoT sensors to be worth $400 billion in 2024, she said.
Samta Bonsal of the GE Software Center spoke on the Industrial Internet. “That world is huge,” she said, and predicted it will have “a bigger impact” than consumer-oriented IoT applications. Gartner says the market for all IoT chips will be worth $7.58 billion in 2015, she noted. The market research firm also forecasts that 8 billion connected devices will be shipped during 2020, encompassing 35 billion semiconductor devices produced on 6 million wafers.
E. Jan Vardaman of TechSearch International presented a lively review of 3DIC technology, past and present. “There’s been a lot of good progress with TSV (through-silicon vias), enabling us to improve the process,” she said. Still, 3DIC has been a long time in coming, noting that Micron Technology began research and development on DRAM stacking a dozen years ago and Xilinx initiated development of a silicon-based interposer to be used with TSVs in 2006, six years before it was able to offer a field-programmable gate array with such technology, manufactured in volume by TSMC.
Dyi-Chung Hu of Unimicron looked past the silicon interposer to the era to using glass for interposers and substrate core materials. Glass has a low coefficient of thermal expansion compared with silicon, he noted, and is very flat. Its chief drawback is its brittleness, according to Hu.
Michael Gaynes of IBM’s Thomas J. Watson Research Center reported on his company’s two ICECool projects for the Defense Advanced Research Projects Agency, developing 3DICs that could run cooler in data-center servers.
The last day of the conference coincided with a convention devoted to the Star Trek television series in the adjacent hotel ballroom. Attendees dressed as Klingons and starship crew members mingled with the 3DIC technologists in the hotel lobby, all dreaming and thinking about the future.
By Ed Korczynski, Sr. Technical Editor, SST/SemiMD
The good people at ChipWorks have released some of the first public data on Intel’s new 14nm-node process, and the results indicate that materials limitations in on-chip electrical interconnects are adding costs. Additional levels of metal have been added, and complex “air-gap” structures have been added to the dielectric stack. Flash memory chips have already used air-gaps, and IBM has already used a subtractive variant of air-gaps with >10 levels of metal for microprocessor manufacturing, but this is the first known use of additive air-gaps for logic after Intel announced that a fully-integrated process was ready for 22nm-node chips.
Mark Bohr of Intel famously published data in 1995 (DOI: 10.1109/IEDM.1995.499187) on the inherent circuit speed limitations of interconnects, showing proportionality to the resistance (R) of the metal lines multiplied by the capacitance (C) of the dielectric insulation around the metal (Fig.1). The RC product thus should be minimized for maximum circuit speed, but the materials used for both the metal and the dielectric insulation around metal lines are at limits of affordability in manufacturing.
There are no materials that super-conduct electricity at room temperature, and only expensive and room-sized supercomputers and telecommunications base-stations can afford to use the liquid-nitrogen cooling that is needed for known superconductors to function. Carbon Nano-Tubes (CNT) and 2D atomic-layers of carbon in the form of graphene can conduct ballistically, but integration costs and electrical contact resistances limit use. Copper metal remains as the best electrical conductor for on-chip interconnects, yet as horizontal lines and vertical vias continue to shrink in cross-sectional area the current density has reached the limit of reliability. The result is the increase in the number of metal layers to 13 for 14nm-node Intel microprocessors, while IBM used 15 layers for 22nm-node Power8 chips.
Low-k Dielectrics and Pore Sizes
The dielectric constant (“k”) of silicon oxide is ~4, and ~3.5 with the addition of fluorine to the oxide (SiOF). Carbon-Doped Oxide (CDO or SiOC or SiOC:H) with k~3.0 has been integrated well into interconnect stacks. Some polymers can provide k values in the 2.0-2.7, but they cannot be integrated into most interconnects due to lack of mechanical strength, chemical resistance, and overall stability. Air has k=1, and there have been specialized chips made using metal wires floating in air, but lack of physical structure results in poor manufacturing yield and weak reliability.
A clever compromise is to use both SiOC with k~3 and air with k~1 in a stack, which results in an integrated k value weighted by the percent of the volume taken up by each phase. Porous Low-k (PLK) with 10% porosity allows for an integrated k of ~2.7 for modest improvement, but increasing porosity to just 20% for k~2.4 results in connected random pores that reduce reliability. To reliably integrate 20-30% air into SiOC, the pores cannot be random but must be engineered as discrete gaps in the structure.
In 2007, IBM announced that it would engineer air-gaps in microprocessors, but the company claimed to be using an extremely complex process for integration involving a self-assembled thin-film mask to anisotropically etch out holes between lines and then further isotropic etching to form elongated pores. Though relatively complex and expensive, this process allows for the use of any 2D layout for lines in a given metal layer.
Additive Air-gap Process-Design Integration
For fab lines that are still working with aluminum metal and additive dielectrics, air-gaps are a defect that occurs with imperfect dielectric fill. When not planned as part of the design, air-gaps formed in a lower-layer can be exposed to etchants during subsequent processing resulting in metal shorts or opens. However, Figure 2 shows that it is possible to engineer air-gaps by Chemical-Vapor Deposition (CVD) of dielectric material into line-space structures with proper process control and design layout restrictions. Twenty years ago, this editor worked for an OEM on CVD processes for dielectric fill, and the process can be tuned to be highly repeatable and relatively low-cost if a critical masking step can be avoided. In 1998, Shieh et al. from Stanford (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) showed proof-of-concept for this approach to lower k values.
Four years ago at IEDM 2010, Intel presented details of how to engineer air-gaps using CVD. As this editor wrote at that time in an extensive analysis:
The lithographic masking step is needed for two reliability reasons. First, by excluding air-gap formation in areas near next-layer vias, alignment between layers can be more easily done. Second, wide spaces are excluded where the final non-conformal CVD step wouldn’t automatically pinch-off to close the gaps; leaving full SiOC(H) in wider spaces also helps with mechanical strength. The next layer is patterned with a conventional dual-damascene flow, with the option to add air-gaps.
Now we know that Intel kept air-gaps on the metaphorical shelf by skipping use at the 22nm-node. The 2014 IEDM paper from Intel will discuss details of 14nm-node air-gaps: two levels at 80nm and 160nm minimum pitches, yielding a 17% reduction in capacitance delays.
This process requires regularly spaced 1D line arrays as a design constraint, which may also be part of the reason for additional metal layers to allow for 2D connections through vias. Due to lithography resolution advantages with 1D “gridded” layouts, other logic fabs may soon run 1D designs at which point additive air-gaps like that used by Intel will provide a relatively easy boost to IC speeds.
SEMI’s Strategic Materials Conference was held September 30-October 1, 2014, in Santa Clara, CA at the Biltmore hotel.
By Karey Holland, Techcet Group
The 2014 Strategic Materials Conference was very well attended. There were people from several of the leading IC makers as well as suppliers of equipment and materials to the fabs. Unfortunately, the audio and video systems were not stellar, so we had to endure some ear shattering system noise, and any light image was not visible on the screens. Otherwise, the venue was good. Throughout the conference, several themes were repeated.
Focus on the stability we hope for in post 2013 times, but concern about volatility and uncertainty of the world economics, esp. the recession-like growth numbers in Europe and Japan expected for the next few years. While forecasters (Gartner, IC Insights, VLSI Research, Linx, Techcet Group and others) anticipate IC wafer starts growing at ≥6% CAGR over the next 5 years, there is concern that any number of geo political world problems could throw us back into a global recession. Attendees had a greater concern than the presenters over the possibility of a future recession, and that the impact would be greater to IC industry now due to the entrenchment of mobile platforms.
Focus on cost of lithography as a driver for increased cost of leading edge MCUs/MPUs … with current nodes, multi-patterning requires many more expose/develop/dep/etch steps than EUV, but EUV has not yet met the requirements for manufacturing implementation. It is likely that EUV will first be used for only a few critical layers. DSA (directed self-assembly) may be used also for a few selected critical layers, but issues of defects will likely keep it from use in many layers.
Focus on the expected (and currently numerous options) for advanced devices and implications for materials. This includes advanced packaging technologies.
450mm wafers may continue to slip, if the other large IC makers (e.g. TSMC, Samsung, GlobalFoundries) don’t agree with Intel on first implementation date/node. Collaboration across the entire ecosystem was stressed for 450mm to become a reality.
Below are things I found particularly interesting in the presentations and/or at the end of day panel discussions.
The key note presentation, “Materials Innovation for the Digital 6th Sense Era,” was by Matt Nowak of Qualcomm. He discussed both the vision of the Internet of Things (IoT), the required IC devices (including analog & sensors) and implications to materials (and cost to manufacture) from these new IC devices; a perfect start to SMC 2014. Qualcomm defines the Digital 6th Sense Era is “the augmentation of human ability”, or as Sue Davis put it “intelligent data based extension of our 5 senses ==>to a 6th“. Essentially this is where the ability of the IoT/IoE data feedback can act as our 6th sense by capturing data about one & one’s environment which results in prediction/information being shared based on data collection and/or user selections regarding the environment around us (or about us, e.g., tele-health).” Because the smartphone is the “most pervasive platform ever” (US Android users average 106 Apps launched/day), it can serve as a remote connection to the IoT world … be that monitoring our health, schedules, honey-do lists, and improving our understanding and enjoyment of the world around us. For advanced logic one might expect, lithography for advanced ICs (quad patterning vs EUV) were discussed as key cost drivers. Other required/expected advanced materials include high mobility channel materials and thin barrier metals (likely Co). Beyond CMOS, new structures and materials may be required to support sensors (bio, chemical, fluidic), nano batteries, piezo, thermal, and solar harvesters.
Mark Thirsk, Linx-Consulting, reviewed IC growth and lack thereof for past years, and observed that 2014 will be “first good year in 8 years” (since 2006), and forecast 6-8% CAGR for the next few years – strongly dependent on the success of the IoT. IC market growth since 2010 correlates strongly to GDP since 2010, and thus regional GDP differences (e.g. the current European recession) are reflected in IC demand. Technology challenges & opportunities in for the next 5+ years include advanced logic (3D NAND, and new memory method after 2018), numerous AL (atomic layer) processes, 3D / advanced packaging, patterning efficiency, and complexity. The electronic materials landscape is changing: the supply chain is merging, and there are new entrants (esp. from Korea, Taiwan & China) in advanced materials such as photoresists. Interestingly, China appears to be focusing more on investing in fabless than fabs.
Duncan Meldrum, Hilltop Economics, said that the current subdued market growth (3% 2013-16) is due to more fiscal responsible people. China & Asia are growing 4 to 7.7%, US & Latin America about 2.1 to 3.1, Euro <2%, and Japan ~1.5%. The tax increase in Japan is having a very negative impact. He expects the US to see a 5% year over year improvement (very good news) with our investments finally growing in 2nd half of 2014. He anticipates healthy, but not stellar consumer spending through 2016.
Patrick Ho, Stifel Nicolas, initially discussed that for companies that follow Moore’s Law, that it is increasingly Fab capital intensity (Capex) with addition of FinFETs, new materials (e.g. High k), 3D NAND, and Multi-Patterning (from delayed EUV). One can assume this will continue to be the case as CMOS devices moves from Si channel to replacement channel filled with SiGe, Ge, or III-V and memories move to new technologies such as ReRAM, STTRAM, etc. His observation is that only Intel is pulling for 450mm, and if TSMC & Samsung don’t exert more pull, 450mm may not happen (esp. in light of the negative impact to equipment revenue per square inch of silicon). The top 4 OEMs (ASML, KLA-T, Lam, AMAT) are large enough to push back on the top 3 IC makers, and that consolidation is continuing. Patrick noted that all 4 top OEMs have dividends, and he anticipates that they will eventually get better valuations. He showed a nice list of companies he thinks are acquisition candidates (CMC, Nanometrics, Nikon, Nova, Axcelis, Rudolph, Veeco, FormFactor, and Ultratech). Other comments: Moore’s law lives, but is under stress. Innovation w/ or w/o EUV will bring industry back to Moore’s Law. Changing landscape will help economics of leading players.
Ross Kozarsky, who leads Lux Research’s advanced materials team, discussed the longer range materials he investigates such as graphene, 3D printing, and Meta-materials. Graphene film sheets are of interest for transparent conductive materials (e.g. touchscreens), possibly moving to FETs & sensors. 3D printing has been around 30 yrs; today it’s used mostly for prototyping, but manufacturing use makes sense and could really increase total growth. Multifunctional and multi-materials printers will be needed. Autonomous cars are now a big growth opportunity, opening great opportunity for chemical and material companies to innovate.
Geraud Duboix, IBM Almaden, develops porous low k materials for interconnect passivation and their integration (esp. plasma damage). In the 0.65 to 0.1um timeframe, interconnect RC delay was slowing devices even though the transistors were getting faster, and thus began the drive for lower k insulators. The ITRS has been showing the need for lower k since its inception, but it also has pushed out the date of the more aggressive low ks. Initially to achieve lower k, C and F were added to SiO2 to break-up network structure. Today, they are driving low k down by adding porosity. Once a big concern, Geraud said that ULK mechanical properties are now no longer a concern with UV treatment, the lowest k being integrated is 2.3-2.4, and new low k materials are emerging. Geraud is working on porous low k materials, to achieve lower k, and larger pores deliver lower k. He discussed the various pore-sizes in evaluation, the importance of porogens (material in the low k deposition that is later removed to create pores) and methods being used to seal the created pores (especially before conformal barrier metal deposition). Interestingly, he commented that creating and sealing the larger pores is somewhat easier, although he’s being asked to work on the smaller pores for now. During the panel discussion Mansour Moinpour (Intel) asked why Geraud was working on smaller pores that are more difficult to fill. Geraud responded that for the designers insulators with 2.0 or 1.8 k would be too big a change and they want 2.4 and 2.2 first.
Todd Younkin, from Intel’s central research (components) novel materials group, discussed that the industry will continue CMOS Scaling through 7nm. As stated by others, lithography is a challenge and using several methods to accomplish patterning, while productivity and pattern placement (alignment) are concerns. Intel is working on devices with channels of higher mobility materials that Si (III-V or MoS2) as well as beyond CMOS (e.g., GAA) devices. Todd said that early in device research development, Intel works to make sure manufacturing should be capable of meeting cost expectations. These include the cost of multi-patterning versus EUV, ultra-low k interconnect materials, etc.
Angela Franklin, of TriQuint (recently renamed Qorvo) discussed the challenges of supply management (and unlike others, she projects well when talking, so we could avoid the audio system problems … thanks Angela!). Angela educated the audience about Qorvo devices (some look more like MEMS with permanent epoxy “cavity” structures that resonate w/ the RF) which are significantly different from the leading edge logic and non-volatile most of us follow. Unlike the device manufactures that use Si, Qorvo uses smaller substrates of III-V and GaN. Many films are already on the substrates when purchased. The fab process is very solvent intensive, and only 1/3 aqueous. Unlike others, Qorvo uses significant eBeam lithography with up to 28 different resists and many negative resists, as well as metal lift-off (my first job at IBM >30 yrs ago).
Prof. Philip Wong of Stanford gave his typical dynamic and mind-stretching presentation. His discussion was focused on the single digit nodes, and the possible new channel materials for logic (III-V or 2D MoS2, MoSe2, WSe2, WTe2 or ??) and possible new devices, including carbon nanotube FET (CNFET), STTRAM, CBRAM, ReRAM (using HfOx, TaOx, TiOx). He said that memory chips will hold 32Tbits. He then smiled and said “none of this before the next 10 years”. He showed some exciting interleaved memory and logic ideas using a base of 2D or 3D FETs, topped by STTRAM, then 2D or 3D FETs, and then 3D RRAM. Because the interconnects of the bottom device are present, all processing for the others must be at low temperature (<400C).
Discussion Panel. When asked about collaboration with materials suppliers, Intel and IBM research had significantly different responses. Intel invests dollars and works with graduate students on advanced projects and hopefully a “lucky accident” brings advances. IBM research mentioned that legal issues often get in the way of collaboration with suppliers.
Notes for SMC Day 2 2014 Blog
Tim Hendry, from Intel’s supply management team started off day 2. A large concern he brought up was what he described as the widening connections between fab, material suppliers, and sub-suppliers. He then discussed the concerns and possible ways to improve connections, as well as the importance of metrology and verification of chemical quality. Unfortunately, some of the sub-suppliers are very big chemical companies that have difficulty getting excited about the low volume materials used to make ICs. He finished up by saying that Intel is focused on controlling the costs of manufacturing that require close partnerships with materials suppliers. Intel is driving for unprecedented collaboration among the materials and sub tier suppliers to achieve cost, performance and defect targets. The cost of packaging and shipping materials globally is driving investigation into new operating models to cut costs.
Dennis Hausmann of LamRC/NVLS discussed ALD/CVD in more details than others. For Each CVD/ALD step, an average of $2-$3/wafer is added to manufacturing cost, while only about $1/wafer of this is for chemistry+power+exhaust management. He reviewed at least 4 versions of ALD tools (furnaces to single wafer) and said that there is a “right ALD tool” for the right deposition job. He said that single wafer tools with proper development can meet same throughput as batch furnaces. However, if you look at the development cost, single wafer tools are much better in cost. For depositions that improve with plasma ALD, single wafer tools also make sense. An important observation by Dennis was that for ALD, sometimes it is the unknown contaminant that “makes it go”. This is something that has been observed in the past of copper plating chemistries, as well as some CMP slurries.
James ONeil, CTO Entegris had an interesting title, which should fit most suppliers “Accelerating yield in a disruptive environment”. James emphasized that suppliers need meaningful process discussions, insights & collaboration with their customers.
Adrienne Pierce of Edwards introduced SCIS collaboration to most of us. This is a supply chain collaboration working group. Some topics are tracing defects origins and BKMs for specific process (e.g. ALD).
There were then two parallel sessions; one on advanced memories and the other on 3D packaging. In the memory session, Norma Sosa of IBM talked about PCRAM (phase change memory, which Micron has been shipping for a few years now), Mark Raynor, Matheson, discussed RRAM for Non-Volatile, and Suresh Upa, SanDisk, discussed packaging implications.
After the breakout, we had presentations from four materials supplier companies. The four same very similar things. Dave Bern of Dow Chemical discussed using the “right tool” for collaboration and the importance of making sure suppliers agree to work in areas that fit their “core competencies”. Wayne Mitchel of Air Products noted that ICs are only 2% of GDP. He agreed with Dave Bern that suppliers should only agree to work (partner) with customer on areas within expertise, otherwise it takes too much time and money to execute successfully. Jean Marc Girard, Air Liquide discussed the numerous risks of supply chain, from the sub-supplier, the environment (e.g. earthquakes), and materials stability (or lack thereof). Kevin O’Shea of SAFC Hitech emphasized that taking materials from a catalog of low volume and ramping to IC manufacturing needs is not trivial, and may also not be consistent with the materials manufacturer (the sub-supplier, or company that is “primary” in the materials).
The day 2 Panel discussion had more audience participation. Some discussions I found particularly interesting are discussed below.
Tim (Intel) said the gap is getting wider between Intel, suppliers, sub-suppliers (esp. customs for IC industry). The large sub-supplier that doesn’t have an interest in moving forward – there is no motivation to increase metrology, metrics, etc. The shrinking sub-supplier base isn’t good for our industry – reduction in cost per bit comes from shrinks and reuse of capital, not only lower cost materials..
Kurt Carlson said that sub suppliers don’t think IC fabrication is the best industry – the IC industry wants more and more, yet wants to pay less and less. It’s not worth it to us (good sub-suppliers leave because it’s too costly for the small volumes).
Jean Marc said they don’t want to duplicate development costs, if they don’t need to; they would rather use universities and share on things like toxicology.
Dave said it costs millions of dollars to test materials, like EUV.
Mansour Moinpour asked about collaboration on liquid particle, GCMS, and similar – can we have joint & consistent measurements across the industry? James Entegris responded that end user need to be drivers. Jean Marc suggested that maybe SEMI standards could drive a standard of industrial analytics.
The value of roadmaps was very different to the various participants, however the idea of regulatory alignment and a roadmap related to this was generally thought to be useful.
The question of cost and logistics … there are some materials that require shipping a lot of water, which adds cost. Intel said that they are getting into more cost sensitive mobile market and they may be driven to this rather than exact materials copy in near future. Tim said the Intel CEO is “hell bent” that Intel will make money in the mobile market. “Intel will pull it off.”
Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.
Even with the wide variety of topics on offer at the Monterey Conference Center, many discussions circled back to EUV lithography. After years of its being hailed as the “magic bullet” in semiconductor manufacturing, industry executives and engineers are concerned that the technology will have a limited window of usefulness. Its continued delays have led some to write it off for the 10-nanometer and 7-nanometer process nodes.
EUV photomasks were the subject of three conference sessions and the focus of seven posters. There were four posters devoted to photomask inspection, an area of increasing concern as detecting and locating defects in a mask gets more difficult with existing technology.
The conference opened Tuesday, Sept. 16, with the keynote presentation by Martin van den Brink, the president and chief technology officer of ASML Holding. His talk, titled “Many Ways to Shrink: The Right Moves to 10 Nanometer and Beyond,” was clearly meant to provide some reassurance to the attendees that progress is being made with EUV.
He reported his company’s “30 percent improvement in overlay and focus” with its EUV systems in development. ASML has shipped six EUV systems to companies participating in the technology’s development (presumably including Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing, which have made equity investments in ASML), and it has five more being integrated at present, van den Brink said.
The light source being developed by ASML’s Cymer subsidiary has achieved an output of 77 watts, he said, and the company expects to raise that to 81 watts by the end of 2014. The key figure, however, remains 100 watts, which would enable the volume production of 1,000 wafers per day. No timeline on that goal was offered.
The ASML executive predicted that chips with 10nm features would mostly be fabricated with immersion lithography systems, with EUV handling the most critical layers. For 7nm chips, immersion lithography systems will need 34 steps to complete the patterning of the chip design, van den Brink said. At that process node, EUV will need only nine lithography steps to get the job done, he added.
Among other advances, EUV will require actinic mask inspection tools, according to van den Brink. Other speakers at the conference stressed this future requirement, while emphasizing that it is several years away in implementation.
Mask making is moving from detecting microscopic defects to an era of mesoscopic defects, according to Yalin Xiong of KLA-Tencor. Speaking during the “Mask Complexity: How to Solve the Issues?” panel discussion on Thursday, Sept. 18, Xiong said actinic mask inspection will be “available only later, and it’s going to be costly.” He predicted actinic tools will emerge by 2017 or 2018. “We think the right solution is the actinic solution,” Xiong concluded.
Peter Buck of Mentor Graphics, another panelist at the Sept. 18 session, said it was necessary to embrace mask complexity in the years to come. “Directed self-assembly has the same constraints as EUV and DUV (deep-ultraviolet),” he observed.
People in the semiconductor industry place high values on “good,” “fast,” and “cheap,” Buck noted. With the advent of EUV lithography and its accompanying challenges, one of those attributes will have to give way, he said, indicating cheapness was the likely victim.
Mask proximity correction (MPC) and Manhattanization will take on increasing importance, Buck predicted. “MPC methods can satisfy these complexities,” he said.
For all the concern about EUV and the ongoing work with that technology, the panelists looked ahead to the time when electron-beam lithography systems with multiple beams will become the litho workhorses of the future.
Mask-writing times were an issue touched upon by several panelists. Shusuke Yoshitake of NuFlare Technology reported hearing about a photomask design that took 60 hours to write. An extreme example, to be sure, but next-generation multi-beam mask writers will help on that front, he said.
Daniel Chalom of IMS Nanofabrication said that with 20nm chips, the current challenge is reduce mask-writing times to less than 15 hours.
In short, presenters at the SPIE conference were optimistic and positive about facing the many challenges in photomask design, manufacturing, inspection, metrology, and use. They are confident that the technical hurdles can be overcome in time, as they have in the past.
By Dr. Phil Garrou, Contributing Editor, Solid State Technology
Intel has just announced that Embedded Multi-die Interconnect Bridge (“EMIB”) packaging technology will be available to 14nm foundry customers. Claiming it is a “…lower cost and simpler 2.5D packaging approach for very high density interconnects between heterogeneous dies on a single package.” [link]
Intel released the following description “Instead of an expensive silicon interposer with TSV (through silicon via), a small silicon bridge chip is embedded in the package, enabling very high density die-to-die connections only where needed. Standard flip-chip assembly is used for robust power delivery and to connect high-speed signals directly from chip to the package substrate. EMIB eliminates the need for TSVs and specialized interposer silicon that add complexity and cost.”
It is highly likely that this is tied to the issuance of patent application publication US 2014/0070380 A1 published March 13 2014.
In simplified form interconnect bridges (“silicon glass or ceramic”) are embedded in a laminate substrate and connected with flip chip as shown below.
A cross section of the package is more revealing showing connections through the laminate and connections through the bridge substrate (316) which would be TSV in the case of a silicon bridge substrate. The underside of the bridge substrate (314) may be connected to another bridge substrate for further interconnect routing as shown below.
While there is no silicon interposer, there do appear to be TSV in the embedded interconnect substrate as shown below. While removing complexity from the IC fabrication by eliminating TSV from the foundry process, the packaging operation becomes much more complex.
Since the 2.5D interposer has been reduced in size to the interconnect bridges this may reduce cost, but will increase signal length vs a true 3D stack or a silicon interposer 2.5D.
Further details will be discussed in a future IFTLE blog.
Graphene meets heat waves; UT Dallas technology could make night vision, thermal imaging affordable; Breakthrough in OLED technology
A new spin on spintronics; Novel solid-state nanomaterial platform enables terahertz photonics; Novel crumpling method takes flat graphene from 2-D to 3-D
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.