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Intel Announces “New Interconnect” for 14nm

Tuesday, September 2nd, 2014

By Dr. Phil Garrou, Contributing Editor, Solid State Technology

Intel has just announced that Embedded Multi-die Interconnect Bridge (“EMIB”) packaging technology will be available to 14nm foundry customers. Claiming it is a “…lower cost and simpler 2.5D packaging approach for very high density interconnects between heterogeneous dies on a single package.” [link]

Intel released the following description “Instead of an expensive silicon interposer with TSV (through silicon via), a small silicon bridge chip is embedded in the package, enabling very high density die-to-die connections only where needed. Standard flip-chip assembly is used for robust power delivery and to connect high-speed signals directly from chip to the package substrate. EMIB eliminates the need for TSVs and specialized interposer silicon that add complexity and cost.”

It is highly likely that this is tied to the issuance of patent application publication US 2014/0070380 A1 published March 13 2014.

In simplified form interconnect bridges (“silicon glass or ceramic”) are embedded in a laminate substrate and connected with flip chip as shown below.

Bridge Interconnect as described in recent Intel patent.

A cross section of the package is more revealing showing connections through the laminate and connections through the bridge substrate (316) which would be TSV in the case of a silicon bridge substrate. The underside of the bridge substrate (314) may be connected to another bridge substrate for further interconnect routing as shown below.

While there is no silicon interposer, there do appear to be TSV in the embedded interconnect substrate as shown below. While removing complexity from the IC fabrication by eliminating TSV from the foundry process, the packaging operation becomes much more complex.

Since the 2.5D interposer has been reduced in size to the interconnect bridges this may reduce cost, but will increase signal length vs a true 3D stack or a silicon interposer 2.5D.

Further details will be discussed in a future IFTLE blog.

Intel EMIB Module in Cross Section

The Week in Review: August 29, 2014

Friday, August 29th, 2014

Intel Corporation announced two new technologies for Intel Custom Foundry customers that need cost-effective advanced packaging and test technologies.

Fairchild Semiconductor, a supplier of high performance power and mobile products, today announced it will eliminate its internal five-inch and significantly reduce six-inch wafer fabrication lines, resulting in the closure of its manufacturing and assembly facilities in West Jordan, Utah and Penang, Malaysia, as well as the remaining five-inch wafer fabrication lines in Bucheon, South Korea.

KLA-Tencor Corporation released two metrology tools and an upgraded data analysis system that can reduce overlay error by 25% when using multi-patterning in leading-edge IC fabs. By taking additional data and using feed-forward control loops, the integrated solution dynamically adjusts the exposures in lithographic steppers to improve both overlay and critical dimension (CD) results in high-volume manufacturing (HVM).

United Microelectronics Corporation (UMC) and Fujitsu Semiconductor Limited announced an agreement for UMC to become a minority shareholder of a newly formed subsidiary of Fujitsu Semiconductor that will include its 300mm wafer manufacturing facility located in Kuwana, Mie, Japan.

Scientists have developed what they believe is the thinnest-possible semiconductor, a new class of nanoscale materials made in sheets only three atoms thick.

SEMI announced the keynotes for the 2nd Vietnam Semiconductor Strategy Summit (September 16-17), an executive conference focused on Vietnam’’s growing role in the global semiconductor industry.

Solid State Watch: August 22-28, 2014

Friday, August 29th, 2014
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The Week in Review: August 22, 2014

Friday, August 22nd, 2014

Himax Technologies, Inc., a supplier and fabless manufacturer of display drivers and other semiconductor products, and Lumus, a producer of Augmented Reality glasses, announced another joint initiative to continue developing the next-generation of smart glasses that will set new technological standards in image quality and performance.

North America-based manufacturers of semiconductor equipment posted $1.41 billion in orders worldwide in July 2014 (three-month average basis) and a book-to-bill ratio of 1.07, according to the July EMDS Book-to-Bill Report published this week by SEMI.   A book-to-bill of 1.07 means that $107 worth of orders were received for every $100 of product billed for the month.

Intel Corporation and Unity Technologies this week announced a strategic collaboration to advance the development of Android-based applications on Intel architecture. The agreement accelerates Intel’s mobility push as millions of developers using the Unity development platform can now bring native Android games and other apps to Intel-based mobile devices. Unity adds support for Android across all of Intel’s current and future processors including both the Intel Core and Intel Atom processor families.

MediaTek this week announced the establishment of a new research and development facility in Bengaluru, India. The new R&D facility will focus on developing innovative and inclusive solutions for wireless communications and establish MediaTek’s presence in other core segments such as connectivity and home entertainment devices.

Amkor Technology, Inc. announced that David Watson has been appointed as a new member of the Company’s Board of Directors. With this appointment, Amkor’s Board has been expanded to nine members. Mr. Watson is currently serving as Executive Vice President and Chief Operating Officer for Comcast Cable. In this role Mr. Watson oversees the teams responsible for day-to-day operations of the cable division, including sales and marketing of cable video, high-speed Internet and voice services, as well as oversight of the three operating divisions and Comcast Spotlight, the advertising sales unit.

STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, announced this week that it has shipped over 100 million semiconductor packages with the company’s fcCuBE technology, advanced flip chip packaging with fine pitch copper (Cu) column bumps, Bond-on-Lead (BOL) interconnection and enhanced assembly processes.

Intersil Corporation, a provider of power management and precision analog solutions, announced the ISL98611 display power and LED driver for smartphones. The ISL98611 is the first power management IC that integrates the display power and backlight LED driver functions in a single chip. It significantly improves efficiency of both functions to increase smartphone battery life by an hour or more.

Research Alert: August 5, 2014

Tuesday, August 5th, 2014

Taking great ideas from the lab to the fab

A “valley of death” is well-known to entrepreneurs–the lull between government funding for research and industry support for prototypes and products. To confront this problem, in 2013 the National Science Foundation (NSF) created a new program called InTrans to extend the life of the most high-impact NSF-funded research and help great ideas transition from lab to practice.

In partnership with Intel Corporation, NSF announced the first InTrans award of $3 million to a team of researchers who are designing customizable, domain-specific computing technologies for use in healthcare.

The work could lead to less exposure to dangerous radiation during x-rays by speeding up the computing side of medicine. It also could result in patient-specific cancer treatments.

Led by the University of California, Los Angeles, the research team includes experts in computer science and engineering, electrical engineering and medicine from Rice University and Oregon Health and Science University. The team comes mainly from the Center of Domain-Specific Computing (CDSC), which was supported by an NSF Expeditions in Computing Award in 2009.

Expeditions, consisting of five-year, $10 million awards, represent some of the largest investments currently made by NSF’s Computer, Information Science and Engineering (CISE) directorate.

Today’s InTrans grant extends research efforts funded by the Expedition program with the aim of bringing the new technology to the point where it can be produced at a microchip fabrication plant (or fab) for a mass market.

National Science Foundation tests out the assembly line of the future

There’s no shortage of ideas about how to use nanotechnology, but one of the major hurdles is how to manufacture some of the new products on a large scale. With support from the National Science Foundation (NSF), University of Massachusetts (UMass) Amherst chemical engineer Jim Watkins and his team are working to make nanotechnology more practical for industrial-scale manufacturing.

One of the projects they’re working on at the NSF Center for Hierarchical Manufacturing (CHM) is a roll-to-roll process for nanotechnology that is similar to what is used in traditional manufacturing. They’re also designing a process to manufacture printable coatings that improve the way solar panels absorb and direct light. They’re even investigating the use of self-assembling nanoscale products that could have applications for many industries.

“New nanotechnologies can’t impact the U.S. economy until practical methods are available for producing products, using them in high volumes, at low cost. CHM is researching the fundamental scientific and engineering barriers that impede such commercialization, and innovating new technologies to surmount those barriers,” notes Bruce Kramer, senior advisor in the NSF Engineering Directorate’s Division of Civil, Mechanical and Manufacturing Innovation (CMMI), which funded the research.

“The NSF Center for Hierarchical Manufacturing is developing platform technologies for the economical manufacture of next generation devices and systems for applications in computing, electronics, energy conversion, resource conservation and human health,” explains Khershed Cooper, a CMMI program director.

“The center creates fabrication tools that are enabling versatile and high-rate continuous processes for the manufacture of nanostructures that are systematically integrated into higher order structures using bottom-up and top-down techniques,” Cooper says. “For example, CHM is designing and building continuous, roll-to-roll nanofabrication systems that can print, in high-volume, 3-D nanostructures and multi-layer nanodevices at sub-100 nanometer resolution, and in the process, realize hybrid electronic-optical-mechanical nanosystems.”

New material allows for ultra-thin solar cells

Extremely thin, semi-transparent, flexible solar cells could soon become reality. At the Vienna University of Technology, Thomas Mueller, Marco Furchi and Andreas Pospischil have managed to create a semiconductor structure consisting of two ultra-thin layers, which appears to be excellently suited for photovoltaic energy conversion.

Several months ago, the team had already produced an ultra-thin layer of the photoactive crystal tungsten diselenide. Now, this semiconductor has successfully been combined with another layer made of molybdenum disulphide, creating a designer-material that may be used in future low-cost solar cells. With this advance, the researchers hope to establish a new kind of solar cell technology.

The solar cell’s layer system: two semiconductor layers in the middle, connected to electrodes on either side.

Two-Dimensional Structures

Ultra-thin materials, which consist only of one or a few atomic layers are currently a hot topic in materials science today. Research on two-dimensional materials started with graphene, a material made of a single layer of carbon atoms. Like other research groups all over the world, Thomas Mueller and his team acquired the necessary know-how to handle, analyse and improve ultra-thin layers by working with graphene. This know-how has now been applied to other ultra-thin materials.

“Quite often, two-dimensional crystals have electronic properties that are completely different from those of thicker layers of the same material”, says Thomas Mueller. His team was the first to combine two different ultra-thin semiconductor layers and study their optoelectronic properties.

Two Layers with Different Functions

Tungsten diselenide is a semiconductor which consists of three atomic layers. One layer of tungsten is sandwiched between two layers of selenium atoms. “We had already been able to show that tungsten diselenide can be used to turn light into electric energy and vice versa”, says Thomas Mueller. But a solar cell made only of tungsten diselenide would require countless tiny metal electrodes tightly spaced only a few micrometers apart. If the material is combined with molybdenium disulphide, which also consists of three atomic layers, this problem is elegantly circumvented. The heterostructure can now be used to build large-area solar cells.

When light shines on a photoactive material single electrons are removed from their original position. A positively charged hole remains, where the electron used to be. Both the electron and the hole can move freely in the material, but they only contribute to the electrical current when they are kept apart so that they cannot recombine.

To prevent recombination of electrons and holes, metallic electrodes can be used, through which the charge is sucked away – or a second material is added. “The holes move inside the tungsten diselenide layer, the electrons, on the other hand, migrate into the molybdenum disulphide,” says Thomas Mueller. Thus, recombination is suppressed.

This is only possible if the energies of the electrons in both layers are tuned exactly the right way. In the experiment, this can be done using electrostatic fields. Florian Libisch and Professor Joachim Burgdörfer (TU Vienna) provided computer simulations to calculate how the energy of the electrons changes in both materials and which voltage leads to an optimum yield of electrical power.

Tightly Packed Layers

“One of the greatest challenges was to stack the two materials, creating an atomically flat structure”, says Thomas Mueller. “If there are any molecules between the two layers, so that there is no direct contact, the solar cell will not work.” Eventually, this feat was accomplished by heating both layers in vacuum and stacking it in ambient atmosphere. Water between the two layers was removed by heating the layer structure once again.

Part of the incoming light passes right through the material. The rest is absorbed and converted into electric energy. The material could be used for glass fronts, letting most of the light in, but still creating electricity. As it only consists of a few atomic layers, it is extremely light weight (300 square meters weigh only one gram), and very flexible. Now the team is working on stacking more than two layers – this will reduce transparency, but increase the electrical power.

Blog review June 30, 2014

Monday, June 30th, 2014

Pete Singer blogs that at The ConFab last week, IBM’s Gary Patton gave us three reasons to be very positive about the future of the semiconductor industry: an explosion of applications, the rise of big data and the need to analyze all that data.

Tony Chao of Applied Materials writes that Applied Ventures will be participating in the second-annual Silicon Innovation Forum (SIF) held in conjunction with SEMICON West 2014 in San Francisco on Tuesday, July 8. The forum is designed to bring new and emerging innovators together with the semiconductor industry’s top strategic investors and venture capitalists (VCs), in order to enable closer collaboration and showcase the next generation of entrepreneurs in microelectronics.

Adele Hars of ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news. Malier said that CEA-Let has been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development.

Phil Garrou blogs that last week at the 2014 ISC (International Supercomputing Conference) it was announced that the Intel Xenon Phi processor “Knights Landing” would debut in 2015. It will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can work on up to four threads per core.

Solid State Watch: May 30-June 5, 2014

Friday, June 6th, 2014
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The Week in Review: June 6, 2014

Friday, June 6th, 2014

After two years of decline, fab equipment spending for Front End facilities in 2014 is expected to increase 24 percent in 2014 (US$35.7 billion), according to the May 2014 SEMI World Fab Forecast Report released this week.

This week, the Society for Information Display (SID) unveiled the winners of its prestigious 19th annual Display Industry Awards.

The Semiconductor Industry Association (SIA) this week announced that worldwide sales of semiconductors reached $26.34 billion for the month of April 2014.

Imec announced this week that it is collaborating with Samsung Electronics to accelerate innovation and collaboration among technology companies and researchers working in the burgeoning mobile wearable field.

Synopsys, Inc. and Intel Corporation this week announced broad SoC design enablement for Intel’s 14nm Tri-Gate process technology for use by customers of Intel Custom Foundry.

Scouting report for materials at end of the road: 2013 ITRS

Monday, May 12th, 2014

Ed Korczynski, Sr. Technical Editor, SST/SemiMD

The IC fabrication industry is approaching the end of the road for device miniaturization, with both atomic and economic limits looming on the horizon. New materials are widely considered as key to the future of profitable innovation in ICs, so everyone from process engineers to business pundits needs to examine the Emerging Research Materials (ERM) chapter of the just published 2013 edition of the International Technology Roadmap for Semiconductors (ITRS).

The 2013 ITRS covers both near-term (2014-2020) and long-term (2020 onward) perspectives on what materials and processes would be desired to build ideal ICs (Fig. 1, Table ERM15). However, to properly understand the information in the current edition we need to consider the changes in the IC fab industry since 1992 when the first edition of the ITRS’s predecessor was published as the U.S. National Technology Roadmap for Semiconductors (NTRS).

Fig. 1

Twenty-two years ago, the industry had dozens of fabs working on next-generation technology, and with lithographic scaling dominating innovation there was broad consensus on gradual materials evolutions. Today, the industry has 3 logic fabs and about as many memory lines pushing processes to smaller geometries, and each fab may use significantly different revolutionary materials. The result today is that there is little consensus on direction for new materials, and at best we can quantify the relative benefits of choosing one or another of the many options available.

In fact, with just a few players left in the game, there is much to lose for any one player to disclose strategic plans such as the use of revolutionary materials. Mark Thirsk, managing partner with specialty materials analysts Linx Consulting, commented, “We built our business based on anonymizing and generalizing the world, and then predicting the future based on big categorical buckets. But now there are a very few number of people pushing the boundaries and we’re being asked to model specific fab processes such as those for Intel or TSMC.”

For all of the above reasons, the current ITRS might be better understood as a scouting report that quantifies the roughness of the terrain when our current roads end. Exotic materials such as graphene and indium-gallium-phosphide may be used as alternate materials for the Si channels in transistors, novel stacks of atomic-layers may be used as electrical contacts, and spintronics and single-electron devices may one day replace DRAM and Flash chips for solid-state memory chips. However,  “significant challenges” exist in integrating any of these new technologies into high-volume manufacturing.

In the near-term, Cu wires clad with various metal barriers are projected to provide the best overall performance for on-chip interconnects.  As stated in the 2013 Executive Summary, “Unfortunately no new breakthroughs are reported for interconnections since no viable materials with resistivity below copper exist. However, progress in manipulation of edgeless wrapped materials (e.g., carbon nanotubes, graphene combinations etc.) offer the promise of ‘ballistic conductors,’ which may emerge in the next decade.”

Specialty Materials Suppliers

Fig. 2

Figure 2 (Figure ERM5) shows the inherent complexity involved in the stages of developing a new chemical precursor for use in commercial IC production. The chapter summarizes the intrinsic difficulty of atomic-scale R&D for future chips as follows:

A critical ERM factor for improving emerging devices, interconnects, and package technologies is the ability to characterize and control embedded interface properties. As features approach the nanometer scale, fundamental thermodynamic stability considerations and fluctuations may limit the ability to fabricate materials with tight dimensional distributions and controlled useful material properties.

In addition to daunting technical issues with pre-cursor R&D, the business model for chemical suppliers is being strained by industry consolidation and by dimensional shrinks. Consolidation means that each fab has unique pre-cursor requirements, so there may be just one customer for a requested chemistry and no ability to get a return on the investment if the customer decides to use a different approach.

Shrinks down to atomic dimensions means that just milliliters instead of liters of chemistry may be needed. For example, atomic-layer deposition (ALD) precursor R&D requires expertise and investment in molecular- and chemical-engineering, and so significant sunk costs to create any specialty molecule in research quantities. “We’ll have an explosion of precursors required based on proprietary IP held by different companies,” reminds Thirsk. “The people who are being asked to develop the supply-chain of ever increasing specifications are simultaneously being squeezed on margin and volumes.”

For materials such as Co, Ru, La, and Ti-alloys to be used in fabs we need to develop more than just deposition and metrology steps. We will also likely require atomic-level processes for cleaning and etch/CMP, which can trigger a need for yet another custom material solution.

Established chemical suppliers—such as Air Liquide, Dow, DuPont, Linde, Praxair, and SAFC—run international businesses serving many industries. IC manufacturing is just a small portion of their businesses, and they can afford to simply walk-away from the industry if the ROI seems unattractive. “We’re finding more and more that, for example in wet cleaning chemistry, the top line of the market is flat,” cautioned Thirsk. “You can find some specialty chemistries that provide better profits, but the dynamics of the market are such that there’s reduced volume and reduced profitability. So where will the innovation come from?”

Alternate Channel Materials

With finFETs and SOI now both capable of running in fully-depleted mode, alternative materials to strained silicon are being extensively explored to provide higher MOSFET performance at reduced power. Examples include III-V semiconductors, Ge, graphene, carbon nanotubes, and other semiconductor nanowires (NW). To achieve complimentary MOS high performance, co-integration of different materials (i.e. III-V and Ge) on Si may be necessary. Significant materials issues such as defect reduction, interface chemistry, metal contact resistivity, and process integration must be addressed before such improvements can be achieved.

Nano-wire transistors

Top down fabricated nanowires (NW) are one-dimensional structures that can be derived from two-dimensional finFETs. Patterned and etched <5nm Si NW have been reported to have room temperature quantum oscillatory behavior with back-gate voltage with a peak mobility approaching ∼900 cm2/Vs. Despite extensive R&D, grown Si NW demonstrate no performance improvements over patterned-and-etched NW, and controlled growth in desired locations remains extraordinarily challenging. Overall, significant challenges must be overcome for NW to be integrated in high density, particularly when targeting laterally placed NW with surround gates and low resistance contacts.

—E.K.

Blog review April 7, 2014

Monday, April 7th, 2014

Pete Singer reveals the lineup of presenters for Session 1 of The ConFab, to be held June 22-25 in Las Vegas, and provides summaries of their talks. Speakers will be Vijay Ullal, COO, Fairchild Semiconductor; Dave Anderson, President and CEO, Novati Technologies; Gopal Rao, Senior Director Business Development, SEMATECH; Adrian Maynes, Program Manager, F450C; and Bill McClean, President, IC Insights.

Phil Garrou blogs about a variety of diverse issues this week, including GLOBALFOUNDRIES’ potential purchase of IBM’s semiconductor business, Altera’s separate deals with Intel and TSMC, why FinFET could be more expensive that more conventional CMOS strategies, as view by Handle Jones of IBS, and a new joint development program between ASE and Inotera focused on 3D IC packaging.

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