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Intel Q1 Revenue, Profit Rise; Chipmaker Will Cut Up to 12,000 Jobs

Wednesday, April 20th, 2016


By Jeff Dorsch, Contributing Editor

Intel reported net income of $2.0 billion in the first quarter, up 3 percent from a year earlier, while revenue rose 7 percent to $13.7 billion, compared with $12.8 billion one year ago.

The company also announced that it is embarking on an extended restructuring program, eliminating up to 12,000 positions around the world, a reduction in force of about 11 percent, by mid-2017. The cutbacks will include a consolidation of facilities with involuntary and voluntary departures by employees.

“Our first-quarter results tell the story of Intel’s ongoing strategic transformation, which is progressing well and will accelerate in 2016,” Intel CEO Brian Krzanich said in a statement. “We are evolving from a PC company to one that powers the cloud and billions of smart, connected computing devices.”

Intel will focus on its growth businesses – namely, data center, Internet of Things, field-programmable gate arrays, and memory – under the restructuring initiative. The company will realize cost savings of $750 million in 2016 and estimated annual savings of $1.2 billion.

“These actions drive long-term change to further establish Intel as the leader for the smart, connected world,” Krzanich stated. “I am confident that we’ll emerge as a more productive company with broader reach and sharper execution.”

Chief Financial Officer Stacy Smith told analysts the restructuring will make Intel “more agile, more efficient…and more profitable.”

Smith plans to take another post in Intel’s senior management within the next few months. He will be leading sales, manufacturing, and operations once a successor is named as CFO.

Intel said it would consider internal and external candidates for the CFO post.

The company’s second-quarter outlook calls for $13.5 billion in revenue, plus or minus $500 million, with a gross margin percentage of 61 percent. Intel will take a restructuring charge of about $1.2 billion during Q2.

A “weak PC market” in Q1 led to the Client Computing Group posting revenue of $7.5 billion, increasing 2 percent from a year ago yet down 14 percent from the fourth quarter of 2015, Smith said.

The Data Center Group realized Q1 revenue of $4.0 billion, a 9 percent gain from a year earlier. The Internet of Things Group had revenue of $651 million, up 22 percent year-over-year.

Revenue in the Non-Volatile Memory Solutions Group was $557 million, down 6 percent from a year earlier, while the Intel Security Group had Q1 revenue of $537 million, a 12 percent gain from a year ago.

The Programmable Solutions Group, formerly known as Altera (acquired by Intel in late 2015), had $359 million in revenue, not including $99 million in revenue due to acquisition-related adjustments.

Betsy Van Hoes of Wedbush Securities said, “It’s been a long time since there’s been a restructuring of the company. As they forge forward, they need to pare down and invest in the right area. As much as I hate that — it’s terrible for people who are laid off, that — for the investors it’s positive.”

EUV Resists and Stochastic Processes

Friday, March 4th, 2016


By Ed Korczynski, Sr. Technical Editor

In an exclusive interview with Solid State Technology during SPIE-AL this year, imec Advanced Patterning Department Director Greg McIntyre said, “The big encouraging thing at the conference is the progress on EUV.” The event included a plenary presentation by TSMC Nanopatterning Technology Infrastructure Division Director and SPIE Fellow Anthony Yen on “EUV Lithography: From the Very Beginning to the Eve of Manufacturing.” TSMC is currently learning about EUVL using 10nm- and 7nm-node device test structures, with plans to deploy it for high volume manufacturing (HVM) of contact holes at the 5nm node. Intel researchers confirm that they plan to use EUVL in HVM for the 7nm node.

Recent improvements in EUV source technology— 80W source power had been shown by the end of 2014, 185W by the end of 2015, and 200W has now been shown by ASML—have been enabled by multiple laser pulses tuned to the best produce plasma from tin droplets. TSMC reports that 518 wafers per day were processed by their ASML EUV stepper, and the tool was available ~70% of the time. TSMC shows that a single EUVL process can create 46nm pitch lines/spaces using a complex 2D mask, as is needed for patterning the metal2 layer within multilevel on-chip interconnects.

To improve throughput in HVM, the resist sensitivity to the 13.54nm wavelength radiation of EUV needs to be improved, while the line-width roughness (LWR) specification must be held to low single-digit nm. With a 250W source and 25 mJ/cm2 resist sensitivity an EUV stepper should be able to process ~100 wafer-per-hour (wph), which should allow for affordable use when matched with other lithography technologies.

Researchers from Inpria—the company working on metal-oxide-based EUVL resists—looked at the absorption efficiencies of different resists, and found that the absorption of the metal oxide based resists was ≈ 4 to 5 times higher than that of the Chemically-Amplified Resist (CAR). The Figure shows that higher absorption allows for the use of proportionally thinner resist, which mitigates the issue of line collapse. Resist as thin as 18nm has been patterned over a 70nm thin Spin-On Carbon (SOC) layer without the need for another Bottom Anti-Reflective Coating (BARC). Inpria today can supply 26 mJ/cm2 resist that creates 4.6nm LWR over 140nm Depth of Focus (DoF).

To prevent pattern collapse, the thickness of resist is reduced proportionally to the minimum half-pitch (HP) of lines/spaces. (Source: JSR Micro)

JEIDEC researchers presented their summary of the trade-off between sensitivity and LWR for metal-oxide-based EUV resists:  ultra high sensitivity of 7 mJ/cm2 to pattern 17nm lines with 5.6nm LWR, or low sensitivity of 33 mJ/cm2 to pattern 23nm lines with 3.8nm LWR.

In a keynote presentation, Seong-Sue Kim of Samsung Electronics stated that, “Resist pattern defectivity remains the biggest issue. Metal-oxide resist development needs to be expedited.” The challenge is that defectivity at the nanometer-scale derives from “stochastics,” which means random processes that are not fully predictable.

Stochastics of Nanopatterning

Anna Lio, from Intel’s Portland Technology Development group, stated that the challenges of controlling resist stochastics, “could be the deal breaker.” Intel ran a 7-month test of vias made using EUVL, and found that via critical dimensions (CD), edge-placement-error (EPE), and chain resistances all showed good results compared to 193i. However, there are inherent control issues due to the random nature of phenomena involved in resist patterning:  incident “photons”, absorption, freed electrons, acid generation, acid quenching, protection groups, development processes, etc.

Stochastics for novel chemistries can only be controlled by understanding in detail the sources of variability. From first-principles, EUV resist reactions are not photon-chemistry, but are really radiation-chemistry with many different radiation paths and electrons which can be generated. If every via in an advanced logic IC must work then the failure rate must be on the order of 1 part-per-trillion (ppt), and stochastic variability from non-homogeneous chemistries must be eliminated.

Consider that for a CAR designed for 15mJ/cm2 sensitivity, there will be just:

145 photons/nm2 for 193, and

10 photons/nm2 for EUV.

To improve sensitivity and suppress failures from photon shot-noise, we need to increase resist absorption, and also re-consider chemical amplification mechanisms. “The requirements will be the same for any resist and any chemistry,” reminded Lio. “We need to evaluate all resists at the same exposure levels and at the same rules, and look at different features to show stochastics like in the tails of distributions. Resolution is important but stochastics will rule our world at the dimensions we’re dealing with.”


Many Mixes to Match Litho Apps

Thursday, March 3rd, 2016


By Ed Korczynski, Sr. Technical Editor

“Mix and Match” has long been a mantra for lithographers in the deep-sub-wavelength era of IC device manufacturing. In general, forming patterns with resolution at minimum pitch as small as 1/4 the wavelength of light can be done using off-axis illumination (OAI) through reticle enhancement techniques (RET) on masks, using optical proximity correction (OPC) perhaps derived from inverse lithography technology (ILT). Lithographers can form 40-45nm wide lines and spaces at the same half-pitch using 193nm light (from ArF lasers) in a single exposure.

Figure 1 shows that application-specific tri-layer photoresists are used to reach the minimum resolution of 193nm-immersion (193i) steppers in a single exposure. Tighter half-pitch features can be created using all manner of multi-patterning processes, including Litho-Etch-Litho-Etch (LELE or LE2) using two masks for a single layer or Self-Aligned Double Patterning (SADP) using sidewall spacers to accomplish pitch-splitting. SADP has been used in high volume manufacturing (HVM) of logic and memory ICs for many years now, and Self-Aligned Quadruple Patterning (SAQP) has been used in HVM by at least one leading memory fab.

Fig.1: Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

Next-Generation Lithography (NGL) generally refers to any post-optical technology with at least some unique niche patterning capability of interest to IC fabs:  Extreme Ultra-Violet (EUV), Directed Self-Assembly (DSA), and Nano-Imprint Lithography (NIL). Though proponents of each NGL have dutifully shown capabilities for targeted mask layers for logic or memory, the capabilities of ArF dry and immersion (ArFi) scanners to process >250 wafers/hour with high uptime dominates the economics of HVM lithography.

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

It is looking most likely that the answer is “all of the above.” EUV and NIL could be used for single layers. For other unique patterning application, ArF/ArFi steppers will be used to create a basic grid/template which will be cut/trimmed using one of the available NGL. Each mask layer in an advanced fab will need application-specific patterning integration, and one of the rare commonalities between all integrated litho modules is the overwhelming need to improve pattern overlay performance.

Naga Chandrasekaran, Micron Corp. vice president of Process R&D, provided a fantastic overview of the patterning requirements for advanced memory chips in a presentation during Nikon’s LithoVision technical symposium held February 21st in San Jose, California prior to the start of SPIE-AL. While resolution improvements are always desired, in the mix-and-match era the greatest challenges involve pattern overlay issues. “In high volume manufacturing, every nanometer variation translates into yield loss, so what is the best overlay that we can deliver as a holistic solution not just considering stepper resolution?” asks Chandrasekaran. “We should talk about cost per nanometer overlay improvement.”

Extreme Ultra-Violet (EUV)

As touted by ASML at SPIE-AL, the brightness and stability and availability of tin-plasma EUV sources continues to improve to 200W in the lab “for one hour, with full dose control,” according to Michael Lercel, ASML’s director of strategic marketing. ASML’s new TWINSCAN NXE:3350B EUVL scanners are now being shipped with 125W power sources, and Intel and Samsung Electronics reported run their EUV power sources at 80W over extended periods.

During Nikon’s LithoVision event, Mark Phillips, Intel Fellow and Director of Lithography Technology Development for Logic, summarized recent progress of EUVL technology:  ~500 wafers-per-day is now standard, and ~1000 wafer-per-day can sometimes happen. However, since grids can be made with ArFi for 1/3 the cost of EUVL even assuming best productivity for the latter, ArFi multi-patterning will continue to be used for most layers. “Resolution is not the only challenge,” reminded Phillips. “Total edge-placement-error in patterning is the biggest challenge to device scaling, and this limit comes before the device physics limit.”

Directed Self-Assembly (DSA)

DSA seems most suited for patterning the periodic 2D arrays used in memory chips such as DRAMs. “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node” was the title of a presentation at SPIE-AL by researchers from Coventor, in which DSA compared favorably to SAQP.

Imec presented electrical results of DSA-formed vias, providing insight on DSA processing variations altering device results. In an exclusive interview with Solid State Technology and SemiMD, imec’s Advanced Patterning Department Director Greg McIntyre reminds us that DSA could save one mask in the patterning of vias which can all be combined into doublets/triplets, since two masks would otherwise be needed to use 193i to do LELE for such a via array. “There have been a lot of patterning tricks developed over the last few years to be able to reduce variability another few nanometers. So all sorts of self-alignments.”

While DSA can be used for shrinking vias that are not doubled/tripled, there are commercially proven spin-on shrink materials that cost much less to use as shown by Kaveri Jain and Scott Light from Micron in their SPIE-AL presentation, “Fundamental characterization of shrink techniques on negative-tone development based dense contact holes.” Chemical shrink processes primarily require control over times, temperatures, and ambients inside a litho track tool to be able repeatably shrink contact hole diameters by 15-25 nm.

Nano-Imprint Litho (NIL)

For advanced IC fab applications, the many different options for NIL technology have been narrowed to just one for IC HVM. The step-and-pattern technology that had been developed and trademarked as “Jet and Flash Imprint Lithography” or “J-FIL” by, has been commercialized for HVM by Canon NanoTechnologies, formerly known as Molecular Imprints. Canon shows improvements in the NIL mask-replication process, since each production mask will need to be replicated from a written master. To use NIL in HVM, mask image placement errors from replication will have to be reduced to ~1nm., while the currently available replication tool is reportedly capable of 2-3nm (3 sigma).

Figure 2 shows normalized costs modeled to produce 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. Key to throughput is fast filling of the 26mmx33mm mold nano-cavities by the liquid resist, and proper jetting of resist drops over a thin adhesion layer enables filling times less than 1 second.

Fig.2: Relative estimated costs to pattern 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

Researchers from Toshiba and SK Hynix described evaluation results of a long-run defect test of NIL using the Canon FPA-1100 NZ2 pilot production tool, capable of 10 wafers per hour and 8nm overlay, in a presentation at SPIE-AL titled, “NIL defect performance toward high-volume mass production.” The team categorized defects that must be minimized into fundamentally different categories—template, non-filling, separation-related, and pattern collapse—and determined parallel paths to defect reduction to allow for using NIL in HVM of memory chips with <20nm half-pitch features.


What’s the Next-Gen Litho Tech? Maybe All of Them

Thursday, February 25th, 2016

By Jeff Dorsch, Contributing Editor

The annual SPIE Advanced Lithography symposium in San Jose, Calif., hasn’t offered a clear winner in the next-generation lithography race. It’s becoming clearer, however, that 193i immersion and extreme-ultraviolet lithography will co-exist in the future, while directed self-assembly, nanoimprint lithography, and maybe even electron-beam direct-write technology will fit into the picture, too.

At the same time, plasma deposition and etching processes are assuming a greater interdependence with 193i, especially when it comes to multiple patterning, such as self-aligned double patterning, self-aligned quadruple patterning, and self-aligned octuple patterning (yes, there is such a thing!).

“We’ve got to go down to the sub-nanometer level,” Richard Gottscho, Lam Research’s executive vice president of global products, said Monday morning in his plenary presentation at the conference. “We must reduce the variability in multiple patterning,” he added.

Gottscho touted the benefits of atomic level processing in continuing to shrink IC dimensions. Atomic level deposition has been in volume production for a decade or more, he noted, and atomic level etching is emerging as an increasingly useful technology.

When it comes to EUV, “it’s a matter of when, not if,” the Lam executive commented. “EUV will be complementary with 193i.”

Anthony Yen, director of nanopatterning technology in the Infrastructure Division of Taiwan Semiconductor Manufacturing, followed Gottscho in the plenary session. “The fat lady hasn’t sung yet, but she’s on the stage,” he said of EUV.

Harry Levinson, senior director of GlobalFoundries, gave the opening plenary presentation, with the topic of “Evolution in the Concentration of Activities in Lithography.” He was asked after his presentation, “When is the end?” Levinson replied, “We’re definitely not going to get sub-atomic.”

With that limit in mind, dozens of papers were presented this week on what may happen before the semiconductor industry hits the sub-atomic wall.

There were seven conferences within the symposium, on specific subjects, along with a day of classes, an interactive poster session, and a two-day exhibition.

The Alternative Lithographic Technologies conference was heavy on directed self-assembly and nanoimprint lithography papers, while also offering glimpses at patterning with tilted ion implantation and multiphoton laser ablation lithography.

“Patterning is the battleground,” said David Fried, Coventor’s chief technology officer, semiconductor, in an interview at the SPIE conference. He described directed self-assembly as “an enabler for optical lithography.”

Mattan Kamon of Coventor presented a paper on Wednesday afternoon on “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node.”

DSA could be used in conjunction with SAQP or LELELELE, according to Fried. While some lithography experts remain leery or skeptical about using DSA in high-volume manufacturing, the Coventor CTO is a proponent of the technology’s potential.

“Unit process models in DSA are not far-fetched,” he said. “I think they’re pretty close.  The challenges of EUV are well understood. DSA challenges are a little less clear. There’s no ‘one solution fits all’ with DSA.” Fried added, “There are places where DSA can still win.”

Franklin Kalk, executive vice president of technology for Toppan Photomasks, is open to the idea of DSA and imprint lithography joining EUV and immersion in the lithography mix. “It will be some combination,” he said in an interview, while adding, “It’s a dog’s breakfast of technologies. Don’t ever count anything out.”

Richard Wise, Lam’s technical managing director in the company’s Patterning, Global Products Groups CTO Office, said EUV, when ready, will likely be complementary with multipatterning for 7 nanometer.

Self-aligning quadruple patterning, for example, was once considered “insanity” in the industry, yet it is a proven production technology now, he said.

While EUV technology is “very focused on one company,” ASML Holding, there is a consensus at SPIE that EUV’s moment is at hand, Wise said. Intel’s endorsement of the technology and dedication to advancing it speaks volumes of EUV’s potential, he asserted.

“Lam’s always excelled in lot-to-lot control,” an area of significant concern, Wise said, especially with all of this week’s talk about process variability.

What will be the final verdict on the future of lithography technology? Stay tuned.

Intel Posts Mixed Results for Q4, 2015

Friday, January 15th, 2016


By Jeff Dorsch, Contributing Editor

Intel reported net income of $11.4 billion on revenue of $55.4 billion for the year ended December 26, compared with net of $11.7 billion on revenue of $55.9 billion in 2014.

For the fourth quarter, the world’s largest chipmaker measured by annual revenue posted net income of $3.6 billion on revenue of $14.9 billion, compared with $3.7 billion in net on revenue of $14.7 billion a year earlier.

Intel said revenue from the Client Computing Group, its PC chip business, was $8.8 billion, down 1 percent from a year ago. The Data Center Group was up 4 percent, year over year, to $4.3 billion.

The Internet of Things and Non-Volatile Memory Solution groups both showed revenue gains, of 8 percent and 10 percent, respectively.

“Our results for the fourth quarter marked a strong finish to the year and were consistent with expectations,” Intel CEO Brian Krzanich said in a statement. “Our 2015 results demonstrate that Intel is evolving and our strategy is working. This year, we’ll continue to drive growth by powering the infrastructure for an increasingly smart and connected world.”

Intel is forecasting revenue of $14 billion for the first quarter of 2016, with full-year revenue growing in middle-to-high single digits. Capital expenditures in 2016 will be flat with last year, at $9.5 billion.

The 2016 forecast does not account for the company’s recent acquisition of Altera, according to Intel.

InvenSense Developers Conference Tackles Sensor Security, New Technologies

Monday, November 23rd, 2015

By Jeff Dorsch, Contributing Editor

The second day of the InvenSense Developers Conference saw presenters get down to cases – use cases for sensors.

There were track sessions devoted to mobile technology and the Internet of Things, with the latter featuring presentations on industrial and automotive applications, smart homes and drones, smartphones and tablet computers, and wearable electronics. InvenSense partner companies had their own track on New Technologies, fitting into the conference’s “Internet of Sensors” theme.

The conference also featured two developer tracks in parallel, providing five InvenSense presentations on its FireFly hardware and software, SensorStudio, and other offerings.

One of the presentations that wrapped up the conference on Wednesday afternoon (November 18) was given by Pim Tuyls, chief executive officer of Intrinsic-ID, the Dutch company that worked with InvenSense to develop the TrustedSensor product, a secure sensor-based authentication system incorporating the FireFly system-on-a-chip device.

TrustedSensor will be shipped to alpha customers in the first quarter of 2016 and will go out to beta customers in the second quarter of next year, according to Tuyls. “This is real,” he said.

The Intrinsic-ID founder briefly reviewed the company’s history, to start. It was spun out of Royal Philips in 2008 and is an independent company with venture-capital funding, Tuyls noted.

Intrinsic-ID was founded to provide “cyber physical security based on physically unclonable function,” or PUF, Tuyls said. “We invented PUF,” he added. “It has been vetted by security labs and government agencies,” among other parties.

Taking “The Trusted Sensor” as his theme, the Intrinsic-ID CEO said, “Sensors are the first line of defense. You want to make sure you can provide a certain level of security.”

It is critical to achieve “the right balance” in designing, fabricating, and installing sensors, with security, flexibility, and low footprint among the key considerations, according to Tuyls.

While whimsically describing PUF as “a magic concept,” Tuyls noted, “Chips are physically unique,” with no two completely alike due to manufacturing processes.

PUF can “extract a crypto key from any device,” he added. “You can authenticate any device.”

Intrinsic-ID has tested the PUF technology with a wide variety of silicon foundries, Tuyls said – namely, Cypress Semiconductor, GlobalFoundries, IBM, Intel, Renesas Electronics, Samsung Electronics, Taiwan Semiconductor Manufacturing, and United Microelectronics. It has been implemented by Altera, Microsemi, NXP Semiconductors, Samsung, and Synopsys, he added, and process nodes ranging from 180 nanometers down to 14nm have been tested.

Tuyls concluded by emphasizing the importance of sensor security for the Internet of Things. “We should not wait; we should not try to save a few cents,” he said. “It is important, but it is hard.”

Earlier in the day, attendees heard from Sam Massih, InvenSense’s director of wearable sensors. “There’s a wearable solution for every part of the body,” he commented.

“Step count isn’t enough,” Massih said. “You need context for data.” He cited the example of a user who goes to the gym three times a week and spends an hour on the elliptical trainer machine for one hour on each visit.

“That’s data that can be monetized,” he said.

InvenSense announced last month that it would enter the market for automotive sensors. Amir Panush, the company’s head of automotive and IoT industrial, said in his presentation, “Sensors need to be smart enough.”

The megatrends in automotive electronics include the use of motion sensors for safety in advanced driver-assistance systems (ADAS), the smart connected car, and tough emission restrictions, according to Panush.

“We have signed a deal with a Tier One partner,” Panush said, meaning a leading automotive manufacturer, without identifying the company. “We are ramping up internal R&D in automotive.” InvenSense is presently opening design centers focusing on the $5 trillion automotive market, he added.

InvenSense was founded in 2003 and went public in 2011. The company posted revenue of $372 million in fiscal 2015 with a net loss of $1.08 million (primarily due to charging $10.55 million in interest expense against net income), after being profitable for the previous four years. InvenSense gets more than three-quarters of its revenue from mobile sensors and has a growing business in IoT sensors.

Customers in Asia accounted for 63 percent of the company’s fiscal 2015 revenue, according to InvenSense’s 10-K annual report. The company spent $90.6 million on research and development, representing about 24 percent of its net revenue.

GlobalFoundries and TSMC make nearly all of InvenSense’s wafers. Assembly packaging of its microelectromechanical system (MEMS) devices and sensors is outsourced to Advanced Semiconductor Engineering, Amkor Technology, Lingsen Precision Industries, and Siliconware Precision Industries.

The company had 644 employees as of March 29, 2015, with nearly half of them involved in R&D.

STMicroelectronics is InvenSense’s primary competitor for consumer motion sensors, the 10-K states, while the company also competes with Analog Devices, Epson Toyocom, Kionix, Knowles, Maxim Integrated Products, MEMSIC, Murata Manufacturing, Panasonic, Robert Bosch, and Sony.

Wally Rhines of Mentor Graphics Gets Phil Kaufman Award

Monday, November 16th, 2015

By Jeff Dorsch, Contributing Editor

There was a celebrity roast on 4th Street in San Jose, Calif., on Thursday night.

The occasion was the presentation of the annual Phil Kaufman Award to Wally Rhines, chairman and chief executive officer of Mentor Graphics, for his contributions in the field of electronic design automation. Dr. Rhines has served as Mentor’s CEO since 1993 and as chairman of the EDA software and services company since 2000.

The Phil Kaufman Award is presented by the Electronic Design Automation Consortium (EDAC) and the IEEE Council on Electronic Design Automation (CEDA). It honors the memory of Philip A. Kaufman, the EDA industry pioneer, electronics engineer, and entrepreneur, who died in 1992.

Rhines received some gentle ribbing from Craig Barrett, the former Intel chairman and CEO, who once was a Stanford University professor and served on the advisory panel for Rhines’ doctoral thesis.

Barrett said of Rhines, who was a top chip executive at Texas Instruments prior to joining Mentor, “We competed for about 20 years, which is probably why he went to Mentor Graphics.”

He added, “His hairline is receding faster than mine.”

The retired Intel executive later said Rhines’ career has been “fantastic,” adding, “He certainly exceeded all our expectations. You done good, man. Keep it up.”

A video shown before the formal presentation offered Barrett and other top executives showering accolades on Rhines, who turned 69 years old on Wednesday, November 11. Among those praising Rhines were Aart de Geus, chairman and co-CEO of Synopsys, and Lip-Bu Tan, president and CEO of Cadence Design Systems – business rivals and friends.

“He’s actually a cool cat,” de Geus said of Rhines in the video.

In his remarks, Rhines returned the favor to those praising him, saying of de Geus and Tan, “We’ve had enjoyable interactions.

“I’m particularly gratified that my professor, Craig Barrett, came here for my roast,” he said. “He willingly paid for the beer at The Oasis in Menlo Park.”

On a more serious note, Rhines said of Barrett, “He was very critical to my success.”

Rhines recalled the days when chip designers used rubylith sheets to lay out integrated circuits. “We evolved an industry,” he commented. While IC design and layout has become highly automated with EDA software, system design in many industries remains in the rubylith era, Rhines said. He called for a movement to “automate system design the way we automated electronic design.”

The evening drew to a close with a spoof video depicting Rhines as not only a visionary leader in EDA, but also as a race-car mechanic, a sushi chef, and a hair stylist. A good time was had by all.

IoT Security, Software Are Highlighted at ARM TechCon

Friday, November 13th, 2015


By Jeff Dorsch, Contributing Editor

Many people are aware of the Internet of Things concept. What they want to know now is how to secure the IoT and how to develop code for it.

Plenty of vendors on hand for the ARM TechCon conference and exposition in Santa Clara, Calif. this week were offering solutions on both counts. And there were multiple presentations in the three-day conference program devoted to both subjects.

Mentor Graphics, for instance, spoke about “Use Cases for ARM TrustZone Benefits of HW-Enforced Partitioning and OS Separation.” MediaTek presented on “Secured Communication Between Devices and Clouds with LinkIt ONE and mbedTLS.” And so on.

ARM CEO Simon Segars said in his keynote address that security and trust are one of the key principles in the Internet of Things (the others being connectivity and partnership across the ecosystem). Security and trust, he asserted, must be “at every level baked into the hardware, before you start layering software on top.”

James Bruce, ARM’s director of mobile solutions, addressed the security topic at length in an interview at the conference. ARM is taking a holistic approach to security through its TrustZone technology, he said, describing it as “a great place to put [network] keys.”

With microcontrollers, the chips often used in IoT devices, TrustZone makes sure sensitive data is “inaccessible to normal software,” Bruce said. At the same time, “you want to make devices easy to update,” he added.

ARM wants to enable its worldwide ecosystem of partners to stay ahead of cyberattacks and other online dangers, according to Bruce. “That’s why we’re doing the groundwork now,” he said.

The reaction of ARM partners to the introduction of TrustZone CryptoCells and the new ARMv8-M architecture for embedded devices has been “very positive,” Bruce said, adding, “Security can’t be an afterthought.”

Ron Ih, senior manager of marketing and business development in the Security Products Group at Atmel, described standard encryption as “only a piece” of security measures. “Authentication is a key part,” he said.

Atmel was touting its Certified-ID platform at ARM TechCon, featuring the ATECC508A cryptographic co-processor. Ih cited the “made for iPhone” chips that Apple requires of its partners developing products to complement the smartphone, ensuring ecosystem control. “You either have the chip or you don’t,” he said.

“People don’t care about the devices,” Ih concluded. “They care about who the devices are connected to.”

Simon Davidmann, president and chief executive officer of Imperas Software, is a veteran of the electronic design automation field, and he brings his experience to bear in the area of embedded software development.

Software, especially for the IoT, is “getting so complex, you can’t do what you used to do,” he said. “The software world has to change. Nobody should build software without simulation.”

At the same time, simulation is “necessary but not sufficient” in software development, he said. Code developers should be paying attention to abstractions, assertions, verification, and other aspects, according to Davidmann.

“Our customers are starting to adopt virtual platforms,” he added.

Jean Labrosse, president and CEO of MIcrium, a leading provider of real-time operating system kernels and other software components, said “the industry is changing” with the onset of the Internet of Things. Multiple-core chips are entering into the mix – not only for their low-power attributes, but for the safety and security they can provide, he noted.

Jeffrey Fortin, director of product management at Wind River and a specialist in IoT platforms, spoke on the last day of the conference on “Designing for the Internet of Things: The Technology Behind the Hype.”

Wind River, now an Intel subsidiary, has been around for more than three decades, developing “an embedded operating system that could be connected to other systems,” he said.

There are two business interests driving IoT demand, according to Fortin – business optimization and business transformation. He described the IoT as “using data to feed actionable analytics.”

The foundation of the IoT is hardware and software that provides safety and security, Fortin said.

Colt McAnlis of Google (Photo by Jeff Dorsch)

In the final keynote of ARM TechCon, Google developer advocate Colt McAnlis spoke on “The Hard Things About the Internet of Things.”

IoT technology, at present, is “not optimizing the user,” he said in a frequently funny and witty presentation. Networking and battery issues are bedeviling the IoT ecosystem, he asserted.

By draining the batteries of mobile devices with near-constant signals, such as setting location via GPS, companies are imposing “a taxation system for every single thing [IoT] does,” McAnlis said. “We’re talking about how often we’re sampling. People are already realizing this sucks.”

Beacons installed in a shopping mall can bombard smartphone users with advertising and coupons, he noted, while the property management gets data on specifics of foot traffic. “Imagine this at scale,” installed on every block of San Francisco, he added.

“We have a chance to not make this a reality,” McAnlis asserted. “We need IoT technology to make this not suck for users.”

At the end of his keynote, McAnlis asked the attendees to hold up their smartphones and vow, “I solemnly agree not to screw this up.”

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