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Blog review June 30, 2014

Monday, June 30th, 2014

Pete Singer blogs that at The ConFab last week, IBM’s Gary Patton gave us three reasons to be very positive about the future of the semiconductor industry: an explosion of applications, the rise of big data and the need to analyze all that data.

Tony Chao of Applied Materials writes that Applied Ventures will be participating in the second-annual Silicon Innovation Forum (SIF) held in conjunction with SEMICON West 2014 in San Francisco on Tuesday, July 8. The forum is designed to bring new and emerging innovators together with the semiconductor industry’s top strategic investors and venture capitalists (VCs), in order to enable closer collaboration and showcase the next generation of entrepreneurs in microelectronics.

Adele Hars of ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news. Malier said that CEA-Let has been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development.

Phil Garrou blogs that last week at the 2014 ISC (International Supercomputing Conference) it was announced that the Intel Xenon Phi processor “Knights Landing” would debut in 2015. It will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can work on up to four threads per core.

Solid State Watch: May 30-June 5, 2014

Friday, June 6th, 2014
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The Week in Review: June 6, 2014

Friday, June 6th, 2014

After two years of decline, fab equipment spending for Front End facilities in 2014 is expected to increase 24 percent in 2014 (US$35.7 billion), according to the May 2014 SEMI World Fab Forecast Report released this week.

This week, the Society for Information Display (SID) unveiled the winners of its prestigious 19th annual Display Industry Awards.

The Semiconductor Industry Association (SIA) this week announced that worldwide sales of semiconductors reached $26.34 billion for the month of April 2014.

Imec announced this week that it is collaborating with Samsung Electronics to accelerate innovation and collaboration among technology companies and researchers working in the burgeoning mobile wearable field.

Synopsys, Inc. and Intel Corporation this week announced broad SoC design enablement for Intel’s 14nm Tri-Gate process technology for use by customers of Intel Custom Foundry.

Scouting report for materials at end of the road: 2013 ITRS

Monday, May 12th, 2014

Ed Korczynski, Sr. Technical Editor, SST/SemiMD

The IC fabrication industry is approaching the end of the road for device miniaturization, with both atomic and economic limits looming on the horizon. New materials are widely considered as key to the future of profitable innovation in ICs, so everyone from process engineers to business pundits needs to examine the Emerging Research Materials (ERM) chapter of the just published 2013 edition of the International Technology Roadmap for Semiconductors (ITRS).

The 2013 ITRS covers both near-term (2014-2020) and long-term (2020 onward) perspectives on what materials and processes would be desired to build ideal ICs (Fig. 1, Table ERM15). However, to properly understand the information in the current edition we need to consider the changes in the IC fab industry since 1992 when the first edition of the ITRS’s predecessor was published as the U.S. National Technology Roadmap for Semiconductors (NTRS).

Fig. 1

Twenty-two years ago, the industry had dozens of fabs working on next-generation technology, and with lithographic scaling dominating innovation there was broad consensus on gradual materials evolutions. Today, the industry has 3 logic fabs and about as many memory lines pushing processes to smaller geometries, and each fab may use significantly different revolutionary materials. The result today is that there is little consensus on direction for new materials, and at best we can quantify the relative benefits of choosing one or another of the many options available.

In fact, with just a few players left in the game, there is much to lose for any one player to disclose strategic plans such as the use of revolutionary materials. Mark Thirsk, managing partner with specialty materials analysts Linx Consulting, commented, “We built our business based on anonymizing and generalizing the world, and then predicting the future based on big categorical buckets. But now there are a very few number of people pushing the boundaries and we’re being asked to model specific fab processes such as those for Intel or TSMC.”

For all of the above reasons, the current ITRS might be better understood as a scouting report that quantifies the roughness of the terrain when our current roads end. Exotic materials such as graphene and indium-gallium-phosphide may be used as alternate materials for the Si channels in transistors, novel stacks of atomic-layers may be used as electrical contacts, and spintronics and single-electron devices may one day replace DRAM and Flash chips for solid-state memory chips. However,  “significant challenges” exist in integrating any of these new technologies into high-volume manufacturing.

In the near-term, Cu wires clad with various metal barriers are projected to provide the best overall performance for on-chip interconnects.  As stated in the 2013 Executive Summary, “Unfortunately no new breakthroughs are reported for interconnections since no viable materials with resistivity below copper exist. However, progress in manipulation of edgeless wrapped materials (e.g., carbon nanotubes, graphene combinations etc.) offer the promise of ‘ballistic conductors,’ which may emerge in the next decade.”

Specialty Materials Suppliers

Fig. 2

Figure 2 (Figure ERM5) shows the inherent complexity involved in the stages of developing a new chemical precursor for use in commercial IC production. The chapter summarizes the intrinsic difficulty of atomic-scale R&D for future chips as follows:

A critical ERM factor for improving emerging devices, interconnects, and package technologies is the ability to characterize and control embedded interface properties. As features approach the nanometer scale, fundamental thermodynamic stability considerations and fluctuations may limit the ability to fabricate materials with tight dimensional distributions and controlled useful material properties.

In addition to daunting technical issues with pre-cursor R&D, the business model for chemical suppliers is being strained by industry consolidation and by dimensional shrinks. Consolidation means that each fab has unique pre-cursor requirements, so there may be just one customer for a requested chemistry and no ability to get a return on the investment if the customer decides to use a different approach.

Shrinks down to atomic dimensions means that just milliliters instead of liters of chemistry may be needed. For example, atomic-layer deposition (ALD) precursor R&D requires expertise and investment in molecular- and chemical-engineering, and so significant sunk costs to create any specialty molecule in research quantities. “We’ll have an explosion of precursors required based on proprietary IP held by different companies,” reminds Thirsk. “The people who are being asked to develop the supply-chain of ever increasing specifications are simultaneously being squeezed on margin and volumes.”

For materials such as Co, Ru, La, and Ti-alloys to be used in fabs we need to develop more than just deposition and metrology steps. We will also likely require atomic-level processes for cleaning and etch/CMP, which can trigger a need for yet another custom material solution.

Established chemical suppliers—such as Air Liquide, Dow, DuPont, Linde, Praxair, and SAFC—run international businesses serving many industries. IC manufacturing is just a small portion of their businesses, and they can afford to simply walk-away from the industry if the ROI seems unattractive. “We’re finding more and more that, for example in wet cleaning chemistry, the top line of the market is flat,” cautioned Thirsk. “You can find some specialty chemistries that provide better profits, but the dynamics of the market are such that there’s reduced volume and reduced profitability. So where will the innovation come from?”

Alternate Channel Materials

With finFETs and SOI now both capable of running in fully-depleted mode, alternative materials to strained silicon are being extensively explored to provide higher MOSFET performance at reduced power. Examples include III-V semiconductors, Ge, graphene, carbon nanotubes, and other semiconductor nanowires (NW). To achieve complimentary MOS high performance, co-integration of different materials (i.e. III-V and Ge) on Si may be necessary. Significant materials issues such as defect reduction, interface chemistry, metal contact resistivity, and process integration must be addressed before such improvements can be achieved.

Nano-wire transistors

Top down fabricated nanowires (NW) are one-dimensional structures that can be derived from two-dimensional finFETs. Patterned and etched <5nm Si NW have been reported to have room temperature quantum oscillatory behavior with back-gate voltage with a peak mobility approaching ∼900 cm2/Vs. Despite extensive R&D, grown Si NW demonstrate no performance improvements over patterned-and-etched NW, and controlled growth in desired locations remains extraordinarily challenging. Overall, significant challenges must be overcome for NW to be integrated in high density, particularly when targeting laterally placed NW with surround gates and low resistance contacts.

—E.K.

Blog review April 7, 2014

Monday, April 7th, 2014

Pete Singer reveals the lineup of presenters for Session 1 of The ConFab, to be held June 22-25 in Las Vegas, and provides summaries of their talks. Speakers will be Vijay Ullal, COO, Fairchild Semiconductor; Dave Anderson, President and CEO, Novati Technologies; Gopal Rao, Senior Director Business Development, SEMATECH; Adrian Maynes, Program Manager, F450C; and Bill McClean, President, IC Insights.

Phil Garrou blogs about a variety of diverse issues this week, including GLOBALFOUNDRIES’ potential purchase of IBM’s semiconductor business, Altera’s separate deals with Intel and TSMC, why FinFET could be more expensive that more conventional CMOS strategies, as view by Handle Jones of IBS, and a new joint development program between ASE and Inotera focused on 3D IC packaging.

The Week in Review: March 28, 2014

Friday, March 28th, 2014

Altera Corporation and Intel Corporation announced their collaboration on the development of multi-die devices that leverage Intel’s package and assembly capabilities and Altera’s leading-edge programmable logic technology. The collaboration is an extension of the foundry relationship between Altera and Intel, in which Intel is manufacturing Altera’s Stratix 10 FPGAs and SoCs using the 14nm Tri-Gate process. Altera’s work with Intel will enable the development of multi-die devices that efficiently integrates monolithic 14nm Stratix 10 FPGAs and SoCs with other advanced components, which may include DRAM, SRAM, ASICs, processors and analog components, in a single package.

Samsung introduced a new lineup of flip chip LED packages and modules offering enhanced design flexibility and a high degree of reliability. The new offerings, for use in leading-edge LED lighting such as LED bulbs, MR/PAR and downlights, will be available in the market during the second quarter of this year. Samsung’s new flip chip (FC) LED package and flip chip on module (FCOM) solutions feature highly efficient and versatile LED structures, created by flipping over blue LED chips and adhering phosphor film to each of them. Unlike conventional LED packages that dispense phosphor and then place a plastic mold over each chip, Samsung’s FC package technology can produce LED packages down to a chip-scale size without any mold, enabling more compact lighting fixture designs.

eInfochips, a semiconductor and product engineering company, this week launched design services for chips based on 16nm geometry. The comprehensive suite of services includes Netlist to GDSII, Sign-off, and Design for Testability. eInfochips is one of the few engineering services companies in the world capable of delivering 16nm chip designs which reduce a chip’s power consumption by half, while improving performance by one-third over 28nm technology.

SEMATECH announced this week that Particle Measuring Systems has joined SEMATECH to advance the development of nanoscale particle removal processes and cleaning technologies for next-generation wafers and devices. This collaboration will address many of the profound changes taking place in the semiconductor industry that are impacting fundamental aspects of process and equipment design, including integration of new materials and process technology for sub-20nm node manufacturing, next-generation lithography requirements.

CEA-Leti will demonstrate its new prototype for wireless high data rate Li-Fi (light fidelity) transmission at Light + Building 2014 in Frankfurt, Germany, March 30-April 4. The technology employs the high-frequency modulation capabilities of light-emitting diode (LED) engines used in commercial lighting. It achieves throughputs of up to 10Mb/s at a range of three meters, suitable for HD video streaming or Internet browsing, using light power of less than 1,000 lumens and with direct or even indirect lighting. With this first proof of concept and its expertise in RF communications, Leti forecasts data transmission rates in excess of 100Mb/s with traditional lighting based on LED lamps using this technology approach and without altering the high-performance lighting characteristics.

Solid State Watch: February 14-20, 2014

Friday, February 21st, 2014
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Blog review February 10, 2014

Monday, February 10th, 2014

Dick James of ChipWorks blogs that when Intel launched their Haswell series chips last June, they stated that the high-end systems would have embedded DRAM, as a separate chip in the package. “It took us a while to track down a couple of laptops with the requisite Haswell version, but we did and now we have a few images that show it’s a very different structure from the other e-DRAMs that we’ve seen,” he notes.

Phil Garrou continues his look at the 2013 Georgia Tech Interposer Conference, focusing on presentations from Amkor and GlobalFoundries. He writes that Ron Huemoeller of Amkor projects that in the high end silicon will dominate; in the mid-end, silicon will be prominent and organic /glass may play a role; in the low end, organic, or low cost glass or silicon if they exist will play a role. Dave McCann of GlobalFoundries examined market needs for interposers.

Semico’s review of the latest and greatest from the Consumer Electronics Show highlights five technologies they think you should pay attention to as game changers: 3D Printing, the Bosch wireless sensor network for IoT; Bionics: Thought-controlled prosthetics; Aging in place: Pain relief; and LED Lighting.

Vivek Bakshi, of EUV Litho, Inc., ponders some interesting questions, such as how important is the semiconductor industry relative to other industries, and how did we get to where we are, the continuation of Moore’s Law and why have there been so few Nobel prizes given to the chip industry?

Karen Lightman of the MEMS Industry Group says the upcoming MEMS Executive Congress Europe “checks all the boxes” with great content and speakers, networking time with MEMS industry execs and OEM users, and an unbeatable location in Munich.

Pete Singer takes a look back at February 1964 through the pages of Solid State Technology, when wafers were small, dreams were big and The Beatles were on the Ed Sullivan show. The issue discussed thermionic energy convertors, the potential of which is still being explored today by Stanford.

The Week In Review: February 6, 2014

Friday, February 7th, 2014

The Financial Times (FT) is reporting that IBM Corp is exploring the sale of its semiconductor business and has hired Goldman Sachs to find potential buyers. The FT report continues that another financial option may be to find a partner for a JV to jointly run its semiconductor business. FT projects that the most likely buyers would be Global Foundries or TSMC  since it is likely that these two foundry giants along with Samsung and Intel will be the only players left in advanced chip manufacturing as the cost of 20nm and lower fabs now exceeds $6B.

Research reported this week shows that electrical resistance in nanoribbons of epitaxial graphene changes in discrete steps following quantum mechanical principles. The research shows that the graphene nanoribbons act more like optical waveguides or quantum dots, allowing electrons to flow smoothly along the edges of the material. In ordinary conductors such as copper, resistance increases in proportion to the length as electrons encounter more and more impurities while moving through the conductor.

In a merger that will bring together two key suppliers in the semiconductor industry, Entegris, Inc. and ATMI announced Entegris will acquire ATMI for approximately $1.15 billion, or approximately $850 million net of cash acquired, including the net cash proceeds from the sale of ATMI’s LifeSciences business of $170 million. The companies anticipate closing the transaction in the second quarter of 2014.

The closing Executive Panel discussion at the SEMI Industry Strategy Symposium on January 15 provoked diverse views on the drivers and future of innovation in the microelectronics manufacturing supply chain.  While technology demand and manufacturing efficiency provide the motivation for continued innovation in the minds of some, others believe the supply chain is forfeiting its value proposition and places too much emphasis on cost reduction. For the full story on Solid State Technology, click here.

Intel Corporation this week announced that its board of directors elected five new corporate vice presidents.

Blog review February 3, 2014

Monday, February 3rd, 2014

Ira Feldman provides an interesting perspective on last month’s SEMI Industry Strategy Symposium. He notes that numerous speakers including Jon Casey (IBM) and Mike Mayberry (Intel) stated that scaling will continue below the 10 nm process node perhaps to 5 or 7 nm. However, the question raised by both the speakers and the audience was at what cost will this scaling be achieved.

“Long live the FinFET,” says Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc. In this blog post, he describes how designers will have to seek out new tools and methodologies to overcome FinFET design challenges. One example is the adoption of giga-scale parallel SPICE simulators to harness circuit simulation challenges in FinFET designs. Traditional SPICE simulators don’t have the capacity and lack sufficient performance to support FinFET designs, while FastSPICE simulators likely will not meet accuracy requirements, he writes.

Adele Hars of Advanced Substrate News reports that STMicroelectronics will soon be announcing a “major foundry player” that will be both a dual FD-SOI manufacturing source for ST, plus an open source for the industry. This important piece of news came out of the company’s Q4 and FY13 presentation in Paris on January 28th.

Phil Garrou finishes up his review of the IMAPS 2013 meeting, with an analysis of Xilinx/SPIL results from their 2.5D 28nm FPGA program, a review of the Copper TSV work presented by Nanyang/IME, Canon’s FPA-5510iV and FPA-5510iZ TSA steppers designed to support high density processes and the implementation of 2.5 & 3D technology, and a report on the embedded technology being developed by AT&S.

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