Posts Tagged ‘Intel’
By Jeff Dorsch, Contributing Editor
In the five decades of Moore’s Law, named for the Intel co-founder, “computing has really had one trajectory,” Krzanich said – smaller, more personal, and more connected.
With the advent of wearable gadgets, implemented with Intel’s Curie module, “personal is at a new level,” he noted. “Displays are more personal and more connected.”
The devices of today, such as smartphones and tablet computers, “are dumb displays,” he asserted. “Everything you do is flat.”
While the advent of touch displays has freed users from computer mice and keyboards, the display remains “2D, flat,” Krzanich noted.
The next step is to make computers able to “see and hear like a human,” he said. “For humans, everything is 3D.”
He added, “That future is not too far off.”
Speech recognition has been in development for some time and has demonstrably advanced, Krzanich said. “When you can hear but not see, you’re only halfway there,” he added.
The Intel chief then held up a RealSense module, which is 3.75 millimeters in thickness. It can be embedded in the top bezel of a laptop computer, among other applications, he noted.
Intel is making its RealSense software development kit available at intel.com/realsense, and “all of these APIs are free,” Krzanich said.
“RealSense cameras enable a new video experience, a much more immersive experience,” Krzanich said. “The computer starts to see the world as you and I do.”
Moving beyond consumer applications, Intel is now working on industrial and professional apps, according to Krzanich.
He demonstrated how a device with a RealSense camera could complete a three-dimensional scan of his body in about 30 seconds, and showed off a bust of himself made with a 3D printer.
This was followed by a demonstration of putting a virtual Brian Krzanich into a video game, where the figure ran and did handsprings and backflips. “If only I could do this in real life,” he joked.
Krzanich also demonstrated how RealSense can work with augmented reality, repeating a demo done at the International Consumer Electronics Show in January, where a virtual piano appeared in mid-air and could be played. With some help, he showed how a virtual secondary screen could materialize in mid-air and could employ AR for a variety of applications.
Krzanich appealed to the keynote attendees to take advantage of the free RealSense SDK.
“We want you to create something bigger and better,” he concluded. “We need help.”
By Jeff Dorsch, contributing editor
The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium in San Jose, Calif.
Extreme-ultraviolet lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing.
On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.
There are other lithography technologies being discussed at the conference, of course. They are bit players in the drama, so to speak, although there is a lot of discussion and buzz about directed self-assembly technology this week.
ASML broke big news on Tuesday morning, reporting that Taiwan Semiconductor Manufacturing was able to expose more than 1,000 wafers in one day this year with ASML’s NXE:3300B EUV system. “During a recent test run on an NXE:3300B EUV system we exposed 1,022 wafers in 24 hours with sustained power of over 90 watts,” Anthony Yen, TSMC’s director of research and development, said at SPIE.
While ASML was obviously and justifiably proud of this milestone, after achieving its 2014 goal of producing 500 wafers per day, it cautioned that more development remains for EUV technology.
“The test run at TSMC demonstrates the capability of the NXE:3300B scanner, and moves us closer to our stated target of sustained output of 1,000 wafers per day in 2015,” ASML’s Hans Meiling, vice president service and product marketing EUV, said in a statement. “We must continue to increase source power, improve system availability, and show this result at multiple customers over multiple days.”
The day before, Cymer announced the first shipment of its XLR 700ix light source, which is said to improver scanner throughput and process stability for manufacturing chips with 14-nanometer features. The company also debuted DynaPulse as an upgrade option for its OnPulse customers. The XLR 700ix and DynaPulse together are said to offer better on-wafer critical dimension uniformity and provide stable on-wafer performance.
Another revelation at SPIE is that SK Hynix has been working with the NXE:3300, too, and is pleased with the system’s capabilities. According to Chang-Moon Lim, who spoke Monday morning, SK Hynix was recently able to expose 1,670 wafers over three days, with uptime of 86.3 percent over that period.
“Progress has been significant on various aspects, which should not be overshadowed by the delay of [light] sources,” he said of ASML’s EUV systems.
The Korean chipmaker is exploring how it could work without pellicles on the EUV reticle, Lim noted. ASML has been developing a pellicle, made with polycrystalline silicon, in cooperation with Intel and others.
Nikon Precision and other Nikon subsidiaries didn’t issue any press releases at SPIE. The companies presented much information at Sunday’s LithoVision 2015 event, held at the City National Civic auditorium, across the street from the San Jose Convention Center, where SPIE Advanced Lithography is staged.
On offer at the Nikon conference was the claimed superiority of 193i immersion lithography equipment to EUV systems for the 14nm, 7nm and future process nodes. Donis Flagello, Nikon Research Corp. of America’s president, CEO, and chief operating officer, emphasized that message on Tuesday morning with an invited paper on “Evolving optical lithography without EUV.”
Nikon’s champion machine is the NSR-S630D immersion scanner, which was touted throughout the LithoVision event. The system is capable of exposing 250 wafers per hour, according to Nikon’s Yuichi Shibazaki.
Ryoichi Kawaguchi of Nikon told attendees, “EUV lithography needs more stability and improvement.” He also brought up the topic of manufacturing on 450-millimeter wafers, which has mostly gone ignored in the lithography competition. Nikon will ship a 450mm system this spring to the Global 450 Consortium in Albany, N.Y., Kawaguchi said. The bigger substrates could provide “an alternative option to reduce cost,” he added.
Erik Byers of Micron Technology observed, “EUV is not a panacea.”
Which lithography technology will prevail in high-volume manufacturing? The question may not be definitively answered for some time.
Scott McGregor, President and CEO of Broadcom, sees some major changes for the semiconductor industry moving forward, brought about by rising design and manufacturing costs. Speaking at the SEMI Industry Strategy Symposium (ISS) in January, McGregor said the cost per transistor was rising after the 28nm, which he described as “one of the most significant challenges we as an industry have faced.” Pete Singer reports.
Matthew Hogan, Mentor Graphics writes a tongue-in-cheek blog about IP, saying chip designers need only to merely insert the IP into the IC design and make the necessary connections. Easy-peasey! Except…robust design requires more than verifying each separate block—you must also verify that the overall design is robust. When you are using hundreds of IPs sourced from multiple suppliers in a layout, how do you ensure that the integration of all those IPs is robust and accurate?
Dick James, Senior Analyst at Chipworks IEDM blogs that Monday was FinFET Day. He highlights three finFET papers, by TSMC, Intel, and IBM.
A research team led by folks at Cornell University (along with University of California, Berkeley; Tsinghua University; and Swiss Federal Institute of Technology in Zurich) have discovered how to make a single-phase multiferroic switch out of bismuth ferrite (BiFeO3) as shown in an online letter to Nature. Ed Korczynski reports.
SEMI praised the bipartisan effort in the United States Congress to pass the Revitalize American Manufacturing and Innovation (RAMI) Act as part of the year-end spending package. Since its introduction in August 2013, SEMI has been a champion and leading voice in support of the bill that would create public private partnerships to establish institutes for manufacturing innovation.
Phil Garrou takes a look at some of the key presentations at the 2014 IEEE 3DIC Conference recently held in Cork, Ireland.
Adele Hars writes that there were about 40 SOI-based papers presented at IEDM. In Part 1 of ASN’s IEDM coverage, she provides a rundown of the top SOI-based advanced CMOS papers.
Karen Lightman of the MEMS Industry Group says power is the HOLY GRAIL to both the future success of wearables and IoT/Everything. Power reduction and management through sensor fusion, power generation through energy harvesting as well as basic battery longevity. It became very clear from conversations at the MIG conference as well as in talking with folks on the CES show floor that the issue of power is the biggest challenge and opportunity facing us now.
In order to keep pace with Moore’s Law, semiconductor market leaders have had to adopt increasingly challenging technology roadmaps, which are leading to new demands on electronic materials (EM) product quality for leading-edge chip manufacturing. Dr. Atul Athalye, Head of Technology, Linde Electronics, discusses the challenges.
By Ed Korczynski, Sr. Technical Editor
In another example of the old one-liner that “all that is old is new again,” the old technique of solid-source doping is being used by Intel for a critical process step in so-called “14nm node” finFET manufacturing. In the 7th presentation in the 3rd session of this year’s IEDM, a late news paper written by 52 co-authors from Intel titled “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588m2 SRAM Cell Size” disclosed that solid source doping was used under the fins.
As reported by Dick James of Chipworks in his blog coverage of IEDM this year, the fins have a more vertical profile compared to the prior “22nm node” and are merely 8nm wide (Fig. 1). Since Intel is still using bulk silicon wafers instead of silicon-on-insulator (SOI), to prevent leakage through the substrate these 8nm fins required a new process to make punch-through stopper junctions, and the new sub-fin doping technique uses solid glass sources. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over the prior node, and Idlin by 30% for NMOS and 38% for PMOS.
Solid glass sources of boron (B) and phosphorous (P) dopants have been used for decades in the industry. In a typical application, a lithographically defined silicon-nitride hard-mask protects areas from a blanket deposition in a tube furnace of an amorphous layer containing the desired dopant. Additional annealing before stripping off the dopant layer allows for an additional degree of freedom in activating dopants and forming junctions.
In recent years, On Semiconductor published how solid-source doping on the sidewalls of Vertical DMOS transistors enable a highly phosphorous doped path for the drain current to be brought back to the silicon surface. The company shows that phosphorous-oxy-chloride (POCl) and phospho-silicate glass (PSG) sources can both be used to form heavily doped junctions 1-2 microns deep.
The challenge for solid-source doping of 8nm wide silicon fins is how to scale processes that were developed for 1-2 microns to be able to form repeatable junctions 1-2 nm in scale. Self-aligned lithographic techniques could be used to mask the tops of fins, and various glass sources could be used. It is likely that ultra-fast annealing is needed to form stable ultra-shallow junctions.
Intel is notoriously protective of process Intellectual Property (IP) and so has almost certainly ensured that any equipment and materials suppliers who work on the solid-source doping process sign Non-Disclosure Agreements (NDA) with amendments that forbid acknowledging signing the NDA itself, so it is pointless to directly ask for any further details at this point. However, slides from John Borland’s recent presentation at the NCCAVS Junction Technology Users Group meeting provide a great overview of the publicly available information on finFET junction formation, and include the following:
…higher dopant activation can be realized at low temperatures if the junction is amorphous and recrystalized by using SPE (solid phase epitaxy) recrystalization of the junction as also shown in the data by Intel.
Also seen at IEDM this year in the 7th presentation of the Advanced Process Modules section, Taiwanese researchers—National Nano Device Laboratories, National Chiao Tung University, and National Cheng Kung University—joined with Californian consultants—Current Scientific, Evans Analytical Group—to show “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing.” They claim an ideal subthreshold swing (~60 mV/dec) at a high doping level. Poly-Si n & p JLFinFETs (W/L=10/20 nm) with SDP experimentally exhibit superior gate control (Ion/Ioff >10E6) and improved device variation.
By Jeff Dorsch, Contributing Editor
At the 60th annual International Electron Devices Meeting this week in San Francisco, there was much buzz about the 14-nanometer FinFET papers being presented by IBM and Intel. Those papers were the subject of a press release two months in advance.
Getting less attention at IEDM 2014 were the papers on sensors, microelectromechanical systems (MEMS) devices and bio-MEMS. This technology generates fewer headlines, although it is present in smartphones, fitness trackers, and many other electronic products.
Monday afternoon, December 15, saw the first MEMS-related papers presented at the conference, on nanoelectromechanical systems (NEMS) and energy harvesters. Donald Gardner of Intel, an IEEE Fellow, presented a paper on “Integrated On-Chip Energy Storage Using Porous-Silicon Electrochemical Capacitors,” which was supported by research at Florida International University and the University of Turku.
Gardner described how porous-silicon nanostructures were synthesized and passivated with titanium nitride through atomic-level deposition or with carbon through chemical vapor deposition. These coatings helped keep the porous silicon from oxidizing, he explained.
These electrochemical capacitors, an alternative to batteries, produced with the porous silicon could be used in energy harvesting and some applications in energy storage, according to the authors of the paper.
Session 8 of the IEDM conference also included a paper authored by France’s Institute of Electronics, Microelectronics and Nanotechnology (IEMN) and STMicroelectronics, “Fabrication of Integrated Micrometer Platform for Thermoelectric Measurements.” Maciej Haras presented the paper. He noted that 55 percent to 60 percent of energy used is released as waste heat. Harvesting energy from such heat could be a significant source of power generation in the future.
“Thermoelectricity is quite unpopular on the market,” Haras noted. Toxic materials, such as antimony, bismuth, lead, and tellurium, could be replaced by silicon, germanium or silicon germanium (SiGe) could to produce CMOS-compatible thermoelectrics, he said.
In energy conversion efficiency, silicon that is only 10 nanometers thick is 10 times more efficient than bulk silicon, Haras said.
Session 15 on Tuesday morning, December 16, was devoted to “Graphene Devices, Biosensors and Photonics.” This session featured some of the longest paper titles at the conference, such as “An Ultra-Sensitive Resistive Pressure Sensor Based on the V-Shaped Foam-like Structure of Laser-Scribed Graphene,” “A Semiconductor Bio-electrical Platform with Addressable Thermal Control for Accelerated Bioassay Development,” and “Label-Free Optical Biochemical Sensor Realized by a Novel Low-Cost Bulk-Silicon-based CMOS Compatible 3-Dimensional Optoelectronic IC (OEIC) Platform.”
Other papers were more direct, with shorter titles, such as “Flexible, Transparent Single-Layer Graphene Earphone,” which was about exactly that, and “An Integrated Tunable Laser Using Nano-Silicon-Photonic Circuits.”
Coming up on Tuesday afternoon is Session 22, devoted to MEMS and resonator technology, with six papers scheduled.
The nuts and bolts of MEMS and NEMS technology can be quite esoteric, yet such devices are crucial to the future of electronics.
By Jeff Dorsch, Contributing Editor
The presentations at this week’s 3D Architectures in Semiconductor Integration and Packaging conference could be summed up in a famous Facebook status: “It’s complicated.”
They also could be summed up in one word: Progress.
This year has seen tremendous progress in implementation of 3DIC technology, according to speakers at the 11th annual conference, held in Burlingame, Calif. Those who have been touting and tracking 3D chips for years are looking forward to the 2015 introduction of Intel’s Xeon Phi “Knights Landing” processor for high-performance computing, which will incorporate the Hybrid Memory Cube technology in the same package as the CPU.
Activities began Wednesday, December 10, with a preconference symposium on “2.5/3D-IC Design Tools and Flows” and “3D Integration: 3D Process Technology.” Bill Martin of E-System Design kicked off the program with a presentation on path finding, a topic addressed several times over the next two days. He emphasized that preparing for a chip design project, such as choosing the right tools, is as important as the design and implementation phases when it comes to embracing 3DIC technology.
John Ferguson of Mentor Graphics later said there is “an infrastructure problem” in the semiconductor industry when it comes to process design kits (PDKs) for 2.5D and 3D chips. Taiwan Semiconductor Manufacturing has collaborated with Mentor and other leading suppliers of electronic design automation tools to offer PDKs to TSMC foundry customers, yet the next step must be taken to have outsourced semiconductor assembly and test contractors provide packaging PDKs.
Phil Garrou, a senior consultant for Yole Developpement, said 2014 has witnessed significant progress in implementation of 3DIC technology. “We no longer need to prove performance,” he said. “The remaining issue is cost.”
Several speakers addressed the topic of the Internet of Things and how it involves 3DICs on the first day of the conference. Steven Schulz of the Silicon Integration Initiative (Si2) said 3D chip designers should think of their products not as system-on-a-chip devices, but system-on-a-stack.
Yole’s Rozalia Beica said predictions that the Internet of Things market will be worth trillions of dollars in 2022 are “overoptimistic” and that “optimism is higher than current investment.” Yole looks for the market in IoT sensors to be worth $400 billion in 2024, she said.
Samta Bonsal of the GE Software Center spoke on the Industrial Internet. “That world is huge,” she said, and predicted it will have “a bigger impact” than consumer-oriented IoT applications. Gartner says the market for all IoT chips will be worth $7.58 billion in 2015, she noted. The market research firm also forecasts that 8 billion connected devices will be shipped during 2020, encompassing 35 billion semiconductor devices produced on 6 million wafers.
E. Jan Vardaman of TechSearch International presented a lively review of 3DIC technology, past and present. “There’s been a lot of good progress with TSV (through-silicon vias), enabling us to improve the process,” she said. Still, 3DIC has been a long time in coming, noting that Micron Technology began research and development on DRAM stacking a dozen years ago and Xilinx initiated development of a silicon-based interposer to be used with TSVs in 2006, six years before it was able to offer a field-programmable gate array with such technology, manufactured in volume by TSMC.
Dyi-Chung Hu of Unimicron looked past the silicon interposer to the era to using glass for interposers and substrate core materials. Glass has a low coefficient of thermal expansion compared with silicon, he noted, and is very flat. Its chief drawback is its brittleness, according to Hu.
Michael Gaynes of IBM’s Thomas J. Watson Research Center reported on his company’s two ICECool projects for the Defense Advanced Research Projects Agency, developing 3DICs that could run cooler in data-center servers.
The last day of the conference coincided with a convention devoted to the Star Trek television series in the adjacent hotel ballroom. Attendees dressed as Klingons and starship crew members mingled with the 3DIC technologists in the hotel lobby, all dreaming and thinking about the future.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.