Posts Tagged ‘IC’
By Ed Korczynski, Sr. Technical Editor, SST/SemiMD
The good people at ChipWorks have released some of the first public data on Intel’s new 14nm-node process, and the results indicate that materials limitations in on-chip electrical interconnects are adding costs. Additional levels of metal have been added, and complex “air-gap” structures have been added to the dielectric stack. Flash memory chips have already used air-gaps, and IBM has already used a subtractive variant of air-gaps with >10 levels of metal for microprocessor manufacturing, but this is the first known use of additive air-gaps for logic after Intel announced that a fully-integrated process was ready for 22nm-node chips.
Mark Bohr of Intel famously published data in 1995 (DOI: 10.1109/IEDM.1995.499187) on the inherent circuit speed limitations of interconnects, showing proportionality to the resistance (R) of the metal lines multiplied by the capacitance (C) of the dielectric insulation around the metal (Fig.1). The RC product thus should be minimized for maximum circuit speed, but the materials used for both the metal and the dielectric insulation around metal lines are at limits of affordability in manufacturing.
There are no materials that super-conduct electricity at room temperature, and only expensive and room-sized supercomputers and telecommunications base-stations can afford to use the liquid-nitrogen cooling that is needed for known superconductors to function. Carbon Nano-Tubes (CNT) and 2D atomic-layers of carbon in the form of graphene can conduct ballistically, but integration costs and electrical contact resistances limit use. Copper metal remains as the best electrical conductor for on-chip interconnects, yet as horizontal lines and vertical vias continue to shrink in cross-sectional area the current density has reached the limit of reliability. The result is the increase in the number of metal layers to 13 for 14nm-node Intel microprocessors, while IBM used 15 layers for 22nm-node Power8 chips.
Low-k Dielectrics and Pore Sizes
The dielectric constant (“k”) of silicon oxide is ~4, and ~3.5 with the addition of fluorine to the oxide (SiOF). Carbon-Doped Oxide (CDO or SiOC or SiOC:H) with k~3.0 has been integrated well into interconnect stacks. Some polymers can provide k values in the 2.0-2.7, but they cannot be integrated into most interconnects due to lack of mechanical strength, chemical resistance, and overall stability. Air has k=1, and there have been specialized chips made using metal wires floating in air, but lack of physical structure results in poor manufacturing yield and weak reliability.
A clever compromise is to use both SiOC with k~3 and air with k~1 in a stack, which results in an integrated k value weighted by the percent of the volume taken up by each phase. Porous Low-k (PLK) with 10% porosity allows for an integrated k of ~2.7 for modest improvement, but increasing porosity to just 20% for k~2.4 results in connected random pores that reduce reliability. To reliably integrate 20-30% air into SiOC, the pores cannot be random but must be engineered as discrete gaps in the structure.
In 2007, IBM announced that it would engineer air-gaps in microprocessors, but the company claimed to be using an extremely complex process for integration involving a self-assembled thin-film mask to anisotropically etch out holes between lines and then further isotropic etching to form elongated pores. Though relatively complex and expensive, this process allows for the use of any 2D layout for lines in a given metal layer.
Additive Air-gap Process-Design Integration
For fab lines that are still working with aluminum metal and additive dielectrics, air-gaps are a defect that occurs with imperfect dielectric fill. When not planned as part of the design, air-gaps formed in a lower-layer can be exposed to etchants during subsequent processing resulting in metal shorts or opens. However, Figure 2 shows that it is possible to engineer air-gaps by Chemical-Vapor Deposition (CVD) of dielectric material into line-space structures with proper process control and design layout restrictions. Twenty years ago, this editor worked for an OEM on CVD processes for dielectric fill, and the process can be tuned to be highly repeatable and relatively low-cost if a critical masking step can be avoided. In 1998, Shieh et al. from Stanford (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) showed proof-of-concept for this approach to lower k values.
Four years ago at IEDM 2010, Intel presented details of how to engineer air-gaps using CVD. As this editor wrote at that time in an extensive analysis:
The lithographic masking step is needed for two reliability reasons. First, by excluding air-gap formation in areas near next-layer vias, alignment between layers can be more easily done. Second, wide spaces are excluded where the final non-conformal CVD step wouldn’t automatically pinch-off to close the gaps; leaving full SiOC(H) in wider spaces also helps with mechanical strength. The next layer is patterned with a conventional dual-damascene flow, with the option to add air-gaps.
Now we know that Intel kept air-gaps on the metaphorical shelf by skipping use at the 22nm-node. The 2014 IEDM paper from Intel will discuss details of 14nm-node air-gaps: two levels at 80nm and 160nm minimum pitches, yielding a 17% reduction in capacitance delays.
This process requires regularly spaced 1D line arrays as a design constraint, which may also be part of the reason for additional metal layers to allow for 2D connections through vias. Due to lithography resolution advantages with 1D “gridded” layouts, other logic fabs may soon run 1D designs at which point additive air-gaps like that used by Intel will provide a relatively easy boost to IC speeds.
By Ed Korczynski, Sr. Technical Editor, Solid State Technology and SemiMD
The “Internet of Things” (IoT) has been seen as the next major market that will demand high volumes of integrated circuits (IC). The IoT can be loosely defined as a network of small, low-cost, ubiquitous electronic devices where sensing data and communicating information occurs without direct human intervention. Each device would function as a “smart node” in the network by doing some low-level signal processing to filter signals from noise, and to reduce the bandwidth needed for node-to-node communications. The nodes will need to communicate up to some manner of a “cloud” for secure memory storage and to bounce actionable information down to humans.
Figure 1 shows a conservative forecast of the global IoT market that was recently published by IDC. IDC expects the worldwide IoT installed base to experience a compound annual growth rate (CAGR) of 17.5% from 2013 to 2020, starting from 9.1 billion smart nodes installed at the end of 2013 and growing to 28.1 billion units by 2020.
Due to the anticipated elastic-demand for IoT devices that would come from cost reductions, the forecasts for the number of IoT nodes ranges to 50 billion or even 80 billion by the year 2020, as documented in the recent online Pete’s Post “Don’t Hack My Light Bulb, Bro”. The post also provides an excellent overview of recent discussions regarding the host of additional technology and business challenges associated with the enterprise infrastructure and security issues surrounding the integration of vast streams of new information.
As shown in Figure 1, the smart nodes form the foundation for the whole IoT. Consequently, the world will need low-cost high-volume manufacturing (HVM) technologies to create the different functionalites needed for smart nodes. Sensor- and logic-technologies to enable IoT smart nodes will generally evolve from existing IC applications, while R&D continues in Radio Frequency (RF) communications and in Micro Electro-Mechanical Systems (MEMS) energy harvesting.
IoT smart-nodes will use wireless RF technologies to communicate between themselves and with the “cloud.” In support of rapid growth in the 71-86 GHz RF “E-band” telecom backhaul segment—which transports data from cell sites in the peripheral radio access network (RAN) to the wireless packet core—Presto Engineering recently announced a non-captive production-scale testing service for 50µm-thin gallium arsenide wafers.
Silicon-On-Insulator (SOI) substrate supplier Soitec has excellent perspective on the global market for RF chips, since it’s High-Resistivity SOI (HR-SOI) wafers are widely used in commercial fabs. Bernard Aspar, senior vice president and general manager of the Communications and Power business unit of Soitec, explained to SemiMD in an exclusive interview why the market for RF chips is growing rapdily. RF front-end module unit sales are forecasted to increase at a CAGR of ~16% over the period of 2013-2017, while the area of silicon needing to be delivered could actually increase at ~30% CAGR. RF chips are increasing in average size due to the need to integrate multiple standards for wireless communications and multiple antenna switches. “The first components to be integrated in silicon were the antenna switches, moving from 70% on GaAs in 2010 to more than 80% on SOI in 2014,“ said Aspar.
Soitec claims that >80% of smart-phones today use an RF chip built on a wafer from the company, based on sales last year of >300k 200mm HR-SOI wafers. Due to anticipated future growth in RF demand, the company has plans to eventually move HR-SOI production to 300mm diameter wafers. Most of the anticipated demand will be for the company’s new variant of HR-SOI called eSI (“enhanced Signal Integrity”previously called “Trap Rich”) with a measured effective resistivity as high as 10 kOhm-cm for improved device performance.
This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) and purely capacitive crosstalk similar to quartz substrates. HR-SOI substrates in general demonstrate reduced harmonics compared with standard SOI substrates, and the eSI wafers reduce harmonics to the point that they can be considered as lossless. Soitec was recently given a Best Partnership Award by Sony Semiconductor for supplying RF substrates.
“We’re also adding value to the substrate because it allows for simplification of the fab processing,” said Aspar. The eSI wafers enable much higher linearity and isolation, helping designers to address some of the most advanced LTE requirements at competitive costs. These substrates also provides benefits for the integration of passives, such as the quality factor of spiral inductors or tunable MEMS capacitors.
Vibrational Energy Harvesting
IoT smart nodes will need electrical power to function, and batteries that must be replaced or charged by an external source create issues for ubiquitous always-on small devices. In principle the ambient energies of the environment can be harvested to power smart nodes, and to do so we may consider using thermoelectric, photovoltaic, and piezoelectric properties of thin-films. Thermoelectric and photovoltaic devices both require somewhat specialized ambients for efficient energy harvesting, while piezoelectric devices can extract energy from subtle vibrations almost anywhere in the world (Fig. 2).
Researchers in the Energy Harvesting and Mechatronics Research Lab at Stony Brook University, New York, recently published an excellent overview of the potential for 1 W to 100 kW piezoelectronic energy harvesting in building, automobiles, and wearables electronics in the Journal of Intelligent Material Systems and Structures 24(11) 1405-1430. However, the largest forecasted growth in the IoT is for small devices that would consume µW to mW of active power.
For low-cost and low-power consumption, the logic chips for IoT smart nodes are expected to be made using a 65nm “trailing edge” fab process. For example, CAST Inc. has developed a 32-bit BA20 embedded processor core that can deliver 3.41 CoreMarks/MHz at a maximum frequency of 75 MHz. Using TSMC’s 65nm Low Power fab process, it occupies only 0.01 mm2 of silicon area while consuming 2 µW/MHz. Thus, at maximum speed the chip core would consume just 150µW.
MicroGen Systems, Inc. (MicroGen) is a privately held company developing thin piezoelectric energy harvesters, based on technology from Cornell University’s NanoScale Science and Technology Facility. Founded in 2007, MicroGen has headquarters and R&D in the Ithaca and Rochester, NY areas, and volume manufacturing with X-FAB in Itzehoe, Germany. Figure 3 shows one of the company’s ~100 mm2 area chips featuring an aluminum nitride (AlN) peizoelectric thin-film on a cantilever that produces alternating current (AC) electricity in response to external vibrations. Different cantilever designs allow for harvesting energy from either single-frequency or broadband vibrations. At resonance the AC power output is maximized, so it can be ~100 µW at 120Hz and 0.1g, or ~900 µW at 600Hz and 0.5g.
For any piezoelectric energy harvester there are basic materials properties that must be optimized, including the piezoelectric strain constant as well as the electromechanical coupling factor of the thin-film to the moving mass. Lead-zirconium-titanate (PZT) has been the most studied piezoelectric thin-film due to high strain constant and ability to couple to a substrate though the use of buffer layers.
S. H. Baek, et al. showed “Piezoelectric MEMS with Giant Piezo Actuation” in Science 18 November 2011, Vol 344 using lead-manganese-niobate with lead-titanate (PMN-PT) layers epitaxially grown on a strontium-titanate (STO) buffer layer over 4°-off-axis(001)Si. Figure 4 shows both the transverse piezoelectric coefficient (C/m2) and the energy-harvesting figure of merit (GPa) for this and other thin-films. Note that to acheive stable “giant” piezoelectric effects the PMN-PT layer had to be grown epitaxially with precise control over the STO grain orientation.
By Bill Martin, President and VP of Engg, E-System Design
In the late 1940’s, three physicists (Bardeen, Brattain and Shockley) invented the first transistor and were later awarded the Nobel Prize in 1956 (Figure 1). Texas Instruments commercialized the integrate silicon transistor (IC) in 1954 revolutionizing consumer products. The IC invention and commercialization came at a perfect point in history1,2.
During 1950-1970s, the US population grew by 33% (Figure 2), income grew 170% and disposable spending increased 259% (Figure 3). Disposable income was aided by increasing income but also by significant changes to our marginal tax rates. (Figure 4). Consumer demand for better IC based products and their spending $s provided a perfect Petri dish to hone a new technology requiring new processes (silicon, packaging and pcb); supply chains and high tech marketing for future IC based technologies3,4.
In this period, Moore’s Law was ‘coined’ and quickly drove and guided silicon manufacturers to prove their processing prowess. It also drove product companies and their marketing staffs to harness the guaranteed 2x density, improved performance and less expensive next generation silicon technology within their products. Like an atomic clock, the market expected and received the new capabilities every 18-24 months.
The IC treadmill was at full speed replacing older, larger, slower, higher maintenance products with ICs. As ‘they’ conquered existing products, new uses from the significant (medical devices), to the trivial (musical greeting cards) were developed to capture the growing disposable income. In the early days, it was cheap to create any type of product to test market acceptance.
Since the 1970’s the environment has significantly improved:
US population is over 330 million, annual income is over $50K, disposable spending is approaching 50% and the tax rates continue to fall. In addition, the entire world, 7 billion strong and growing, many wanting to have the latest products. Today’s product success benchmark has elevated to a million or more units purchased during a product’s life span. Some very well designed and marketed products attain this volume on the initial day of sale (iPhone)!
Cracks in the foundation: Inflection omen?
But there were cracks in the foundation starting to appear. More resources, more time and additional physical effects that had to be analyzed and resolved. But engineers are very good at solving these issues that arise with each new generation. One aspect that has not been addressed and is racing out of control is a design’s silicon mask costs. Masks allow silicon foundries to build up ICs one layer at a time and define all geometries required for an IC to work. Each physical layer may require 1 or 2 masks. Until the mid 1990’s, mask costs were manageable. But as the industry continued to drive toward smaller geometries, 90nm silicon mask costs passed $1M per design5. Process engineers had accomplished their goals of producing smaller geometries but this caused an escalation in the required number of masks per layer and the finer geometries increased the cost to create and inspect each mask. Both factors led to a geometric impact on mask costs. Once past the $1M per mask set, the next process’ mask prices quickly escalated to $3-4M for a 65nm set. This is just for the masks and does not include other product development costs, wafer/assembly/test manufacturing costs, marketing or sales costs. Quick math: a product with 1 million units of sales that contains one 65 nm integrate circuit will attribute $3-4 dollars to pay back ONLY the mask set expense. FPGA, as a design platform, is one solution but this assumes that your design can be implemented in an FPGA. Many high volume parts still want a dedicated, non-FPGA solution due to per unit costs. Think what the end product’s sale’s price must be for a decent return on investment (ROI). Economics used to be a friend of silicon linear scaling but we might be at the economic inflection point for linear scaling. A recent SemiWiki post by Paul McLellan highlights the complexity and change required to continue the silicon scaling6:
“The problem with double patterning is that it is possible to design layouts that cannot be split into two masks…
To make things worse, this is not a local phenomenon…
The introduction of both multi-patterning and FinFETs has a huge impact …
…the entire place and route flow needs to be completely revamped.”
Economics drive the inflection
Will all these technology issues get resolved? Scientists and engineers have conquered most of what they focus on (flying, space, ocean, medical, etc). In time, all of the technical issues can be resolved but what will be the cost to use these ‘solutions’? Economics on the product development side (development vs. revenues generated) will cause many product developers to search for alternative solutions or cancel projects that are ROI infeasible.
Moore’s Law V1.0 was based upon manufacturing unit learning curves. Each doubling of volume helped decrease the costs to produce the next unit by improving yields. Improving yields allowed designers to create larger die with more transistors and functionality but at a higher cost (at least they could get >0% yield). But this higher cost drove product companies to search for the next generation silicon node that shrunk the die to improve costs: a perfect circular system re-enforcing itself.
Time for Moore’s Law 2.0 (Figure 6: More than Moore modified)
Changing to another solution requires persistence, energy and small successes to gain inertia for Moore’s Law 2.0. Packaging becomes the focus on Moore’s Law 2.0: 2.5D and 3D allow the mixing and matching of many building blocks into miniaturized systems. Blocks already designed, proven with known histories, costs and suppliers: significantly reducing risks and development costs.
Homogeneous silicon will never be able to integrate all into a single piece of silicon but must always be available. Too many compromises in the homogeneous processing will reduce the effectiveness of a given function (ie AMS/RF or memory or MEMS or…) and the cost of: tools, masks and processing complexity will quickly cancel any products looking for a positive ROI.
Maybe not a secret any longer….
Secrets are hard to keep when more and more people start to talk. In recent months, increasing articles and press releases discuss companies that are exploring and/or using 2.5/3D packaging for impressive gains. Many of these efforts have been hidden for either keeping a competitive edge or for fear of public failure. But like many trends, once a trend gains momentum, it is difficult to stop. Moore’s Law V1.0 is a perfect example.
If your company is on the Moore’s Law V2.0 bandwagon, continue to re-examine old thoughts with a fresh perspective.
If your company is not investigating Moore’s Law V2.0, you might want to ask why not?
1 First transistor picture. http://www.bluekep.com/insanoglunun-en-buyuk-kesfi/ and http://en.wikipedia.org/wiki/History_of_the_transistor.
3 “100 Years of U.S. Consumer Spending”, U.S. Departments of Labor and Statistics, May 2006.
4 Annenberg Learner website: http://www.learner.org/courses/envsci/unit/text.php?unit=5&secNum=4.
5 C.R. Helms, Past President & CEO International SEMATECH, “Semiconductor Technology Research, Development, & Manufacturing: Status, Challenges, & Solutions” p16, http://www.nist.gov/pml/div683/conference/upload/Helms_2003.pdf, 2003.
6 Place & Route with FinFETs and Double Patterning, Paul McLellan, Sept 29, 2014, https://www.semiwiki.com/forum/content/3883-place-route-finfets-double-patterning.html.
By Ed Korczynski, Sr. Technical Editor
Virtual Roundtable provides perspective on the need for greater integration within the “fabless-foundry” ecosystem
Q1: The fabless-foundry relationship in commercial IC manufacturing was established during an era of fab technology predictability—clear litho roadmaps for smaller and cheaper devices—but the future of fab technology seems unpredictable. The complexity which must be managed by a fabless company has already increased to justify leaders such as Apple or Qualcomm investing in technology R&D with foundries and with EDA- and OEM-companies. With manufacturing process technology integrating more materials with ever smaller nodes, how do we manage such complexity?
ANSWER: Gregg Bartlett, Senior Vice President, Product Management, GLOBALFOUNDRIES
The vast majority of Integrated Device Manufacturers (IDMs) have either gone completely fabless or partnered with foundries for their leading-edge technology needs instead of making the huge investments necessary to keep pace with technology. The foundry opportunity is increasingly concentrated at the leading edge; this segment is expected to drive 60 percent of the total foundry market by 2016, representing a total of $27.5 billion. Yet there are fewer high-volume manufacturers that have the capabilities to offer leading-edge technologies beyond 28nm, even as the major companies have accelerated their technology roadmaps at 20nm and 14nm and added new device architectures.
This has led to a global capacity challenge. Leading-edge fabs are more expensive and fewer than ever. At the 130nm node, the cost to build a fab was just over $1B. For a 28nm fab, the cost is about $6B and a 14nm fab is nearly $10B. Technology development costs are rising at a similar rate, growing from a few $10M’s at 130nm to several $100M’s at 28nm.
On top of these technology and manufacturing challenges, product life cycles are shrinking and end users are expecting more and more from their devices in terms of performance, power-efficiency, and features. Competing on manufacturing expertise alone is no longer a viable strategy in today’s semiconductor industry, and solutions developed in isolation are not adequate. The industry must work closer across all levels of the supply chain to understand these dynamics and how they put demands on the silicon chip.
Fortunately, the fabless/foundry model is evolving to accommodate these changing dynamics. We have been promoting this idea for years with what we like to call “Foundry 2.0.” In the 1970s/1980s, the industry was dominated by the IDM. Then the foundry model was invented and grew to prominence in the 1990s and early 2000s, but it was much more of a contract manufacturing model. A fabless company developed a design in isolation and then “threw it over the wall” to the foundry for manufacturing. There was not much need for interplay between the two companies. Of course, as technology complexity has increased in the past decade, this dynamic has changed dramatically. We have entered the era of collaborative device manufacturing. Collaboration is a buzz word that gets thrown around a lot, but today it really is critical and it needs to happen across all vectors, including design flow development, manufacturing supply chain, and customer engagement.
Q2: 3D in packaging started with wire-bonded-chip-stacks and now includes silicon-interposers (a.k.a. “2.5D”) and the memory-cube using through-silicon via (TSV). How about the complexity of 3D products using chip-package co-design, and many players in the ecosystem being needed hroughout design-ramp-HVM?
ANSWER: Sesh Ramaswami, Managing Director, TSV and Advanced Packaging, Silicon Systems Group of Applied Materials
Enabling 3D requires the participation of the extended ecosystem. These include contributions from CAD, design tools for die architecture, floor plan, and layout circuit design test structures, as well as methodology wafer level process equipment and materials, wafer-level test assembly and packaging stacked die and package level testing.
Q3: Due to challenges with lithographic scaling below 45nm half-pitch, how does the need to integrate new materials and device structures change the fabless-foundry relationship? How much of fully-depleted channels using SOI wafers and/or finFETs, followed by alternate channels can the industry afford without commited damand from IDMs and major fabless players for specific variants?
ANSWER: Adam Brand, Director of Transistor Technology, Silicon Systems Group of Applied Materials
New materials and device structures are going to play a key role in advancing the technology to the next several nodes.
With EUV delayed, multi-patterning is growing in use, and new materials are enabling the sophisticated and precise extension of multi-patterning to the 7nm node and beyond. The multi-patterning schemes however bring specific restrictions on layout which will affect the design process.
For device structures, Epi in particular is going to enable the next generation of complex device designs with improved mobility and by supporting very thin precisely defined channel structures to scale to smaller gate length and pitch. For these next generation devices, the R&D challenges will be high, but the industry cannot afford to skimp on R&D to find the winning solution to the low power transistor technology required for the 7nm and 5nm and beyond nodes.
Q4: Mobile consumer devices now seem to drive the leading edge of demand for many ICs. However, the Internet-of-Things (IoT) is often spoken of needing just 65nm node chips to keep costs as low as possible, and these designs are expected to run in high volume for many years. How will these different devices that will continue to evolve in different ways get integrated together?
ANSWER: Michael Buehler-Garcia, Senior Director of Marketing, Calibre Design Solutions of Mentor Graphics
IOT has become the new industry buzz word. What it has done is spotlight the multiple elements of a complete solution that do not require emerging process technologies for their chip design. Moreover, while a chip may use a well established process node, the actual design may be very complex. For example Mentor is participating in the German RESCAR program to increase the reliability of automotive electronics using our Calibre PERC solution. The initial reliability checks written are targeted for 180nm and older process nodes. Why? Because today’s 180nm and older node designs are much more complex than when these nodes were mainstream digital nodes and as such require more advanced verification solutions. Bottom line: as opposed to a strategy of only moving to the next process node, chip design companies today have multiple options. It is up to the ecosystem to provide solutions that allow the designers be able to make trade-offs without major changes in their design flows.
Solving an organic semiconductor mystery; Rice-sized laser, powered one electron at a time, bodes well for quantum computing; Carbon nanotube finding could lead to flexible electronics with longer battery life
Stacking 2-dimensional materials may lower cost of semiconductor devices; Scientists measure speedy electrons in silicon; Holst Centre and imec develop thin-film hybrid oxide-organic microprocessor
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.