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Low-Cost Manufacturing of Flexible Functionalities

Wednesday, July 15th, 2015

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By Ed Korczynski, Sr. Technical Editor

SEMICON West includes many business and technology workshops and forums for attendees.  On Wednesday morning July 15, attendees packed the TechXPOT in the South Hall of Moscone Center to hear updates on the status of flexible hybrid electronics manufacturing.

M-H. Huang of Corning showed the surprising properties of “Corning Willow Glass: Substrates for flexible electronic devices.” Willow Glass is created in a fusion-forming process similar to that used to create Gorilla Glass, though with thickness <=200 microns to allow for flexibility. “A key advantage is hermeticity compared to plastic substrates,” reminded Huang. Thin bare glass without any edge or surface coatings can be repeatably bent and twisted without cracking. The minimum bending radius for roll-to-roll (R2R) processing is limited by coating layer delamination:  12.5mm for bare glass, 25mm for AZO-coated glass, and 50mm radius for CZTS cells on glass all passing 500 bending cycles at 60 cycles per minute. Working with the State University of New York at Binghamton Center for Advanced Microelectronic Manufacturing (CAMM), Corning has demonstrated R2R sputtering of Al, Cr/Cu, ITO, SiO2, and IGZO films. Collaborating with ITRI in Taiwan using tools designed specifically for processing flexible glass, Corning demonstrated R2R gravure-offset printing of metal mesh structures silver ink that can be used for 7” touch-panels. Working with both CAMM and ITRI has led to R&D fabrication of a touch sensor with 90% device yield.

Thomas Lantzer, of DuPont Electronic Materials, discussed the “Materials Supplier Perspective on Flexible Hybrid Electronics.” Since the overarching goal of flexible electronics is not just mass and volume reduction but a huge reduction in manufacturing cost, it is axiomatic that fabrication must evolving toward the use of traditional printing methods and flexible substrates.

“There are many printing techniques,” explained Lantzer, “So there are building blocks out there today that we feel will lead to an explosion of fabrication capabilities in the future.” DuPont has been actively involve in flexible materials and electronics for decades, supplying screen printed conductive pastes, resistor pastes for automotive defoggers, flexible films, and flexible materials for copper circuitry.

Mark Poliks, Professor at the State University of New York at Binghamton and Director of the Center for Advanced Microelectronic Manufacturing (CAMM), provided a comprehensive overview of “Materials, Processes & Tools for Fabrication of Flexible Hybrid Electronics.” Working with partners in the Nano-Bio Manufacturing Consortium since 2013, CAMM researchers are developing a wearable disposable sensor system with a target price of $2 to measure human performance parameters. The device including sensors, processor, battery, and wireless communications blocks will be built with copper (Cu) connections on flexible substrates such as polyimide. Initial functionalities will include biometric parameters such as electro-cardio-gram (ECG) signals and skin temperature. First prototypes of ECG sensors on 12.5 micron thin polyimide have been completed, which demonstrate output wave forms with equal or better signal extraction compared to industry standard silver/silver-chloride (Ag/AgCl) electrodes. This new printed sensor and breadboard electronics can be flexed over 200 times and retain the same signal quality and heart-beat extraction. The flexible substrate can accommodate assembly processes for flip-chip (FC) ASIC dice having micro-bumps on a 70 micron pitch, using die-placement accuracy of 9 microns (3 sigma). For flexible hybrid applications, dual-sided placement of components along with printed circuitry reduces the real estate of the final packaged device.

Applied Materials’ Olympia ALD Spins Powerful New Capabilities

Monday, July 13th, 2015

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By Ed Korczynski, Sr. Technical Editor

Applied Materials today unveiled the Applied Olympia ALD system, using thermal sequential-ALD technology for the high-volume manufacturing (HVM) of leading-edge 3D memory and logic chips. Strictly speaking this is a mini-batch tool, since four 300mm wafers are loaded onto a turn-table in the chamber that continuously rotates through four gas-isolated modular processing zones. Each zone can be configured to flow any arbitrary ALD precursor or to exposure the surface to Rapid-Thermal-Processing (RTP) illumination, so an extraordinary combination of ALD processes can be run in the tool. “What are the applications that will result from this? We don’t know yet because the world has never before had a tool which could provide these capabilities,” said David Chu, Strategic Marketing, Applied’s Dielectric Systems and Modules group.

Fig.1: The four zones within the Olympia sequential-ALD chamber can be configured to use any combination of precursors or treatments. (Source: Applied Materials)

Figure 1 shows that in addition to a high-throughput simple ALD process such that wafers would rotate through A-B-A-B precursors in sequence, or zones configured in an A-B-C-B sequence to produce a nano-laminate such as Zirconia-Alumina-Zirconia (ZAZ), almost any combination of pre- and post-treatments can be used. The gas-panel and chemical source sub-systems in the tool allow for the use up to 4 precursors. Consequently, Olympia opens the way to depositing the widest spectrum of next-generation atomic-scale conformal films including advanced patterning films, higher- and lower-k dielectrics, low-temperature films, and nano-laminates.

“The Olympia system overcomes fundamental limitations chipmakers are experiencing with conventional ALD technologies, such as reduced chemistry control of single-wafer solutions and long cycle times of furnaces,” Dr. Mukund Srinivasan, vice president and general manager of Applied’s Dielectric Systems and Modules group. “Because of this, we’re seeing strong market response, with Olympia systems installed at multiple customers to support their move to 10nm and beyond.” Future device structures will need more and more conformal ALD, as new materials will have to coat new 3D features.

When engineering even-smaller structures using ALD, thermal budgets inherently decrease to prevent atomic inter-diffusion. Compared to thermal ALD, Plasma-Enhanced ALD (PEALD) functions at reduced temperatures but tend to induce impurities in the film because of excess energy in the chamber. The ability of Olympia to do RTP for each sequentially deposited atomic-layer leads to final film properties that are inherently superior in defectivity levels to PEALD films at the same thermal budget:  alumina, silica, silicon-nitride, titania, and titanium-nitride depositions into high aspect-ratio structures have been shown.

Purging (from the tool) pump-purge

Fab engineers who have to deal with ALD technology—from process to facilities—should be very happy working with Olympia because the precursors flow through the chamber continuously instead of having to use the pump-purge sequences typical of single-wafer and mini-batch ALD tools used for IC fabrication. Pump-purge sequences in ALD tools result in the following wastes:

*   Wasted chemistry since tools generally shunt precursor-A past the chamber directly to the pump-line when precursor-B is flowing and vice-versa,

*   More wasted chemistry because the entire chamber gets coated along with the wafer,

*   Wasted cleaning chemistry during routine chamber and pump preventative-maintenance,

*   Wasted downtime to clean the chamber and pump, and

*   Wasted device yield because precursors flowing in the same space at different times can accidentally overlap and create defects.

“Today there are chemistries that are more or less compatible with tools,” reminded Chu. “When you try to use less-compatible chemistries, the purge times in single-wafer tools really begin to reduce the productivity of the process. There are chemistries out there today that would be desirable to use that are not pursued due to the limitations of pump-purge chambers.”

—E.K.

3DIC Technology Drivers and Roadmaps

Monday, June 22nd, 2015

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By Ed Korczynski, Sr. Technical Editor

After 15 years of targeted R&D, through-silicon via (TSV) formation technology has been established for various applications. Figure 1 shows that there are now detailed roadmaps for different types of 3-dimensional (3D) ICs well established in industry—first-order segmentation based on the wiring-level/partitioning—with all of the unit-processes and integration needed for reliable functionality shown. Using block-to-block integration with 5 micron lines at leading international IC foundries such as GlobalFoundries, systems stacking logic and memory such as the Hybrid Memory Cube (HMC) are now in production.

Fig. 1: Today’s 3D technology landscape segmented by wiring-level, showing cross-sections of typical 2-tier circuit stacks, and indicating planned reductions in contact pitches. (Source: imec)

“There are interposers for high-end complex SOC design with good yield,” informed Eric Beyne, Scientific Director Advanced Packaging & Interconnect for imec in an exclusive interview with Solid State Technology. ““For a systems company, once you’ve made the decision to go 3D there’s no way back,” said Beyne. “If you need high-bandwidth memory, for example, then you’re committed to some sort of 3D. The process is happening today.” Beyne is scheduled to talk about 3D technology driven by 3D application requirements in the imec Technology Forum to be held July 13 in San Francisco.

Adaptation of TSV for stacking of components into a complete functional system is key to high-volume demand. Phil Garrou, packaging technologist and SemiMD blogger, reported from the recent ConFab that Hynix is readying a second generation of high-bandwidth memory (HBM 2) for use in high performance computing (HPC) such as graphics, with products already announced like Pascal from Nvidia and Greenland from AMD.

For a normalized 1 cm2 of silicon area, wide-IO memory needs 1600 signal pins (not counting additional power and ground pins) so several thousand TSV are needed for high-performance stacked DRAM today, while in more advanced memory architectures it could go up by another factor of 10. For wide-IO HVM-2 (or Wide-IO2) the silicon consumed by IO circuitry is maybe 6 cm2 today, such that a 3D stack with shorter vertical connections would eliminate many of the drivers on the chip and would allow scaling of the micro-bumps to perhaps save a total of 4 cm2 in silicon area. 3D stacks provide such trade-offs between design and performance, so the best results are predicted for 3DICs where the partitioning can be re-done at the gate or transistor level. For example, a modern 8-core microprocessor could have over 50% of the silicon area consumed by L3-cache-memory and IO circuitry, and moving from 2D to 3D would reduce total wire-lengths and interconnect power consumptions by >50%.

There are inherent thresholds based on the High:Width ratio (H:W) that determine costs and challenges in process integration of TSV:

-    10:1 ratio is the limit for the use of relatively inexpensive physical vapor deposition (PVD) for the Cu barrier/seed (B/S),

-    20:1 ratio is the limit for the use of atomic-layer deposition (ALD) for B/S and electroless deposition (ELD) for Cu fill with 1.5 x 30 micron vias on the roadmap for the far future,

-    30:1 ratio and greater is unproven as manufacturable, though novel deposition technologies continue to be explored.

TSV Processing Results

The researchers at imec have evaluated different ways of connecting TSV to underlying silicon, and have determined that direct connections to micro-bumps are inherently superior to use of any re-distribution layer (RDL) metal. Consequently, there is renewed effort on scaling of micro-bump pitches to be able to match up with TSV. The standard minimum micro-bump pitch today of 40 micron has been shrunk to 20, and imec is now working on 10 micron with plans to go to 5 micron. While it may not help with TSV connections, an RDL layer may still be needed in the final stack and the Cu metal over-burden from TSV filling has been shown by imec to be sufficiently reproducible to be used as the RDL metal. The silicon surface area covered by TSV today is a few percents not 10s of percents, since the wiring level is global or semi-global.

Regarding the trade-offs between die-to-wafer (D2W) and wafer-to-wafer (W2W) stacking, D2W seems advantageous for most near-term solutions because of easier design and superior yield. D2W design is easier because the top die can be arbitrarily smaller silicon, instead of the identically sized chips needed in W2W stacks. Assuming the same defectivity levels in stacking, D2W yield will almost always be superior to W2W because of the ability to use strictly known-good-die. Still, there are high-density integration concepts out on the horizon that call for W2W stacking. Monolithic 3D (M3D) integration using re-grown active silicon instead of TSV may still be used in the future, but design and yield issues will be at least comparable to those of W2W stacking.

Beyne mentioned that during the recent ECTC 2015, EV Group showed impressive 250nm overlay accuracy on 450mm wafers, proving that W2W alignment at the next wafer size will be sufficient for 3D stacking. Beyne is also excited by the fact the at this year’s ECTC there was, “strong interest in thermo-compression bonding, with 18 papers from leading companies. It’s something that we’ve been working on for many years for die-to-wafer stacking, while people had mistakenly thought that it might be too slow or too expensive.”

Thermal issues for high-performance circuitry remain a potential issue for 3D stacking, particularly when working with finFETs. In 2D transistors the excellent thermal conductivity of the underlying silicon crystal acts like a built-in heat-sink to diffuse heat away from active regions. However, when 3D finFETs protrude from the silicon surface the main path for thermal dissipation is through the metal lines of the local interconnect stack, and so finFETs in general and stacks of finFETs in particular tend to induce more electro-migration (EM) failures in copper interconnects compared to 2D devices built on bulk silicon.

3D Designs and Cost Modeling

At a recent North California Chapter of the American Vacuum Society (NCCAVS) PAG-CMPUG-TFUG Joint Users Group Meeting discussing 3D chip technology held at Semi Global Headquarters in San Jose, Jun-Ho Choy of Mentor Graphics Corp. presented on “Electromigration Simulation Flow For Chip-Scale Parametric Failure Analysis.” Figure 2 shows the results from use of a physics-based model for temperature- and residual-stress-aware void nucleation and growth. Mentor has identified new failure mechanisms in TSV that are based on coefficient of thermal expansion (CTE) mismatch stresses. Large stresses can develop in lines near TSV during subsequent thermal processing, and the stress levels are layout dependent. In the worst cases the combined total stress can exceed the critical level required for void nucleation before any electrical stressing is applied. During electrical stress, EM voids were observed to initially nucleate under the TSV centers at the landing-pad interfaces even though these are the locations of minimal current-crowding, which requires proper modeling of CTE-mismatch induced stresses to explain.

Fig. 2: Calibration of an Electronic Design Automation (EDA) tool allows for accurate prediction of transistor performance depending on distance from a TSV. (Source: Mentor Graphics)

Planned for July 16, 2015 at SEMICON West in San Francisco, a presentation on “3DIC Technology Past, Present and Future” will be part of one of the side Semiconductor Technology Sessions (STS). Ramakanth Alapati, Director of Packaging Strategy and Marketing, GLOBALFOUNDRIES, will discuss the underlying economic, supply chain and technology factors that will drive productization of 3DIC technology as we know it today. Key to understanding the dynamic of technology adaptation is using performance/$ as a metric.

Solid State Watch: June 5-11, 2015

Thursday, June 11th, 2015
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Silicon Technology Extensions shown at MRS Spring 2015

Monday, June 1st, 2015

By Ed Korczynski, Sr. Technical Editor, Solid State Technology/SemiMD

In the spring meeting of the Materials Research Society held recently in San Francisco, Symposium A: Emerging Silicon Science and Technology included presentations on controlling the structure of crystalline spheres and thin-films. Such structures could be used in future complementary metal-oxide semiconductor (CMOS) devices and in photonic circuits built using silicon.

Alexander Gumennik, et al., from the Massachusetts Institute of Technology, presented on “Extraordinary Stress in Silicon Spheres via Anomalous In-Fiber Expansion” as a way to control the bandgap of silicon and thus enable the use of silicon for photodetection at higher wavelengths. A silica fiber with a crystalline silicon core is fed through a flame yielding spherical silicon droplets via capillary instabilities. Upon cooling the spheres solidify and expand against the stiff silica cladding generating high stress conditions. Band gap shifts of 0.05 eV to the red (in Si) are observed, corresponding to internal stress levels. These stress levels exceed the surface stress as measured through birefringence measurements by an order of magnitude, thus hinting at a pressure-focusing mechanism. The effects of the solidification kinetics on the stress levels reached inside the spheres were explored, and the experimental results were found to be in agreement with a pressure-focusing mechanism arising from radial solidification of the spheres from the outer shell to the center. The simplicity of this approach presents compelling opportunities for the achievement of unusual phases and chemical reactions that would occur under high-pressure high-temperature conditions, which therefore opens up a pathway towards the realization of new in-fiber optoelectronic devices.

Fabio  Carta and others from Columbia University working with researchers from IBM showed results on “Excimer Laser Crystallization of Silicon Thin Films on Low-K Dielectrics for Monolithic 3D Integration.” This research supports the “Monolithic 3D” (M3D) approach to 3D CMOS integration as popularized by CEA-LETI, as opposed to the used of Through Silicon Vias (TSV). M3D requires processing temperature below 400°C if copper interconnects and low-k dielectric will be used in the bottom layer. Excimer laser crystallization (ELC) takes advantage of a short laser pulse to fully melt the amorphous silicon layer without allowing excessive time for the heat to spread throughout the structure, achieving large grain polycrystalline layer on top of temperature sensitive substrates. The team crystallized 100nm thick amorphous silicon layers on top of SiO2 and SiCOH (low-k) dielectrics. SEM micrographs show that post-ELC polycrystalline silicon is characterized by micron-long grains with an average width of 543 nm for the SiO2 sample and 570 nm for the low-k samples. A 1D simulation of the crystallization process on a back end of line structure shows that interconnect lines experience a maximum temperature lower than 70°C for the 0.5 μm dielectric, which makes ELC on low-k a viable pathway for achieving monolithic integration.

Seiji  Morisaki, et al., from Hiroshima Univ, showed results for “Micro-Thermal-Plasma-Jet Crystallization of Amorphous Silicon Strips and High-Speed Operation of CMOS Circuit.” The researchers used micro-thermal-plasma-jet (µ-TPJ) for zone melting recrystallization (ZMR) of amorphous silicon (a-Si) films to form lateral grains larger than 60 µm. By applying ZMR on a-Si strip patterns with widths <3 µm, single liquid-solid interfaces move inside the strips and formation of random grain boundaries (GBs) are significantly suppressed. Applying such strip patterns to active channels of thin-film-transistors (TFTs) results in a demonstrated field effect mobility (µFE) higher than 300 cm2/V*s because they contain minimal grain-boundaries. These a-Si strip pattern were then used to characteristic variability of n- and p-channel TFTs and CMOS ring oscillators. The strip patterns showed improved uniformities and defect densities, in general. A 9-stage ring oscillator fabricated with conventional TFTs had a maximum frequency (Fmax) of operation of 58 MHz under supply voltage (Vdd) of 5V which corresponds to a 1-stage delay (τ) of 0.94 ns, while strip channel TFTs demonstrated 108 MHz Fmax and τ decreased to 0.52 ns.

Ebrahim  Najafi, et al., from the California Institute of Technology, showed how “Ultrafast Imaging of Carrier Dynamics at the p-n Junction Interface” based on scanning ultrafast electron microscopy (SUEM) combines the spatial resolution of an electron probe with the temporal resolution of an optical pulse to enable unprecedented studies of carrier dynamics in spatially complex geometries. Observing the behavior of carriers in both space and time provides direct imaging of carrier excitation, transport, and recombination in the silicon p-n junction and the ability to follow their spatiotemporal behavior. Carrier separation on the surface of the p-n junction extends tens of microns beyond the depletion layer, as explained by a model using a ballistic-type transport. With the invention of SUEM, it should now be possible to study density profiles and electric potentials at surfaces and interfaces at the ultrafast time scale with the spatial resolution of the electron probe.

As a reminder, the Call For Paper for the MRS Fall 2015 meeting closes on June 18.

—E.K.

Solid State Watch: March 6-12, 2015

Friday, March 13th, 2015
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MicroWatt Chips shown at ISSCC

Thursday, March 5th, 2015

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By Ed Korczynski, Sr. Technical Editor

With much of future demand for silicon ICs forecasted to be for mobile devices that must conserve battery power, it was natural for much of the focus at the just concluded 2015 International Solid State Circuits Conference (ISSCC) in San Francisco to be on ultra-low-power circuits that run on mere microWatts (µW). From analog to digital logic to radio-frequency (RF) chips and extending to complete system-on-chip (SoC) prototypes, silicon IC functionality is being designed with evolutionary and even revolutionary reductions in the operational power needed.

The figure shows a multi-standard 2.4 GHz radio that was co-developed by imec, Holst Centre, and Renesas using a 40nm node CMOS process. This was detailed in session 13.2 when Y.H. Liu presented “A 3.7mW-RX 4.4mW-TX Fully Integrated Bluetooth Low-Energy/IEEE802.15.4/Proprietary SoC with an ADPLL-Based Fast Frequency Offset Compensation in 40nm CMOS.” It uses a digital-intensive RF architecture tightly integrated with the digital baseband (DBB) and a microcontroller (MCU), and the digital-intensive RF design reduces the analog core area to 1.3mm2, and the DBB/MCU/SRAM occupies an area of 1.1mm2. This is an evolution of a previous 90nm RF front-end design that results in a reduced supply voltage (20 percent), power consumption (25 percent), and chip area (35 percent).

Ultra-low-power multi-standard 2.4 GHz radio compliant with Bluetooth Low Energy and ZigBee, co-developed by imec, Holst Centre, and Renesas. (Source: Renesas)

“From healthcare to smart buildings, ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life,” said Harmke De Groot, Department Director at imec. “The radio consumes the majority of the power of the total system and is one of the most critical components to enable these emerging applications. Moreover, a low-cost area-efficient radio design is an important catalyst for developing small sensor applications, seamlessly integrated into the environment. Implementing an ultra-low power radio will increase the autonomy of the sensor device, increase its quality, functionality and performance and enable the reduction of the battery size, resulting in a smaller device, which in case of wearable systems, adds to user’s comfort.”

When most ICs were used in devices and systems that were powered by line current there was no advantage to minimizing power consumption, and so digital CMOS circuits could be designed with billions of transistors switching billions of times each second resulting in sufficient brute-force power to solve most problems. With power-consumption now a vital aspect of much of the demand for future chips, this year’s ISSCC offered the following tutorials on low-power chips:

  • “Ultra Low Power Wireless Systems” by Alison Burdett of Toumaz Group (UK),
  • “Low Power Near-threshold Design” by Dennis Sylvester of University of Michigan, and
  • “Analog Techniques for Low-Power Circuits” by Vadim Ivanov of Texas Instruments.

Then on Thursday the 26th, an entire short course was offered on “Circuit Design in Advanced CMOS Technologies:  How to Design with Lower Supply Voltages.” with lectures on the following:

  • “A Roadmap to Lower Supply Voltages – A System Perspective” by Jan M. Rabaey of UC Berkeley,
  • “Designing Ultra-Low-Voltage Analog and Mixed-Signal Circuits” by Peter Kinget of Columbia University,
  • “ACD Design in Scaled technologies” by Andrea Baschirotto of University of Milan-Bicocca, and
  • “Ultra-Low-Voltage RF Circuits and Transceivers” by Hyunchoi Shin of Kwangwoon University.

µW SoC Blocks

Session 5.10 covered “A 4.7MHz 53µW Fully Differential CMOS Reference Clock Oscillator with -22dB Worst-Case PSNR for Miniaturized SoCs” by J. Lee et al. of the Institute of Microelectronics (Singapore) along with researchers from KAIST and Daegu Gyeongbuk Institute of Science and Technology in Korea. While many SoCs for the IoT are intended for machine-to-machine networks, human interaction will still be needed for many applications so session 6.7 covered “A 2.3mW 11cm-Range Bootstrapped and Correlated-Double-Sampling (BCDS) 3D Touch Sensor for Mobile Devices” by L. Du et. al. from UCLA (California).

As indicated by the low MHz speed of the clock circuit referenced above, the only way that these ICs can consume 1/1000th of the power of mainstream chips is to operate at 1/1000th the speed. Also note that most of these chips will be made using 90nm- and 65nm-node fab processes, instead of today’s leading 22nm- and 14nm-node processes, as evidenced by session 8.3 covered “A 10.6µA/MHz at 16MHz Single-Cycle Non-Volatile Memory-Access Microcontroller with Full State Retention at 108nA in a 90nm Process” by V.K. Singhal et al. from the Kilby Labs of Texas Instruments (Bangalore, India). Session 18.3 covered “A 0.5V 54µW Ultra-Low-Power Recognition Processor with 93.5% Accuracy Geometric Vocabulary Tree and 47.5 Database Compression” by Y. Kim et al. of KAIST (Daejeon, Korea).

In the Low Power Digital sessions it was natural that ARM Cortex chips were the basis for two different presentations on ultra-low power functionality, since ARM cores power most of the world’s mobile processors, and since the RISC architecture of ARM was deliberately evolved for mobile applications. Session 8.1 covered “An 80nW Retention 11.7pJ/Cycle Active Subthreshold ARM Cortex-M0+ Subsystem in 65nm CMOS for WSN Applications” by J. Myers et al. of ARM (Cambridge, UK). In the immediately succeeding session 8.2, W. Lim et al. of the University of Michigan (Ann Arbor) presented on the possibilities for “Batteryless Sub-nW Cortex-M0+ Processor with Dynamic Leakage-Suppression Logic.”

nW Beyond Batteries

Session 5.4 covered “A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-Low Power Systems” by A. Shrivastava et al. of PsiKick (Charlottesville, VA). PsiKick’s silicon-proven ultra-low-power wireless sensing devices are based on over 10 years of development of Sub-Threshold (Sub-Vt) devices. They are claimed to operate at 1/100th to 1/1000th of the power budget of other low-power IC sensor platforms, allowing them to be powered without a battery from a variety of harvested energy sources. These SoCs include full sensor analog front-ends, programmable processing and memory, integrated power management, programmable hardware accelerators, and full RF (wireless) communication capabilities across multiple frequencies, all of which can be built with standard CMOS processes using standard EDA tools.

Extremely efficient energy harvesting was also shown by S. Stanzione et al. of Holst Centre/ imec/KU Leuven working with OMRON (Kizugawa, Japan) in session 20.8 “A 500nW Battery-less Integrated Electrostatic Energy Harvester Interface Based on a DC-DC Converter with 60V Maximum Input Voltage and Operating From 1μW Available Power, Including MPPT and Cold Start.” Such energy harvesting chips will power ubiquitous “smarts” embedded into the literal fabric of our lives. Smart clothes, smart cars, and smart houses will all augment our lives in the near future.

—E.K.

Solid State Watch: January 16-22, 2015

Thursday, January 22nd, 2015
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Air-gaps in Copper Interconnects for Logic

Friday, October 31st, 2014

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By Ed Korczynski, Sr. Technical Editor, SST/SemiMD

The good people at ChipWorks have released some of the first public data on Intel’s new 14nm-node process, and the results indicate that materials limitations in on-chip electrical interconnects are adding costs. Additional levels of metal have been added, and complex “air-gap” structures have been added to the dielectric stack. Flash memory chips have already used air-gaps, and IBM has already used a subtractive variant of air-gaps with >10 levels of metal for microprocessor manufacturing, but this is the first known use of additive air-gaps for logic after Intel announced that a fully-integrated process was ready for 22nm-node chips.

Mark Bohr of Intel famously published data in 1995 (DOI:  10.1109/IEDM.1995.499187) on the inherent circuit speed limitations of interconnects, showing proportionality to the resistance (R) of the metal lines multiplied by the capacitance (C) of the dielectric insulation around the metal (Fig.1). The RC product thus should be minimized for maximum circuit speed, but the materials used for both the metal and the dielectric insulation around metal lines are at limits of affordability in manufacturing.

There are no materials that super-conduct electricity at room temperature, and only expensive and room-sized supercomputers and telecommunications base-stations can afford to use the liquid-nitrogen cooling that is needed for known superconductors to function. Carbon Nano-Tubes (CNT) and 2D atomic-layers of carbon in the form of graphene can conduct ballistically, but integration costs and electrical contact resistances limit use. Copper metal remains as the best electrical conductor for on-chip interconnects, yet as horizontal lines and vertical vias continue to shrink in cross-sectional area the current density has reached the limit of reliability. The result is the increase in the number of metal layers to 13 for 14nm-node Intel microprocessors, while IBM used 15 layers for 22nm-node Power8 chips.

Low-k Dielectrics and Pore Sizes

The dielectric constant (“k”) of silicon oxide is ~4, and ~3.5 with the addition of fluorine to the oxide (SiOF). Carbon-Doped Oxide (CDO or SiOC or SiOC:H) with k~3.0 has been integrated well into interconnect stacks. Some polymers can provide k values in the 2.0-2.7, but they cannot be integrated into most interconnects due to lack of mechanical strength, chemical resistance, and overall stability. Air has k=1, and there have been specialized chips made using metal wires floating in air, but lack of physical structure results in poor manufacturing yield and weak reliability.

A clever compromise is to use both SiOC with k~3 and air with k~1 in a stack, which results in an integrated k value weighted by the percent of the volume taken up by each phase. Porous Low-k (PLK) with 10% porosity allows for an integrated k of ~2.7 for modest improvement, but increasing porosity to just 20% for k~2.4 results in connected random pores that reduce reliability. To reliably integrate 20-30% air into SiOC, the pores cannot be random but must be engineered as discrete gaps in the structure.

In 2007, IBM announced that it would engineer air-gaps in microprocessors, but the company claimed to be using an extremely complex process for integration involving a self-assembled thin-film mask to anisotropically etch out holes between lines and then further isotropic etching to form elongated pores. Though relatively complex and expensive, this process allows for the use of any 2D layout for lines in a given metal layer.

Additive Air-gap Process-Design Integration

For fab lines that are still working with aluminum metal and additive dielectrics, air-gaps are a defect that occurs with imperfect dielectric fill. When not planned as part of the design, air-gaps formed in a lower-layer can be exposed to etchants during subsequent processing resulting in metal shorts or opens. However, Figure 2 shows that it is possible to engineer air-gaps by Chemical-Vapor Deposition (CVD) of dielectric material into line-space structures with proper process control and design layout restrictions. Twenty years ago, this editor worked for an OEM on CVD processes for dielectric fill, and the process can be tuned to be highly repeatable and relatively low-cost if a critical masking step can be avoided. In 1998, Shieh et al. from Stanford (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) showed proof-of-concept for this approach to lower k values.

Figure 2: CVD can be easily tuned to initially coat sidewalls (top), then pinch-off (middle), and finally form a closed pore (bottom) during one step. (Source: Ed Korczynski)

Four years ago at IEDM 2010, Intel presented details of how to engineer air-gaps using CVD. As this editor wrote at that time in an extensive analysis:

The lithographic masking step is needed for two reliability reasons. First, by excluding air-gap formation in areas near next-layer vias, alignment between layers can be more easily done. Second, wide spaces are excluded where the final non-conformal CVD step wouldnt automatically pinch-off to close the gaps; leaving full SiOC(H) in wider spaces also helps with mechanical strength. The next layer is patterned with a conventional dual-damascene flow, with the option to add air-gaps.

Now we know that Intel kept air-gaps on the metaphorical shelf by skipping use at the 22nm-node. The 2014 IEDM paper from Intel will discuss details of 14nm-node air-gaps:   two levels at 80nm and 160nm minimum pitches, yielding a 17% reduction in capacitance delays.

This process requires regularly spaced 1D line arrays as a design constraint, which may also be part of the reason for additional metal layers to allow for 2D connections through vias. Due to lithography resolution advantages with 1D “gridded” layouts, other logic fabs may soon run 1D designs at which point additive air-gaps like that used by Intel will provide a relatively easy boost to IC speeds.

RF and MEMS Technologies to Enable the IoT

Friday, October 24th, 2014

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By Ed Korczynski, Sr. Technical Editor, Solid State Technology and SemiMD

The “Internet of Things” (IoT) has been seen as the next major market that will demand high volumes of integrated circuits (IC). The IoT can be loosely defined as a network of small, low-cost, ubiquitous electronic devices where sensing data and communicating information occurs without direct human intervention. Each device would function as a “smart node” in the network by doing some low-level signal processing to filter signals from noise, and to reduce the bandwidth needed for node-to-node communications. The nodes will need to communicate up to some manner of a “cloud” for secure memory storage and to bounce actionable information down to humans.

Figure 1 shows a conservative forecast of the global IoT market that was recently published by IDC. IDC expects the worldwide IoT installed base to experience a compound annual growth rate (CAGR) of 17.5% from 2013 to 2020, starting from 9.1 billion smart nodes installed at the end of 2013 and growing to 28.1 billion units by 2020.

FIGURE 1: Forecast for global IoT applications revenue 2013-2020. Note that smart node “intelligent systems/devices” provide the foundation for this huge growing market. (Source: IDC)

Due to the anticipated elastic-demand for IoT devices that would come from cost reductions, the forecasts for the number of IoT nodes ranges to 50 billion or even 80 billion by the year 2020, as documented in the recent online Pete’s Post “Don’t Hack My Light Bulb, Bro”. The post also provides an excellent overview of recent discussions regarding the host of additional technology and business challenges associated with the enterprise infrastructure and security issues surrounding the integration of vast streams of new information.

As shown in Figure 1, the smart nodes form the foundation for the whole IoT. Consequently, the world will need low-cost high-volume manufacturing (HVM) technologies to create the different functionalites needed for smart nodes. Sensor- and logic-technologies to enable IoT smart nodes will generally evolve from existing IC applications, while R&D continues in Radio Frequency (RF) communications and in Micro Electro-Mechanical Systems (MEMS) energy harvesting.

RF Technology

IoT smart-nodes will use wireless RF technologies to communicate between themselves and with the “cloud.” In support of rapid growth in the 71-86 GHz RF “E-band” telecom backhaul segment—which transports data from cell sites in the peripheral radio access network (RAN) to the wireless packet core—Presto Engineering recently announced a non-captive production-scale testing service for 50µm-thin gallium arsenide wafers.

Silicon-On-Insulator (SOI) substrate supplier Soitec has excellent perspective on the global market for RF chips, since it’s High-Resistivity SOI (HR-SOI) wafers are widely used in commercial fabs. Bernard Aspar, senior vice president and general manager of the Communications and Power business unit of Soitec, explained to SemiMD in an exclusive interview why the market for RF chips is growing rapdily. RF front-end module unit sales are forecasted to increase at a CAGR of ~16% over the period of 2013-2017, while the area of silicon needing to be delivered could actually increase at ~30% CAGR. RF chips are increasing in average size due to the need to integrate multiple standards for wireless communications and multiple antenna switches. “The first components to be integrated in silicon were the antenna switches, moving from 70% on GaAs in 2010 to more than 80% on SOI in 2014,“ said Aspar.

Soitec claims that >80% of smart-phones today use an RF chip built on a wafer from the company, based on sales last year of >300k 200mm HR-SOI wafers. Due to anticipated future growth in RF demand, the company has plans to eventually move HR-SOI production to 300mm diameter wafers. Most of the anticipated demand will be for the company’s new variant of HR-SOI called eSI (“enhanced Signal Integrity”previously called “Trap Rich”) with a measured effective resistivity as high as 10 kOhm-cm for improved device performance.

This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) and purely capacitive crosstalk similar to quartz substrates. HR-SOI substrates in general demonstrate reduced harmonics compared with standard SOI substrates, and the eSI wafers reduce harmonics to the point that they can be considered as lossless. Soitec was recently given a Best Partnership Award by Sony Semiconductor for supplying RF substrates.

“We’re also adding value to the substrate because it allows for simplification of the fab processing,” said Aspar. The eSI wafers enable much higher linearity and isolation, helping designers to address some of the most advanced LTE requirements at competitive costs. These substrates also provides benefits for the integration of passives, such as the quality factor of spiral inductors or tunable MEMS capacitors.

Vibrational Energy Harvesting

IoT smart nodes will need electrical power to function, and batteries that must be replaced or charged by an external source create issues for ubiquitous always-on small devices. In principle the ambient energies of the environment can be harvested to power smart nodes, and to do so we may consider using thermoelectric, photovoltaic, and piezoelectric properties of thin-films. Thermoelectric and photovoltaic devices both require somewhat specialized ambients for efficient energy harvesting, while piezoelectric devices can extract energy from subtle vibrations almost anywhere in the world (Fig. 2).

FIGURE 2: Schematic cross-section of piezoelectric cantilever with end mass, depicted in connection to an energy-harvesting circuit. (Source: Science)

Researchers in the Energy Harvesting and Mechatronics Research Lab at Stony Brook University, New York, recently published an excellent overview of the potential for 1 W to 100 kW piezoelectronic energy harvesting in building, automobiles, and wearables electronics in the Journal of Intelligent Material Systems and Structures 24(11) 1405-1430. However, the largest forecasted growth in the IoT is for small devices that would consume µW to mW of active power.

For low-cost and low-power consumption, the logic chips for IoT smart nodes are expected to be made using a 65nm “trailing edge” fab process. For example, CAST Inc. has developed a 32-bit BA20 embedded processor core that can deliver 3.41 CoreMarks/MHz at a maximum frequency of 75 MHz. Using TSMC’s 65nm Low Power fab process, it occupies only 0.01 mm2 of silicon area while consuming 2 µW/MHz. Thus, at maximum speed the chip core would consume just 150µW.

MicroGen Systems, Inc. (MicroGen) is a privately held company developing thin piezoelectric energy harvesters, based on technology from Cornell University’s NanoScale Science and Technology Facility. Founded in 2007, MicroGen has headquarters and R&D in the Ithaca and Rochester, NY areas, and volume manufacturing with X-FAB in Itzehoe, Germany. Figure 3 shows one of the company’s ~100 mm2 area chips featuring an aluminum nitride (AlN) peizoelectric thin-film on a cantilever that produces alternating current (AC) electricity in response to external vibrations. Different cantilever designs allow for harvesting energy from either single-frequency or broadband vibrations. At resonance the AC power output is maximized, so it can be ~100 µW at 120Hz and 0.1g, or ~900 µW at 600Hz and 0.5g.

FIGURE 3: BOLT™-R0600 energy-harvesting chip without packaging. The green-silver trapezoidal area is a 25-100µm thick cantilever (with several thin-film layers including an AlN piezoelectric) attached to grey rectangular end mass (silicon). A fixed-frequency device, at resonance of ~600Hz it can produce ~900 µWatts of AC power. (Source: MicroGen Systems)

For any piezoelectric energy harvester there are basic materials properties that must be optimized, including the piezoelectric strain constant as well as the electromechanical coupling factor of the thin-film to the moving mass. Lead-zirconium-titanate (PZT) has been the most studied piezoelectric thin-film due to high strain constant and ability to couple to a substrate though the use of buffer layers.

S. H. Baek, et al. showed “Piezoelectric MEMS with Giant Piezo Actuation” in Science 18 November 2011, Vol 344 using lead-manganese-niobate with lead-titanate (PMN-PT) layers epitaxially grown on a strontium-titanate (STO) buffer layer over 4°-off-axis(001)Si. Figure 4 shows both the transverse piezoelectric coefficient (C/m2) and the energy-harvesting figure of merit (GPa) for this and other thin-films. Note that to acheive stable “giant” piezoelectric effects the PMN-PT layer had to be grown epitaxially with precise control over the STO grain orientation.

FIGURE 4: Transverse piezoelectric coefficient (C/m2) and the energy-harvesting figure of merit (GPa) for PMN-PT (“this work”) and other piezoelectric thin-films. (Source: Science)

—E.K.

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