By Mark LaPedus, SemiMD senior editor

For years, the Semiconductor International Capacity Statistics (SICAS) organization has provided critical and valuable statistical data on semiconductor wafer fab capacity and utilization rates.

SICAS releases its figures on a quarterly basis for the public.  And simply put, it provides a pulse for the industry. But now the statistics are incomplete, as Nanya, TSMC, and UMC are no longer providing data to the group, according to Bill Jewell, president of Semiconductor Intelligence LLC, a consulting firm.

“SICAS data is no longer a good representation of industry capacity and utilization,’’ he said in an e-mail. This in turn will provide the IC industry with less data, insight and visibility about the state of the business, Jewell warned.

SICAS has released its data for the second quarter, but the organization has “significant changes in membership,” Jewell posted on his site. “The SICAS membership list no longer includes the Taiwanese companies Nanya Technology Corp., Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) or United Microelectronics Corp. (UMC).”

Semiconductor Intelligence estimates TSMC and UMC represented about 16 percent of total IC capacity in SICAS. “Thus, losing these companies has caused a major disruption in SICAS data and makes comparison of the 2Q 2011 data with previous quarters invalid in most categories,” Jewell said.

The only other change in SICAS participants is the omission of National Semiconductor. The National data may be included with Texas Instruments, which acquired National effective Sept. 27.

SICAS is a loosely-based organization made up of various chip makers. The U.S. Semiconductor Industry Association (SIA) funds the data collections points and distributes the SICAS report.

A spokeswoman for the SIA confirmed that Nanya, TSMC and UMC are no longer providing data for SICAS. “I can’t comment on why,” according to the spokeswoman. “You will have to ask them.”

The spokeswoman insisted that the SICAS data is meaningful despite the loss of TSMC and UMC, the world’s two top foundry vendors.

In an e-mail, TSMC said: ”I am not sure if we are no longer part of the SICAS. However, it is true that we have stopped providing detail capacity data to SICAS. We have routinely released our quarterly capacity plan by each fab and as a whole company. The data can be found on our web site. However, we do not disclose the details within each fab, such as how much capacity for each geometry, etc., as we believe such details are business secret and should not be released to the public, not to mention that these numbers do change from time to time when we migrate tools or switch them around to do specialty technologies.”

TSMC and UMC do release information on wafer capacity and shipments in their quarterly financial results. By taking those numbers to the SICAS figures, Semiconductor Intelligence says second quarter IC capacity, including TSMC and UMC, was 2,084 thousand wafers, up 1.6 percent from 2,052 thousand in 1Q 2011.

This was the fifth consecutive quarterly increase. IC capacity in 2Q 2011 was still 6 percent below the record capacity of 2,223 thousand wafers in 3Q 2008, according to Jewell.

The March 11, 2011 Japanese earthquake and tsunami also had some impact on capacity. Although the size of the impact is difficult to estimate, 2Q 2011 capacity and utilization would have been somewhat higher if not for the Japan disasters.

“The change in participants in SICAS is disappointing,” Jewell concluded. “SICAS has enjoyed fairly high participation rates since it was formed in 1995. As a member of the SICAS founding executive committee I remember the spirit of cooperation as foundry companies and integrated device manufacturers were willing to share data for the first time, with the goal of providing useful information for the entire semiconductor industry.”

by Ed Korczynski

Through-silicon vias (TSV) allow for 3D stacking of chips, as well as “2.5D” integration of multiple chips using silicon interposers. During SEMICON West 2011, Damo Srinivas, Novellus Systems’ senior director of 3D applications, sat down with Semiconductor Manufacturing and Design to talk about near-term 3D product trends and how responsibilities might shift between IC foundries and Outsourced Semiconductor Assembly and Test (OSAT) lines.

TSV in ICs have been in R&D for over 10 years, and are finally scheduled to reach commercial use in IC manufacturing this year. Vias will be made through silicon in DDR3 DRAM dice to reduce size and power consumption for mobile devices, as scheduled for sampling by Elpida in the 2nd-half of 2011. Typical vias through 10-50 micron thick ICs have used 5:1 to 10:1 aspect-ratios (AR) for copper electroplating. Next year should see more 3D chip stacks being sampled. “In four to five years, all the memory manufcturers will have to have TSV,” predicted Srinivas.

TSV through interposers will be made by many OSATs. For interposers, the final silicon target thickness will be 100-140µm. Interposer thickness cannot be reduced below 100 µm without rigid silicon wafers becoming flexible silicon foils. Interposers allow for easy heterogeneous integration of ICs, and also provide a great substrate for wafer-level integration of passive thin-film resistors, capacitors, and inductors.

“I think the interposer will be a bridge to 3D IC,” said Srinivas. “If you had sufficient volume with 2.5 interposers, then you could do a transiton to true 3D.” Novellus supports customers working on both directions, and also provides low-temperature deposition technologies for backside Re-Distribution Layer (RDL) interconnects.

OSAT Business Models

In addition to the many processing challenges associated with the technology, TSV will likely shake-out traditional business models in the IC industry. To fulfill their ultimate potential as means to provide 3D integration of heterogeneous IC technologies, TSV will trigger changes in the way the industry deals with OSATs.

OSATs are already feeling threatened by IDMs and IC foundries starting to do wafer-level packaging. TSMC, for example, has been expanding it’s offerings to provide more upsteam and downstream survices and today can take a design and return tested and packaged chips. The IC fabs will have to own the via-middle TSV process and perhaps the RDL, so they are actually bringing steps back in-house after decades of outsourcing more and more work.

However, for OSATs, TSV could represent the first time that real differentiations could be shown to customers. OSATs are still going to have to do the test, since IDMs don’t want to invest in test infrastructure. An OSAT could negotiate taking some of the wafer-level packaging in exchange for handling the needed test, and the wafer-level work could be highly specialized and add more value.

For dense package-level interconnects, inexpensive ball drop cannot be used. To get to the tightest needed interconnect pitches, some manner of metal plating technology is needed. TSV using Cu metal are particularly easy to integrate with Cu pillars. A hidden benefit in the use of Cu-pillars is that they cost less to plate than lead-free solder.

Managing TSV Backside Reveal

The backside reveal aspect of TSV formation is integrated with the wafer thinning. OSATs typically grind wafers with successively finer grade absrasives to thin down to near the final target, with perhaps 5 microns at most in residual crystalline damage in the silicon. CMP can reduce the damage layer significantly, and in principle a final ultra-low-pressure chemical polish step in CMP could eventually remove all damage.

Wafer or die thinning to 50 micron for wire-bonding—with no need for TSV—is relatively easy. However, once Cu TSV are embedded in via-middle process flows then the backside reveal becomes one of the trickier aspects of integration. If you use chemical or plasma etches for the reveal step then removal rate variations between different materials allows for tuning of the profile between the vias, the isoloation collars, and the silicon field. Purely mechanical mean of backside reveal will almost certainly smear the copper across the backside silicon surface, and so steps must be taken to somehow clean this contaminatation from the surface.

A residual smear of Cu could short a line and kill a circuit, and so the OSATs that will likely be responsible for TSV backside reveal in 3D chip stacks will have to manage the process well. This new process challenge will be an opportunity for OSATs to differentiate themselves and maybe even raise profit margins a bit.

By Ed Korczynski

Commercial fabs may start running through-silicon vias (TSV) in high-volume manufacturing (HVM) in 18 months, if R&D in both design and process keeps working well. Many companies presented data on the state-of-the-art in creating TSV to a cross-disciplinary gathering of the North California Chapter of the American Vacuum Society (NCCAVS) held at SEMI world headquarters last week. Applied Materials reviewed the best known unit-processes that have been integrated into different process flows around the world. Mentor Graphics showed progress in simulating mechanical stresses from the outer package all the way down to the strained-silicon in the transistors.

Sesh Ramaswami, of Applied Materials, explained that co-optimization between TSV unit-processes has led to a better understanding of trade-offs, and multi-dimensional analysis has led to optimized prototype flows. Interposers are already in risk production at TSMC. Regarding TSV through active silicon chips, “End of 2012 time frame is when our customers tell us that they want TSV capability in volume,” according to Ramaswami.

After considering other flows to form TSV through active silicon, the world has settled on two:

1. Via-Middle, TSV after transistors and tungsten but before multi-level Cu interconnect, with 3-5 micron diameter and 50 micron deep vias etched “blind” into full thickness wafers in the fab, and
2. Via-Last, TSV etched to a stop layer from the backside of thinned wafers temporarily-bonded to carriers at an OTAP, with 8-10 micron diameter and 50-100 micron deep vias.

The via-middle TSV etch being “blind” means that it never sees a stop layer and just etches for a certain time. “If you via-middle TSV etch depth uniformity is not good, then the backside will see tall pillars and short pillars,” explained Ramaswami. “A few years ago it used to be 5 to 10 microns variation within a single die. Today it’s within a few microns, and that’s manageable.”

People began with the original damascene fab processes. Now, unit processes have been developed specifically for TSV. Formerly, a 10 micron diameter via needed 3-4 microns of ECD Cu overburden to ensure complete fill, while new ECD recipes reduce the overburden to only 1-2 microns for easier removal using standard Cu CMP tools and modified recipes.

Cost-reduction constraints also create new process-integration issues. For example, Ti is ~5x cheaper than Ta gram for gram and so the former is used as the Cu barrier metal, but Ti reacts with the fluorine etch used during backside TSV reveal; the result is an additional constraint on the dielectric barrier between the metal and the silicon wafer. ”That’s why you need to think about the whole thing as one step,” reminds Ramaswami.

Simulate to iterate

Valeriy Sukharev, of Mentor Graphics, gave on overview of a DFM-like methodology for calculating the gate-to-gate variation of stress in 3D silicon stacks using TSV. His group is working on a simulation-based design verification flow for 3D IC stacks to determine across-die out-of-spec variations in electrical characteristics caused by mechanical stresses. Simulation is particularly important since it is difficult to directly measure stresses inside 3D IC stacks. The end goal is to be able to iterate in virtual space and more efficiently optimize functional/parametric yield and reliability.

The first step is package-scale simulation using finite element analysis (FEA) to generate a set of boundary conditions describing package-induced loads at the faces of already thinned dice. For this initial simulation, the complexity of one chip is approximated by “smear layers” with averaged characteristics of the composite material. For example, standard copper/low-k multi-layer interconnects are approximated by a proportional averaging of the mechanical properties of the copper and the dielectric. The preliminary target is to get the strain distributed throughout the chip stack, including on-chip interconnects and TSV.

Sukharev explained that more modeling and experimental work is needed before the precise stress inside of one transistor channel can be estimated. The challenge is not in modeling the relatively large TSV, but in modeling the relatively small SiGe stress regions and dielectric STI regions. In reality we have silicon islands separated by different surface materials, and stress distribution is thus highly non-homogenous. Mentor Graphics claims that it’s full-chip EDA tool can account for all of these non-homogeneities in modeling external stress. However, real-world chips also see significant local stress variations due to internal forces, such as from temperature variations and different material expansion-coefficients.

At SEMICON West 2011 in San Francisco on July 14, along with many SEMI sponsored events, SEMATECH in cooperation with Fraunhofer-IZFP will host a Stess Management for 3D ICs using TSV workshop. This will be the 5th in a series of product level workshops on stress management for 3D ICs, and this focus is on the via-middle TSV process flow through active silicon. The 6th workshop in the series is scheduled for SEMICON Europa in the fall.

by Ed Korczynski

Resistance-change Random Access Memory (RRAM or ReRAM) devices continue to be developed at labs and fabs around the world, as seen by more than 40 papers at the spring Materials Research Society (MRS) spring meeting which was held April 25-29 in San Francisco, California. RRAMs are based on resistive switching in metal oxides, such as titantia and niobia, that show memristor properties. With single-digit nanosecond switching-speeds and 10-year non-volatile data retention, RRAMs may represent the future of solid-state memory after DRAM and Flash devices eventually reach scaling limits below 22nm half-pitch.

Technically, the other devices competing with RRAM for the future of memory are themselves based on changes in resistance. Phase-change memory (PCM) using GST material switches between low- and high-resistance states, but requires large drive currents to heat the material to effect the phase-change. Spin-transfer-torque RAM (STT-RAM) is also read as a change in resistance, but the cell size is relatively large. RRAM devices built using cross-point arrays could provide the smallest, fastest, leanest, and cheapest non-volatile memory chips.

Between oral presentations and posters, the Spring 2011 MRS Meeting showed many different groups using different switching materials for RRAMs:

8 – TiO

7 – NiO

6 – Zn0:metal

4 – SiO:Cu

3 – HfO:metal

3 – TMO:metal

3 – polymers

2 – TaO

2 – SrTiO

1 – CuO

1 – HfSiO

1 – WO

1 – solid electrolyte

42 + 11 more novel materials in session Q10

= 53 total RRAM presentations.

HP Labs RRAM Update

Stan Williams’ group at HP Labs has led the world in memristor and RRAM R&D using the titania family of materials as the switch since 2006. They claim that their champion device switches in <2ns, and has world-record endurance of >1.2E10 cycles. Stan Williams provided a keynote address to an MRS workshop last year, in which he explained how his group finally discovered that the conducting channel consists of a 1-2nm thin TiO2 tunnel barrier adjacent to a ~30nm thick “magneli-phase” Ti4O7 layer. Modulating the width of the tunnel barrier through diffusion of oxygen-vacancies controls the electrical resistance of the stack.

This year, HP Labs updated their titania work by reporting on two different electroforming mechanisms seen in the same 50nm × 50nm crossbar memristive device. A “soft” electroforming step uses <140µAmp at ~5V to create a high-resistance mode, while a “hard” electroforming step uses ~250µAmp at ~9V to create a low resistance mode. The two switching modes possessed opposite switching polarities that shared a metastable intermediate resistance state. The two modes can be explained by two switching layers at the top- and bottom-electrode interfaces:

• intermediate state, the bottom layer is ON with conducting channels made of both oxygen-vacancies and charge-traps, while the top layer consists of a tunnel gap;
• OFF state, both layers consist of tunnel gaps; and
• ON state, the top layer is ON with conducting channels made of oxygen-vacancies, while the bottom layer consists of a tunnel gap.

J. Joshua (Jianhua) Yang, provided an update on HP Labs’s RRAM work by surprisingly stating that titanium-oxides have stability issues which may limit device lifetimes, but that tantalum-oxides are free of such issue. The titania family seems to show issues getting beyond 100-1000 cycles, due to excessive heating inside the switch material due to the tendency to apply overvoltage. The two phases of titania will react with each other during heating, so the ON/OFF resistance differences are not so stable. “You need stability, and larger oxygen stability in the materials,” explained Yang. Presumably, the world-record cycling performance using titania was achieved using careful limits on overvoltage.

To improve lifetime with overvoltage margin, HP now uses a tantalum-oxide switching layer, a platinum bottom-electrode, and a tantalum top-electrode. The company claims that this system should be scalable to <5nm, the switching speed is merely 5ns, and the resistance state should be stable for 10 years. TaOx as deposited is amorphous, and even after heating steps it may retain some amorphous character.

RRAM Electroforming Avoidance

The ability to create functional RRAMs without electroforming would provide a significant cost and yield advantage in manufacturing. Though there is still debate as to the exact nature of the solid-state ion-diffusion mechanism(s) responsible for the change in resistance, it is clear that proper stacks of nano-scale oxides and sub-oxides are needed. Consequently, once trial-and-error has identified an ideal materials stack, it is likely that a wafer-scale process flow will be found to create the desired stack without the need for electroforming. For example, annealing in a reducing ambient or solid-phase gettering techniques may be used to adjust the stoichiometry of thin-films.

Using a tungsten-plug from a 90nm node DRAM process flow as one electrode, researchers from Research Center Juelich (with funding from Intel) used TiO2 thickness of 25nm and a Pt/Ti top electrode to make inherently electroforming-free RRAMs (Session Q8.4). Initially the devices were found to be in an intermediate state, and can be SET with positive bias voltage to the low resistance state (LRS). Without bias the intermediate state undergoes a RESET process to a high resistance state (HRS). Under negative voltage bias both processes can be reversed and the device returns into the intermediate state. This flipping of the SET and RESET process from positive to negative bias voltage polarity and vice versa can repeatedly be adjusted in one device. This versatile switching scenario is possible due to the use of the low-workfunction Ti and W electrodes which result in low barriers to the oxide.

The Juelich process flow is as follows:

1. Plasma etch to clean the W plug,
2. Reactive sputter TiO2 (300W, 46sccm AR, 17 sccm O2), and
3. PVD of top-electrode.

The top-electrode was 30nm Pt with an optional 5nm layer of Ti or W below. “As long as there is a Pt/TiO2 interface we need forming,” explained Rainer Bruchhaus of Juelich. However, when using either W or Ti as a barrier between the Pt and TiO2 (while maintaining W as bottom electrode) they see no need for electroforming. In all cases, the voltage range is limited to +- 1V.

RRAM scalability

Much of the global interest in RRAM structures is due to the ability of cross-point memory architectures to be shrunk far more easily than other device structures. The process flow to make cross-point arrays is particularly attractive from an overlay perspective, since the top- and bottom-electrodes are perpendicular to each other and the switching material is patterned along with the top-electrode.

The world record for the smallest resistive memory element is currently held by the National Nano Device Laboratories (NNDL) in Taiwan, which showed a 9nm half-pitch functional RRAM at IEDM last December (Paper #19.1, “9nm Half-Pitch Functional Resistive Memory Cell with <1 µA Programming Current Using Thermally Oxidized Sub-Stochiometric WO_x Film,” C. Ho et al, National Nano Device Laboratories, Taiwan/University of California at Berkeley). It features the lowest reported programming current to date of just <1µA using tungsten-oxide, compared to ~20mA for phase-change memories. The device was built using nano-injection lithography which employs a chemical reaction activated with a finely controlled electron beam to deposit a hard-mask for etching, but could have used Nano-imprint Lithography (NIL) or other patterning to form the array.

For more details on the physics of these devices, Applied Physics A, Vol.A102, No.4 is a special issue on “Memristive and Resistive Devices and Systems,” and is now available for free download as individual PDFs.

by Ed Korczynski

Many presentations at SPIE Advanced Lithography this year focused on the need to shift from 2D to essentially 1D layouts in masks as double-patterning is pushed to ever smaller geometries. For the third year in a row Valery Axelrad of Sequoia Design Systems and Michael Smayling of Tela Innovations presented results from collaborations. Canon has been working with both companies for some time now. The update this year was a combined presentation from all three companies entitled, “Optical lithography applied to 20nm CMOS logic and SRAM” [7973-39].

Patterning 20nm node chips with 193nm lithography is difficult even with immersion technology, since the Metal-1 (M1) pitch will be ~64nm, which is well below the 80nm limit for single exposure. Pushing the limits is possible with double-patterning (DP) when each pattern to essentially a 1D layout: Gridded Design Rules (GDR) to make uniform arrays, followed by a “cut” pattern of selectively placed orthogonal line segments. The cut layer thus becomes the most critical in terms of lithographic parameters, with similarities to the hole patterns used in contact layers. For both critical layers, density variations arise due to differences between logic and memory areas.

With Optical Proximity Correction (OPC) now at the limit, source-mask optimization (SMO) improves margins at the resolution limit, but can only make major improvements to small cells or repetitive designs like memory. OPC has been used for full-chip manufacturability improvements at previous technology nodes, but will not converge these days. “Convergence problems always arise when you have near neighbors and correlations between them,” explained Axelrad.

The authors also considered fundamental lithographic manufacturability parameters such as Depth of Focus (DOF), Normalized Illumination Log Slope (NILS), and Mask Error Enhancement Factor (MEEF) before and after SMO. Working with Canon steppers, realistic lens distortions using experimentally obtained Jones-Zernike expansions as well as realistic entrance pupil illumination were obtained as inputs to models.

Co-Optimization of Layout and Lithography

Simultaneous optimization of layout patterns and lithography settings is made possible by the uniformity and repeatability of the lines/cuts patterns. Optimization variables for the cut layer include the cut geometry (width, height, serifs), illumination of the scanner lens entrance pupil, and grouping cuts in similar optical environments to allow for local OPC. The optimization was for the CD error across all cuts, which also reduces variation among cuts by getting all CDs close to the same target value. This reduction of variation substantially simplifies the layout and OPC and produces manufacturable designs including both SRAM and logic.

There are many ways to formalize GDR+cut DP litho, but Tela and partners propose the following 1D rules :

• Highly uniform 1D GDR layouts with sparse identical cuts,
• critical layers are cuts,
• all cuts identical to each other and tripled to ensure yield,
• cuts also on a fixed grid (avoiding difficult neighborhoods),
• interactions between cuts sufficiently small for local iterative OPC to converge using SMO, and
• Use of a M0 layer to reduce the number of cuts and improve uniformity of cut density.

An algorithm was developed to resolve OPC and SMO for critical cut and hole layers:

STEP1: SMO (a.k.a. “co-optimization”) to find optimal cut shape and size, and illumination of the scanner lens entrance pupil (source), using a small representative sample portion of the layout.

STEP2: Local layout correction (pseudo-OPC) using information from Step1 to create the ideal size for the rectangles at each location, some a little smaller and some a little larger. Typically only 3-5 iterations are needed reach <1 nm RMS CD for a 42 nm target CD, which takes 30-60 seconds on a quad-core CPU, for a total simulation time of ~2 hours on a single CPU for ~120 windows.

The test chip is a 100k MOSFET including 50 different standard cells for SRAM and logic, in 50 x 60 microns area, using a 3 x 3 microns SMO sample window. The optimal illumination is a horizontal dipole. Axelrad claimed that after this extensive Source-Mask Optimization (SMO) the critical dimension (CD) error could be <1 nm at best focus conditions for both logic and SRAM cells at the 20nm node.

by Ed Korczynski

Lithography is where design meets manufacturing, and so the SPIE Advanced Lithography (AL) conference this year was where Applied Materials and Magma Design Automation chose to launch their new collaborative solution to the problem of managing yield data when ramping the most complex ICs in high-volume manufacturing (HVM). As device features continue to shrink ever smaller than the 193nm of ArF steppers, process windows continue to shrink to reveal complex interdependent yield loss mechanisms. Add in new materials and evolving device structures, and the industry must be able to learn quickly about new yield-loss mechanisms and then efficiently pass that learning back to designers.

In an exclusive meeting with SemiMD during SPIE, representatives of the two companies explained that this new effort is not directed toward solving random yield defects—due to particles for example—but systematic defects due to intrinsic process-design interactions. With ever smaller process windows and interdependencies, maintaining past yields with established design-rule check (DRC) software, “isn’t possible without new methodology,” explained Erez Paran, Applied Materials’ Integrated Solutions Manager, Process Diagnostics and Control. “This solution is intended to enable manufacturing below the 20nm node.”

The companies report seeing a growing gap between simulation and actual manufacturing data. Even with the best optical-proximity correction (OPC) and other reticle-enhancement techniques (RET), masks still have yield-loss “hot spots” when printed into resist in real fabs. Consequently, unlike the traditional way of doing pre-tapeout simulation, this simulation is post-tapeout to be closer to real fab results. GlobalFoundries has reportedly been working with this for over a year now.

Yield management in deep-sub-micron IC fabs only gets more challenging. The traditional method of “binning” yield loss mechanisms starts to fail when the number of bins explodes, and just because a bin appears more frequently does not mean it will be the most critical. As an almost trivial example, post-OPC masks today include “dummy structures” that can short together without loosing any yield. Not all functional paths can be considered to be critical paths, and sorting the critical from the non-critical is one of the key filters to manage the data volume. The software dashboard provides automated visualization tools to overlay inspection data on design information (figure).

The inspection data shows geometries where there are particular process window limits. Since the limit is systematic and the process is necessarily inflexible, the only possible fix must come from the design using something like additional OPC. With proper data management, the information can be fed further backward within the EDA flow to modify the library level for additional designs. “So it’s sort of short-loop for immediate work, and helps designs go faster for future products in the same process node,” explained Paran.

Knights Data Base (KDB)—part of Magma since the 2006 acquisition of Knights Technology—is the foundation of this new yield management solution. “It’s not only a depository, but a well mined and well correlated data base at the bottom of it all,” said Ankush Oberai, general manager and vice president of Magma’s Fab Analysis Business Unit, “and that’s what makes our solution unique. There’s a lot of input from Applied Materials to this, it’s not just cobbling the two companies’ stuff together.”

The smallest pixel in the inspection tool is ~100nm today, and since some fabs are engaged with 20nm node pilot work, Erez explained that, “if you look at the number of structures you have today there can be five. So it becomes a matter of image processing, algorithms, search-engines, correlation-engines.”

The data base can compare inspection information to more than just a GDSII mask layout, including netlist levels. “Today, there is no single-pattern that can reflect the whole design, so it’s becoming more and more difficult,” said Oberai. “We can overlay the defect map on the layout map, and the layout map is now hierarchical and enriched with critcal path information.”

New fabless business models

When is a design closed? It used to be that passing DRC for a given process-design kit (PDK) meant that a chip should yield. Now the industry faces a time of complexities when designs to be modeled rely on multi-variate simulations based on statistics with varying degrees of confidence.

If following the PDK is necessary but not sufficient, then how can a small team of fabless designers get their chip to yield in a fab? “You can see a new market emerging of small and medium sized companies taking new designs and mediating or cleaning them for manufacturing,” explained Oberai. “You see many more starts ups at the chip level, the entry barrier is becoming lower.” However, the cost to get a lithography mask-set written for advanced IC manufacturing is still probably a million dollars.

Once all these changes have been absorbed, it will invariably be time for yet additional methodology innovation to manage ever increasing yield complexity. “Geometries are not going to stop shrinking, says Oberai, and expects only more data streams to be managed since, “Insitu sensor technologies will take a greater role so we can have predictive data.”

By Ed Korczynski

UPDATED

To know what’s happening in lithography for high-volume manufacturing (HVM) the SPIE Advanced Lithography conference and exhibit is the place to be. Presentations at the Nikon Precision and KLA-Tencor customer events the day before provide vital context. On Day 0 of the conference, Intel fellow Sam Sivakumar said EUV is too late for Intel’s 14nm node, and may be too late for the development of 10nm generation design-rules (DR). EUV could still be on time for single-exposure work in 16/14nm nodes at foundries and memory fabs, and many companies may use EUV to cut grid-lines made using 193i tools.

Before the industry can get to high-volume manufacturing (HVM) of commercial ICs in a fab, companies need to lock-in processes in pilot production. Before that, they must have design-rules (DR) set. Intel leads the world in the race to the smallest features, with the 32nm node in HVM, 22nm node now in pilot production, and 14nm node design rules already set for HVM in 2013. An Intel 10nm node in HVM would follow in 2015.

At Nikon’s LithoVision workshop, Sam Sivakumar, Intel fellow (figure), explained that the DR set for 14nm used 193nm-immersion double-patterning (193i-DP), and that for the 10nm node—featuring 20nm actual line width, and 40nm pitch—design rules will be frozen early in 2013. “So production EUV tools will be delivered too late to meet the need to develop DR for the 10nm node, though Intel remains committed to going into production with EUV” said Sivakumar. Regarding the possibility of re-insertion, it is possible but only after surmounting a barrier. “We’d need to reset the DR for EUV,” elaborated Sivakumar, “because it doesn’t make sense to use DR developed for 193i with EUV. The key point is that DR flexibility needs to be built in, so that we can smoothly insert EUV and derive maximum benefit.”

[UPDATE 3/1: In an evening panel session, Sivakumar asserted Intel's official position as, “Our primary plan is to use EUV for 10nm, but we need ArF double-patterning as a backup.” Intel will have a pre-production 3100 tool this year, and likely will want a production 3300 whenever available. “When going to immersion, it took us well over a year to be able to get the defectivity levels down to that of dry. I'm hoping that all the learnings that will come from the 3100 will map to the 3300.”]

[UPDATE 3/2: In an exclusive followup meeting with SemiMD, Sivakumar explained that Intel has long planned to do 14nm node pilot using EUV, and should be on schedule with the shipment of the 3100 to meet plans. Many of the learnings to be found during pilot, such as SMO-dependencies, should map to HVM so there is confidence that the technology will be capable of ramping into 10nm node production.]

Discussing lithographic CoO for 22nm node patterning, Hidetami Yaegashi of TEL showed data that 193i double-patterning (193i-DP) should be less than EUV running at 150 wph and perhaps only 50% of EUV running at 60 wph.

Any delays in EUV seem to be due to the tough science and engineering challenges associated with sources and resists, while stepper OEMs have been meeting their development commitments.

Leading off Day 1, Luc Van den hove, IMEC president and CEO, announced in his plenary keynote that ASML started shipping the new NXE: 3100 “pre-production” EUV stepper/scanner to IEC last week, using 20 trucks. “The body is being installed even as we speak here,” (figure) announced Van den hove. Source and resist improvements could get us to 6o wph in another year, but all bets are off the table for when ASML could double that. He also said that flare in the new tool is only ~4% compared to 8-10% for the “alpha-demo-tool” first installed.

Next in the morning was the plenary keynote by Shang-yi Chiang, senior vice president of R&D at TSMC, who said “most people believe that Moore’s Law is nearing the end…whether we can extend Moore’s Law into the next decade is in your hands.” The eventual limit will be economic, not technical. “Within transistor and interconnect technology developments we do not see any roadblocks,” he explained. “So the lithography cost is the single greatest factor which may limit our ability to extend Moore’s Law into the next decade.” TSMC’s CoO modeling indicates that 100-150wph EUV should cost less than 193i-DP for 14nm nodes and beyond.

Franklin Kalk, Toppan Photomasks VP, met this afternoon with SemiMD to discuss the many known challenges with lithography for the 22nm node and beyond. Kalk sees pragmatic evolution of optical technologies continuing. Metaphorically speaking, we’re not about to crash into the ground. “I feel like we’re going to land and everything will be OK,” reassured Kalk. “But we may need reverse thrusters to not run off the runway, and we may land on one wheel and bounce a bit.”

by Ed Korczynski

After years of debate and development, air gaps are finally seeing commercial introduction in Flash interconnects. An IEDM 2010 paper presented by Kirk Prall of Micron Technology and Krishna Parat of Intel described the interconnect technology used for the companies’ 25nm multi-level-cell 64 Gbit NAND, which includes air-gaps in low-k dielectric materials (figure).

The disclosure follows details first shown by Intel at the International Interconnect Technology Conference (IITC 2010) on the reliability of air-gaps for electrical insulation in nano-scale devices. While other companies have shown tests of air-gaps, this is the first time that a commercial chip has been designed using air-gaps. Prior Flash chips from many manufacturers have had air-gaps, but seemingly only as anticipated accidents. Philips (now NXP) and IBM have reported on air-gaps for logic chips, but thus far without product commitments.

To reduce the dielectric constant (k) in shrinking integrated circuits (IC), there once was a roadmap for new materials to be deployed with ever lower k at each node. However, integration challenges in practice limited new materials to essentially two moves over the last 15 years: from SiO2 (k~4) to SiOF (k~3.5) and then to SiOCH (k~3). Because solid materials with k<3 have generally not met integration requirements for mechanical stability, much effort was expended to try to add pores (with k~1) to SiOCH to make a porous-low-k (PLK) dielectric with bulk k value proportional to the percent of air incorporated. PLK with porosity up to ~10% allows for k~2.7, and such a film can be integrated with minimal extra work (perhaps just a UV stabilization anneal step) compared to pure SiOCH. However, adding porosity >10% mandates the use of extra barrier/cap layers that almost always combine to produce new failure mechanisms, and the extra layers add capacitance to the whole dielectric stack such that the “effective-k” (keff) tends to end up back at ~2.7 after integration.

At an abstract conceptual level, an air-gap in a dielectric may be considered as a limiting case of PLK, where there is merely one large pore designed into the center of the structure. This is different from “air-bridges” where all solid and liquid dielectric is removed from interconnect structures. Some solid SiOCH dielectric remains around the air-gaps to provide mechanical strength and chemical barrier.

At IEDM 2010, Hynix R&D Division researcher Sungjoo Hong discussed the challenges of continued scaling of NAND Flash technology based on the floating gate (FG) architecture. Scaling has created word-line (WL) to WL spacings such that cross-coupling effects now decrease programming speed. Hong stated that air-gap technology can minimize cross-coupling, but it is necessary to control the integrated process for precise uniformity.

In 2006, researchers from Philips (working with ST, Leti, and IMEC) presented an outstanding paper at the Materials Research Society (MRS) spring meeting on “Benefits and Trade-offs in Multi-Level Air Gap Integration” (Ref: MRS Symp. F Proc. Vol.914). The paper provides a thorough overview of the possible variations on the air-gap theme: generally either additive using CVD or subtractive using a plasma/furnace/vacuum chamber.

One year later, IBM showed subtractive air-gaps integrated into an interconnect stack as proof of concept, using either lithography or self-assembled monolayers to mask off areas around the gaps. At IITC2010, Intel researchers reported that their air gap integration tests have so far resulted in no new failure modes observed. This is highly significant since almost any material change results in new ways for things to fail.

Additive air-gaps: pinching off bread loaves free

For over twenty years, air-gaps have been seen as defects in dielectrics deposited between metal lines. This editor once ran the application lab for Watkins-Johnson (W-J) atmospheric pressure chemical-vapor deposition (APCVD) systems, and learned that any CVD tool can be tuned to produce air-gaps in between lines of equal spacing. As the line sidewalls get coated the cross-section of the coating starts to look like a “bread-loaf” on each side until the top sides “pinch-off” to form an “air-gap” (figure). If you are working with subtractive metal patterning like that for aluminum or tungsten then additive air-gaps can come free with the dielectric deposition.

If you are working with additive metal like copper then additive air-gaps cost an extra etch and deposition step. Of course in either case, the “gap” is really an elongated bubble, and the “air” inside is a combination of the ambient inside the CVD chamber along with trace vapors from the dielectric material.

ChipWorks (the IC reverse-engineering experts in Ottawa) have cross-sectioned commercial memory chips for many years, and often observed dielectric voids in NAND Flash structures. “We have seen voids in between the wordlines of NAND Flash chips, in structures that appear to be not too different from what have been regular in memory,” said ChipWorks’ senior technology advisor Dick James. “We’ve seen voids at ~50nm half-poly-pitch in NAND chips. Even at ~90nm there have been variable voids.”

However, the voids seen so far in commercially available NAND chips appear to be incidental, since they vary in size from gate to gate and sometime disappear entirely (figure). Since ChipWorks has SEM cross-sections of chips from Micron, Samsung, and Toshiba all showing sporadic air-gaps, and since none of these companies had declared air-gaps as intentional design elements, it appears likely they truly were anticipated accidents. Anticipated since the design and manufacturing must allow for air-gaps to be present, yet accidental since the air-gaps may not appear in any one place. Generally speaking, the repeating structures of memory chips makes such anticipated accidental integration possible, while random logic structures don’t allow for such accidents.

Subtractive air-gaps: staying between the lines

To control where air-gaps form outside of periodically structured arrays, another lithography step may be needed to align an etch mask, as shown by Philips and IBM. During their IEDM presentation, Micron and Intel did not detail the air-gap integration processes used for the WL and bitline (BL) dielectrics. However, since the two cross-sections appear differently in the IEDM paper, they probably used different processes. The WL direction looks similar to the WL seen by ChipWorks in previous NAND structures, so was probably formed additively. Presuming the designers are given forbidden pitches to avoid in a layer, the air-gaps could truly come free without even the need for a “non-critical” mask to block out inconvenient areas.

Air-gaps may soon appear in logic structures as well. Since it appears likely that the 22/20nm node of logic will rely upon 1D grid layouts, such severely restricted-design-rules (RDR) will already include forbidden pitches. Consequently, pinch-off additive air-gaps could easily be tuned into CVD processes for dielectrics. If subtractive air-gap flows are needed, then array patterns still allow for relatively easier patterning. Both Intel and IBM are now in top-secret pilot production with this node, but within the year we should learn whether air-gaps are only for memory or whether they will be the mainstream low-k dielectric solution for all future ICs.