by Ed Korczynski
After years of debate and development, air gaps are finally seeing commercial introduction in Flash interconnects. An IEDM 2010 paper presented by Kirk Prall of Micron Technology and Krishna Parat of Intel described the interconnect technology used for the companies’ 25nm multi-level-cell 64 Gbit NAND, which includes air-gaps in low-k dielectric materials (figure).
Intel/Micron 25nm node NAND Flash structures using air-gaps in a) the wordline direction to reduce floating-gate interference by 25%, and b) the bitline direction to reduce capacitance by 30%. (source: IEDM2010 S05P02)
The disclosure follows details first shown by Intel at the International Interconnect Technology Conference (IITC 2010) on the reliability of air-gaps for electrical insulation in nano-scale devices. While other companies have shown tests of air-gaps, this is the first time that a commercial chip has been designed using air-gaps. Prior Flash chips from many manufacturers have had air-gaps, but seemingly only as anticipated accidents. Philips (now NXP) and IBM have reported on air-gaps for logic chips, but thus far without product commitments.
To reduce the dielectric constant (k) in shrinking integrated circuits (IC), there once was a roadmap for new materials to be deployed with ever lower k at each node. However, integration challenges in practice limited new materials to essentially two moves over the last 15 years: from SiO2 (k~4) to SiOF (k~3.5) and then to SiOCH (k~3). Because solid materials with k<3 have generally not met integration requirements for mechanical stability, much effort was expended to try to add pores (with k~1) to SiOCH to make a porous-low-k (PLK) dielectric with bulk k value proportional to the percent of air incorporated. PLK with porosity up to ~10% allows for k~2.7, and such a film can be integrated with minimal extra work (perhaps just a UV stabilization anneal step) compared to pure SiOCH. However, adding porosity >10% mandates the use of extra barrier/cap layers that almost always combine to produce new failure mechanisms, and the extra layers add capacitance to the whole dielectric stack such that the “effective-k” (keff) tends to end up back at ~2.7 after integration.
Cross-sectional schematic of CVD filling the space between two lines where a) first the deposition is relatively conformal, then b) a “bread-loaf” profile at top corners grows, such that c) the top “pinches-off” to form an additive air-gap. (source: BetaSights)
At an abstract conceptual level, an air-gap in a dielectric may be considered as a limiting case of PLK, where there is merely one large pore designed into the center of the structure. This is different from “air-bridges” where all solid and liquid dielectric is removed from interconnect structures. Some solid SiOCH dielectric remains around the air-gaps to provide mechanical strength and chemical barrier.
At IEDM 2010, Hynix R&D Division researcher Sungjoo Hong discussed the challenges of continued scaling of NAND Flash technology based on the floating gate (FG) architecture. Scaling has created word-line (WL) to WL spacings such that cross-coupling effects now decrease programming speed. Hong stated that air-gap technology can minimize cross-coupling, but it is necessary to control the integrated process for precise uniformity.
In 2006, researchers from Philips (working with ST, Leti, and IMEC) presented an outstanding paper at the Materials Research Society (MRS) spring meeting on “Benefits and Trade-offs in Multi-Level Air Gap Integration” (Ref: MRS Symp. F Proc. Vol.914). The paper provides a thorough overview of the possible variations on the air-gap theme: generally either additive using CVD or subtractive using a plasma/furnace/vacuum chamber.
One year later, IBM showed subtractive air-gaps integrated into an interconnect stack as proof of concept, using either lithography or self-assembled monolayers to mask off areas around the gaps. At IITC2010, Intel researchers reported that their air gap integration tests have so far resulted in no new failure modes observed. This is highly significant since almost any material change results in new ways for things to fail.
Additive air-gaps: pinching off bread loaves free
For over twenty years, air-gaps have been seen as defects in dielectrics deposited between metal lines. This editor once ran the application lab for Watkins-Johnson (W-J) atmospheric pressure chemical-vapor deposition (APCVD) systems, and learned that any CVD tool can be tuned to produce air-gaps in between lines of equal spacing. As the line sidewalls get coated the cross-section of the coating starts to look like a “bread-loaf” on each side until the top sides “pinch-off” to form an “air-gap” (figure). If you are working with subtractive metal patterning like that for aluminum or tungsten then additive air-gaps can come free with the dielectric deposition.
If you are working with additive metal like copper then additive air-gaps cost an extra etch and deposition step. Of course in either case, the “gap” is really an elongated bubble, and the “air” inside is a combination of the ambient inside the CVD chamber along with trace vapors from the dielectric material.
ChipWorks (the IC reverse-engineering experts in Ottawa) have cross-sectioned commercial memory chips for many years, and often observed dielectric voids in NAND Flash structures. “We have seen voids in between the wordlines of NAND Flash chips, in structures that appear to be not too different from what have been regular in memory,” said ChipWorks’ senior technology advisor Dick James. “We’ve seen voids at ~50nm half-poly-pitch in NAND chips. Even at ~90nm there have been variable voids.”
SEM cross-section of the wordlines in a Samsung 90nm branded NAND Flash chip, showing air-gaps formed between some of the lines as beneficial accidents of processing. Micron and Toshiba NAND Flash chips show similar accidental air-gaps appearing at the 90nm node and in all smaller chips. (source: ChipWorks)
However, the voids seen so far in commercially available NAND chips appear to be incidental, since they vary in size from gate to gate and sometime disappear entirely (figure). Since ChipWorks has SEM cross-sections of chips from Micron, Samsung, and Toshiba all showing sporadic air-gaps, and since none of these companies had declared air-gaps as intentional design elements, it appears likely they truly were anticipated accidents. Anticipated since the design and manufacturing must allow for air-gaps to be present, yet accidental since the air-gaps may not appear in any one place. Generally speaking, the repeating structures of memory chips makes such anticipated accidental integration possible, while random logic structures don’t allow for such accidents.
Subtractive air-gaps: staying between the lines
To control where air-gaps form outside of periodically structured arrays, another lithography step may be needed to align an etch mask, as shown by Philips and IBM. During their IEDM presentation, Micron and Intel did not detail the air-gap integration processes used for the WL and bitline (BL) dielectrics. However, since the two cross-sections appear differently in the IEDM paper, they probably used different processes. The WL direction looks similar to the WL seen by ChipWorks in previous NAND structures, so was probably formed additively. Presuming the designers are given forbidden pitches to avoid in a layer, the air-gaps could truly come free without even the need for a “non-critical” mask to block out inconvenient areas.
Air-gaps may soon appear in logic structures as well. Since it appears likely that the 22/20nm node of logic will rely upon 1D grid layouts, such severely restricted-design-rules (RDR) will already include forbidden pitches. Consequently, pinch-off additive air-gaps could easily be tuned into CVD processes for dielectrics. If subtractive air-gap flows are needed, then array patterns still allow for relatively easier patterning. Both Intel and IBM are now in top-secret pilot production with this node, but within the year we should learn whether air-gaps are only for memory or whether they will be the mainstream low-k dielectric solution for all future ICs.