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Comfortable Consumer EEG Headset Shown by Imec and Holst Centre

Thursday, August 27th, 2015


By Ed Korczynski, Sr. Technical Editor

A new wireless electroencephalogram (EEG) headset that is comfortable while providing medical-grade data acquisition has been shown by the partnership of imec, the Holst Centre, and the Industrial Design Engineering (IDE) department of TU Delft. The 3D-printed low-volume product enables early research and self-monitoring of emotions and mood in daily life situations using a smartphone application. Consumer applications include games that monitor relaxation and/or concentration, and medical applications that help with sleep disorders and treatment of Attention Deficit Hyperactivity Disorder (ADHD).

Figure 1 shows the new headset with novel elastic electrode arrays in an elegant uni-body assembly to optimize both comfort and signal quality. The electronics package in the middle of the headset fits on the back of the user’s neck. Each electrode is a small array of elastic polymer fingers which allow for dry contact—without needing a conductive liquid or gel—to skin for long-term comfortable use.

Figure1: Comfortable EEG headset developed by imec and Holst Centre and TU Delft in 2015, providing medical-quality data tracing of emotions and mood in daily life situations using a smartphone application. (Source: imec)

“Leveraging imec’s strong background in EEG sensing, dry polymer and active electrodes, miniaturized and low-power data acquisition, and low-power wireless interfaces to smartphones, we were able to focus on the ergonomics of this project. In doing so, we have successfully realized this unique combination of comfort and effectiveness at the lowest possible cost to the future user,” stated Bernard Grundlehner, EEG system architect at imec.

In 2011, imec and Holst Centre created an 8-channel ultra-low-power analog readout application-specific integrated circuit (ASIC) that consumes only 200µW and features high common mode rejection ratio (CMRR) of 120dB and signal to noise ratio of 25dB on real EEG signals. This ASIC is tuned to high input impedance (1GΩ) for compatibility with the use of dry electrodes. That system—including ASIC, radio, and controller chips— could be integrated in a package of 25mmx35mmx5mm dimensions for easy of integration in headsets, helmets, or other accessories. That system consumes only 3.3mW for continuous recording and wireless transmission of 1 channel—9.2mW for 8 channels—allowing for 1.5 to 4 days of functionality when powered by a 100mAh Li-ion battery.

In 2009, imec and Holst Centre showed off a rough mobile EEG prototype to partners and journalists at the yearly imec Technology Forum. Figure 2 shows that the prototype was bulky and a bit awkward to wear, while the figure does not show that sintered silver/silver-chloride electrodes are very hard such that dry contact to the human scalp tends to be uncomfortable.

Figure2: Ed Korczynski tests an imec EEG headset rough prototype, using uncomfortable hard silver/silver-chloride electrodes, at the 2009 Imec Technology Forum. (Source: Ed Korczynski)

The 2015 model uses new flexible electrodes arrays which are inherently more comfortable than hard silver/silver-chloride electrodes. A team of six master students from IDE of TU Delft led the design optimization of the 3D unibody for the new headset using 3D printing for short-loop prototyping and testing of different shapes for stability and comfort. Iterative tests with users for multiple applications led to this design which is intended for long-term comfortable use by consumers outside of a controlled research environment.

The new EEG headset is manufactured in one piece using 3-D printing, after which the electronic components are placed, connected, and covered by a 3-D-printed rubber inlay. The EEG electrodes are situated at the front of the headset for optimal acquisition of signals related to emotion and mood variations. A mobile app can then tie the user’s emotional state to environmental information such as location, time, agenda, and social context to track possible unconscious effects.


Managing Dis-Aggregated Data for SiP Yield Ramp

Monday, August 24th, 2015


By Ed Korczynski, Sr. Technical Editor

In general, there is an accelerating trend toward System-in-Package (SiP) chip designs including Package-On-Package (POP) and 3D/2.5D-stacks where complex mechanical forces—primarily driven by the many Coefficient of Thermal Expansion (CTE) mismatches within and between chips and packages—influence the electrical properties of ICs. In this era, the industry needs to be able to model and control the mechanical and thermal properties of the combined chip-package, and so we need ways to feed data back and forth between designers, chip fabs, and Out-Sourced Assembly and Test (OSAT) companies. With accelerated yield ramps needed for High Volume Manufacturing (HVM) of consumer mobile products, to minimize risk of expensive Work In Progress (WIP) moving through the supply chain a lot of data needs to feed-forward and feedback.

Calvin Cheung, ASE Group Vice President of Business Development & Engineering, discussed these trends in the “Scaling the Walls of Sub-14nm Manufacturing” keynote panel discussion during the recent SEMICON West 2015. “In the old days it used to take 12-18 months to ramp yield, but the product lifetime for mobile chips today can be only 9 months,” reminded Cheung. “In the old days we used to talk about ramping a few thousand chips, while today working with Qualcomm they want to ramp millions of chips quickly. From an OSAT point of view, we pride ourselves on being a virtual arm of the manufacturers and designers,” said Cheung, “but as technology gets more complex and ‘knowledge-base-centric” we see less release of information from foundries. We used to have larger teams in foundries.” Dick James of ChipWorks details the complexity of the SiP used in the Apple Watch in his recent blog post at SemiMD, and documents the details behind the assumption that ASE is the OSAT.

With single-chip System-on-Chip (SoC) designs the ‘final test’ can be at the wafer-level, but with SiP based on chips from multiple vendors the ‘final test’ now must happen at the package-level, and this changes the Design For Test (DFT) work flows. DRAM in a 3D stack (Figure 1) will have an interconnect test and memory Built-In Self-Test (BIST) applied from BIST resident on the logic die connected to the memory stack using Through-Silicon Vias (TSV).

Fig.1: Schematic cross-sections of different 3D System-in-Package (SiP) design types. (Source: Mentor Graphics)

“The test of dice in a package can mostly be just re-used die-level tests based on hierarchical pattern re-targeting which is used in many very large designs today,” said Ron Press, technical marketing director of Silicon Test Solutions, Mentor Graphics, in discussion with SemiMD. “Additional interconnect tests between die would be added using boundary scans at die inputs and outputs, or an equivalent method. We put together 2.5D and 3D methodologies that are in some of the foundry reference flows. It still isn’t certain if specialized tests will be required to monitor for TSV partial failures.”

“Many fabless semiconductor companies today use solutions like scan test diagnosis to identify product-specific yield problems, and these solutions require a combination of test fail data and design data,” explained Geir Edie, Mentor Graphics’ product marketing manager of Silicon Test Solutions. “Getting data from one part of the fabless organization to another can often be more challenging than what one should expect. So, what’s often needed is a set of ‘best practices’ that covers the entire yield learning flow across organizations.”

“We do need a standard for structuring and transmitting test and operations meta-data in a timely fashion between companies in this relatively new dis-aggregated semiconductor world across Fabless, Foundry, OSAT, and OEM,” asserted John Carulli, GLOBALFOUNDRIES’ deputy director of Test Development & Diagnosis, in an exclusive discussion with SemiMD. “Presently the databases are still proprietary – either internal to the company or as part of third-party vendors’ applications.” Most of the test-related vendors and users are supporting development of the new Rich Interactive Test Database (RITdb) data format to replace the Standard Test Data Format (STDF) originally developed by Teradyne.

“The collaboration across the semiconductor ecosystem placed features in RITdb that understand the end-to-end data needs including security/provenance,” explained Carulli. Figure 2 shows that since RITdb is a structured data construct, any data from anywhere in the supply chain could be easily communicated, supported, and scaled regardless of OSAT or Fabless customer test program infrastructure. “If RITdb is truly adopted and some certification system can be placed around it to keep it from diverging, then it provides a standard core to transmit data with known meaning across our dis-aggregated semiconductor world. Another key part is the Test Cell Communication Standard Working Group; when integrated with RITdb, the improved automation and control path would greatly reduce manually communicated understanding of operational practices/issues across companies that impact yield and quality.”

Fig.2: Structure of the Rich Interactive Test Database (RITdb) industry standard, showing how data can move through the supply chain. (Source: Texas Instruments)

Phil Nigh, GLOBALFOUNDRIES Senior Technical Staff, explained to SemiMD that for heterogeneous integration of different chip types the industry has on-chip temperature measurement circuits which can monitor temperature at a given time, but not necessarily identify issues cause by thermal/mechanical stresses. “During production testing, we should detect mechanical/thermal stress ‘failures’ using product testing methods such as IO leakage, chip leakage, and other chip performance measurements such as FMAX,” reminded Nigh.

Model but verify

Metrology tool supplier Nanometrics has unique perspective on the data needs of 3D packages since the company has delivered dozens of tools for TSV metrology to the world. The company’s UniFire 7900 Wafer-Scale Packaging (WSP) Metrology System uses white-light interferometry to measure critical dimensions (CD), overlay, and film thicknesses of TSV, micro-bumps, Re-Distribution Layer (RDL) structures, as well as the co-planarity of Cu bumps/pillars. Robert Fiordalice, Nanometrics’ Vice President of UniFire business group, mentioned to SemiMD in an exclusive interview that new TSV structures certainly bring about new yield loss mechanisms, even if electrical tests show standard results such as ‘partial open.’ Fiordalice said that, “we’ve had a lot of pull to take our TSV metrology tool, and develop a TSV inspection tool to check every via on every wafer.” TSV inspection tools are now in beta-tests at customers.

As reported at 3Dincites, Mentor Graphics showed results at DAC2015 of the use of Calibre 3DSTACK by an OSAT to create a rule file for their Fan-Out Wafer-Level Package (FOWLP) process. This rule file can be used by any designer targeting this package technology at this assembly house, and checks the manufacturing constraints of the package RDL and the connectivity through the package from die-to-die and die-to-BGA. Based on package information including die order, x/y position, rotation and orientation, Calibre 3DSTACK performs checks on the interface geometries between chips connected using bumps, pillars, and TSVs. An assembly design kit provides a standardized process both chip design companies and assembly houses can use to ensure the manufacturability and performance of 3D SiP.


Low-Cost Manufacturing of Flexible Functionalities

Wednesday, July 15th, 2015


By Ed Korczynski, Sr. Technical Editor

SEMICON West includes many business and technology workshops and forums for attendees.  On Wednesday morning July 15, attendees packed the TechXPOT in the South Hall of Moscone Center to hear updates on the status of flexible hybrid electronics manufacturing.

M-H. Huang of Corning showed the surprising properties of “Corning Willow Glass: Substrates for flexible electronic devices.” Willow Glass is created in a fusion-forming process similar to that used to create Gorilla Glass, though with thickness <=200 microns to allow for flexibility. “A key advantage is hermeticity compared to plastic substrates,” reminded Huang. Thin bare glass without any edge or surface coatings can be repeatably bent and twisted without cracking. The minimum bending radius for roll-to-roll (R2R) processing is limited by coating layer delamination:  12.5mm for bare glass, 25mm for AZO-coated glass, and 50mm radius for CZTS cells on glass all passing 500 bending cycles at 60 cycles per minute. Working with the State University of New York at Binghamton Center for Advanced Microelectronic Manufacturing (CAMM), Corning has demonstrated R2R sputtering of Al, Cr/Cu, ITO, SiO2, and IGZO films. Collaborating with ITRI in Taiwan using tools designed specifically for processing flexible glass, Corning demonstrated R2R gravure-offset printing of metal mesh structures silver ink that can be used for 7” touch-panels. Working with both CAMM and ITRI has led to R&D fabrication of a touch sensor with 90% device yield.

Thomas Lantzer, of DuPont Electronic Materials, discussed the “Materials Supplier Perspective on Flexible Hybrid Electronics.” Since the overarching goal of flexible electronics is not just mass and volume reduction but a huge reduction in manufacturing cost, it is axiomatic that fabrication must evolving toward the use of traditional printing methods and flexible substrates.

“There are many printing techniques,” explained Lantzer, “So there are building blocks out there today that we feel will lead to an explosion of fabrication capabilities in the future.” DuPont has been actively involve in flexible materials and electronics for decades, supplying screen printed conductive pastes, resistor pastes for automotive defoggers, flexible films, and flexible materials for copper circuitry.

Mark Poliks, Professor at the State University of New York at Binghamton and Director of the Center for Advanced Microelectronic Manufacturing (CAMM), provided a comprehensive overview of “Materials, Processes & Tools for Fabrication of Flexible Hybrid Electronics.” Working with partners in the Nano-Bio Manufacturing Consortium since 2013, CAMM researchers are developing a wearable disposable sensor system with a target price of $2 to measure human performance parameters. The device including sensors, processor, battery, and wireless communications blocks will be built with copper (Cu) connections on flexible substrates such as polyimide. Initial functionalities will include biometric parameters such as electro-cardio-gram (ECG) signals and skin temperature. First prototypes of ECG sensors on 12.5 micron thin polyimide have been completed, which demonstrate output wave forms with equal or better signal extraction compared to industry standard silver/silver-chloride (Ag/AgCl) electrodes. This new printed sensor and breadboard electronics can be flexed over 200 times and retain the same signal quality and heart-beat extraction. The flexible substrate can accommodate assembly processes for flip-chip (FC) ASIC dice having micro-bumps on a 70 micron pitch, using die-placement accuracy of 9 microns (3 sigma). For flexible hybrid applications, dual-sided placement of components along with printed circuitry reduces the real estate of the final packaged device.

Applied Materials’ Olympia ALD Spins Powerful New Capabilities

Monday, July 13th, 2015


By Ed Korczynski, Sr. Technical Editor

Applied Materials today unveiled the Applied Olympia ALD system, using thermal sequential-ALD technology for the high-volume manufacturing (HVM) of leading-edge 3D memory and logic chips. Strictly speaking this is a mini-batch tool, since four 300mm wafers are loaded onto a turn-table in the chamber that continuously rotates through four gas-isolated modular processing zones. Each zone can be configured to flow any arbitrary ALD precursor or to exposure the surface to Rapid-Thermal-Processing (RTP) illumination, so an extraordinary combination of ALD processes can be run in the tool. “What are the applications that will result from this? We don’t know yet because the world has never before had a tool which could provide these capabilities,” said David Chu, Strategic Marketing, Applied’s Dielectric Systems and Modules group.

Fig.1: The four zones within the Olympia sequential-ALD chamber can be configured to use any combination of precursors or treatments. (Source: Applied Materials)

Figure 1 shows that in addition to a high-throughput simple ALD process such that wafers would rotate through A-B-A-B precursors in sequence, or zones configured in an A-B-C-B sequence to produce a nano-laminate such as Zirconia-Alumina-Zirconia (ZAZ), almost any combination of pre- and post-treatments can be used. The gas-panel and chemical source sub-systems in the tool allow for the use up to 4 precursors. Consequently, Olympia opens the way to depositing the widest spectrum of next-generation atomic-scale conformal films including advanced patterning films, higher- and lower-k dielectrics, low-temperature films, and nano-laminates.

“The Olympia system overcomes fundamental limitations chipmakers are experiencing with conventional ALD technologies, such as reduced chemistry control of single-wafer solutions and long cycle times of furnaces,” Dr. Mukund Srinivasan, vice president and general manager of Applied’s Dielectric Systems and Modules group. “Because of this, we’re seeing strong market response, with Olympia systems installed at multiple customers to support their move to 10nm and beyond.” Future device structures will need more and more conformal ALD, as new materials will have to coat new 3D features.

When engineering even-smaller structures using ALD, thermal budgets inherently decrease to prevent atomic inter-diffusion. Compared to thermal ALD, Plasma-Enhanced ALD (PEALD) functions at reduced temperatures but tend to induce impurities in the film because of excess energy in the chamber. The ability of Olympia to do RTP for each sequentially deposited atomic-layer leads to final film properties that are inherently superior in defectivity levels to PEALD films at the same thermal budget:  alumina, silica, silicon-nitride, titania, and titanium-nitride depositions into high aspect-ratio structures have been shown.

Purging (from the tool) pump-purge

Fab engineers who have to deal with ALD technology—from process to facilities—should be very happy working with Olympia because the precursors flow through the chamber continuously instead of having to use the pump-purge sequences typical of single-wafer and mini-batch ALD tools used for IC fabrication. Pump-purge sequences in ALD tools result in the following wastes:

*   Wasted chemistry since tools generally shunt precursor-A past the chamber directly to the pump-line when precursor-B is flowing and vice-versa,

*   More wasted chemistry because the entire chamber gets coated along with the wafer,

*   Wasted cleaning chemistry during routine chamber and pump preventative-maintenance,

*   Wasted downtime to clean the chamber and pump, and

*   Wasted device yield because precursors flowing in the same space at different times can accidentally overlap and create defects.

“Today there are chemistries that are more or less compatible with tools,” reminded Chu. “When you try to use less-compatible chemistries, the purge times in single-wafer tools really begin to reduce the productivity of the process. There are chemistries out there today that would be desirable to use that are not pursued due to the limitations of pump-purge chambers.”


3DIC Technology Drivers and Roadmaps

Monday, June 22nd, 2015


By Ed Korczynski, Sr. Technical Editor

After 15 years of targeted R&D, through-silicon via (TSV) formation technology has been established for various applications. Figure 1 shows that there are now detailed roadmaps for different types of 3-dimensional (3D) ICs well established in industry—first-order segmentation based on the wiring-level/partitioning—with all of the unit-processes and integration needed for reliable functionality shown. Using block-to-block integration with 5 micron lines at leading international IC foundries such as GlobalFoundries, systems stacking logic and memory such as the Hybrid Memory Cube (HMC) are now in production.

Fig. 1: Today’s 3D technology landscape segmented by wiring-level, showing cross-sections of typical 2-tier circuit stacks, and indicating planned reductions in contact pitches. (Source: imec)

“There are interposers for high-end complex SOC design with good yield,” informed Eric Beyne, Scientific Director Advanced Packaging & Interconnect for imec in an exclusive interview with Solid State Technology. ““For a systems company, once you’ve made the decision to go 3D there’s no way back,” said Beyne. “If you need high-bandwidth memory, for example, then you’re committed to some sort of 3D. The process is happening today.” Beyne is scheduled to talk about 3D technology driven by 3D application requirements in the imec Technology Forum to be held July 13 in San Francisco.

Adaptation of TSV for stacking of components into a complete functional system is key to high-volume demand. Phil Garrou, packaging technologist and SemiMD blogger, reported from the recent ConFab that Hynix is readying a second generation of high-bandwidth memory (HBM 2) for use in high performance computing (HPC) such as graphics, with products already announced like Pascal from Nvidia and Greenland from AMD.

For a normalized 1 cm2 of silicon area, wide-IO memory needs 1600 signal pins (not counting additional power and ground pins) so several thousand TSV are needed for high-performance stacked DRAM today, while in more advanced memory architectures it could go up by another factor of 10. For wide-IO HVM-2 (or Wide-IO2) the silicon consumed by IO circuitry is maybe 6 cm2 today, such that a 3D stack with shorter vertical connections would eliminate many of the drivers on the chip and would allow scaling of the micro-bumps to perhaps save a total of 4 cm2 in silicon area. 3D stacks provide such trade-offs between design and performance, so the best results are predicted for 3DICs where the partitioning can be re-done at the gate or transistor level. For example, a modern 8-core microprocessor could have over 50% of the silicon area consumed by L3-cache-memory and IO circuitry, and moving from 2D to 3D would reduce total wire-lengths and interconnect power consumptions by >50%.

There are inherent thresholds based on the High:Width ratio (H:W) that determine costs and challenges in process integration of TSV:

-    10:1 ratio is the limit for the use of relatively inexpensive physical vapor deposition (PVD) for the Cu barrier/seed (B/S),

-    20:1 ratio is the limit for the use of atomic-layer deposition (ALD) for B/S and electroless deposition (ELD) for Cu fill with 1.5 x 30 micron vias on the roadmap for the far future,

-    30:1 ratio and greater is unproven as manufacturable, though novel deposition technologies continue to be explored.

TSV Processing Results

The researchers at imec have evaluated different ways of connecting TSV to underlying silicon, and have determined that direct connections to micro-bumps are inherently superior to use of any re-distribution layer (RDL) metal. Consequently, there is renewed effort on scaling of micro-bump pitches to be able to match up with TSV. The standard minimum micro-bump pitch today of 40 micron has been shrunk to 20, and imec is now working on 10 micron with plans to go to 5 micron. While it may not help with TSV connections, an RDL layer may still be needed in the final stack and the Cu metal over-burden from TSV filling has been shown by imec to be sufficiently reproducible to be used as the RDL metal. The silicon surface area covered by TSV today is a few percents not 10s of percents, since the wiring level is global or semi-global.

Regarding the trade-offs between die-to-wafer (D2W) and wafer-to-wafer (W2W) stacking, D2W seems advantageous for most near-term solutions because of easier design and superior yield. D2W design is easier because the top die can be arbitrarily smaller silicon, instead of the identically sized chips needed in W2W stacks. Assuming the same defectivity levels in stacking, D2W yield will almost always be superior to W2W because of the ability to use strictly known-good-die. Still, there are high-density integration concepts out on the horizon that call for W2W stacking. Monolithic 3D (M3D) integration using re-grown active silicon instead of TSV may still be used in the future, but design and yield issues will be at least comparable to those of W2W stacking.

Beyne mentioned that during the recent ECTC 2015, EV Group showed impressive 250nm overlay accuracy on 450mm wafers, proving that W2W alignment at the next wafer size will be sufficient for 3D stacking. Beyne is also excited by the fact the at this year’s ECTC there was, “strong interest in thermo-compression bonding, with 18 papers from leading companies. It’s something that we’ve been working on for many years for die-to-wafer stacking, while people had mistakenly thought that it might be too slow or too expensive.”

Thermal issues for high-performance circuitry remain a potential issue for 3D stacking, particularly when working with finFETs. In 2D transistors the excellent thermal conductivity of the underlying silicon crystal acts like a built-in heat-sink to diffuse heat away from active regions. However, when 3D finFETs protrude from the silicon surface the main path for thermal dissipation is through the metal lines of the local interconnect stack, and so finFETs in general and stacks of finFETs in particular tend to induce more electro-migration (EM) failures in copper interconnects compared to 2D devices built on bulk silicon.

3D Designs and Cost Modeling

At a recent North California Chapter of the American Vacuum Society (NCCAVS) PAG-CMPUG-TFUG Joint Users Group Meeting discussing 3D chip technology held at Semi Global Headquarters in San Jose, Jun-Ho Choy of Mentor Graphics Corp. presented on “Electromigration Simulation Flow For Chip-Scale Parametric Failure Analysis.” Figure 2 shows the results from use of a physics-based model for temperature- and residual-stress-aware void nucleation and growth. Mentor has identified new failure mechanisms in TSV that are based on coefficient of thermal expansion (CTE) mismatch stresses. Large stresses can develop in lines near TSV during subsequent thermal processing, and the stress levels are layout dependent. In the worst cases the combined total stress can exceed the critical level required for void nucleation before any electrical stressing is applied. During electrical stress, EM voids were observed to initially nucleate under the TSV centers at the landing-pad interfaces even though these are the locations of minimal current-crowding, which requires proper modeling of CTE-mismatch induced stresses to explain.

Fig. 2: Calibration of an Electronic Design Automation (EDA) tool allows for accurate prediction of transistor performance depending on distance from a TSV. (Source: Mentor Graphics)

Planned for July 16, 2015 at SEMICON West in San Francisco, a presentation on “3DIC Technology Past, Present and Future” will be part of one of the side Semiconductor Technology Sessions (STS). Ramakanth Alapati, Director of Packaging Strategy and Marketing, GLOBALFOUNDRIES, will discuss the underlying economic, supply chain and technology factors that will drive productization of 3DIC technology as we know it today. Key to understanding the dynamic of technology adaptation is using performance/$ as a metric.

Solid State Watch: June 5-11, 2015

Thursday, June 11th, 2015
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Silicon Technology Extensions shown at MRS Spring 2015

Monday, June 1st, 2015

By Ed Korczynski, Sr. Technical Editor, Solid State Technology/SemiMD

In the spring meeting of the Materials Research Society held recently in San Francisco, Symposium A: Emerging Silicon Science and Technology included presentations on controlling the structure of crystalline spheres and thin-films. Such structures could be used in future complementary metal-oxide semiconductor (CMOS) devices and in photonic circuits built using silicon.

Alexander Gumennik, et al., from the Massachusetts Institute of Technology, presented on “Extraordinary Stress in Silicon Spheres via Anomalous In-Fiber Expansion” as a way to control the bandgap of silicon and thus enable the use of silicon for photodetection at higher wavelengths. A silica fiber with a crystalline silicon core is fed through a flame yielding spherical silicon droplets via capillary instabilities. Upon cooling the spheres solidify and expand against the stiff silica cladding generating high stress conditions. Band gap shifts of 0.05 eV to the red (in Si) are observed, corresponding to internal stress levels. These stress levels exceed the surface stress as measured through birefringence measurements by an order of magnitude, thus hinting at a pressure-focusing mechanism. The effects of the solidification kinetics on the stress levels reached inside the spheres were explored, and the experimental results were found to be in agreement with a pressure-focusing mechanism arising from radial solidification of the spheres from the outer shell to the center. The simplicity of this approach presents compelling opportunities for the achievement of unusual phases and chemical reactions that would occur under high-pressure high-temperature conditions, which therefore opens up a pathway towards the realization of new in-fiber optoelectronic devices.

Fabio  Carta and others from Columbia University working with researchers from IBM showed results on “Excimer Laser Crystallization of Silicon Thin Films on Low-K Dielectrics for Monolithic 3D Integration.” This research supports the “Monolithic 3D” (M3D) approach to 3D CMOS integration as popularized by CEA-LETI, as opposed to the used of Through Silicon Vias (TSV). M3D requires processing temperature below 400°C if copper interconnects and low-k dielectric will be used in the bottom layer. Excimer laser crystallization (ELC) takes advantage of a short laser pulse to fully melt the amorphous silicon layer without allowing excessive time for the heat to spread throughout the structure, achieving large grain polycrystalline layer on top of temperature sensitive substrates. The team crystallized 100nm thick amorphous silicon layers on top of SiO2 and SiCOH (low-k) dielectrics. SEM micrographs show that post-ELC polycrystalline silicon is characterized by micron-long grains with an average width of 543 nm for the SiO2 sample and 570 nm for the low-k samples. A 1D simulation of the crystallization process on a back end of line structure shows that interconnect lines experience a maximum temperature lower than 70°C for the 0.5 μm dielectric, which makes ELC on low-k a viable pathway for achieving monolithic integration.

Seiji  Morisaki, et al., from Hiroshima Univ, showed results for “Micro-Thermal-Plasma-Jet Crystallization of Amorphous Silicon Strips and High-Speed Operation of CMOS Circuit.” The researchers used micro-thermal-plasma-jet (µ-TPJ) for zone melting recrystallization (ZMR) of amorphous silicon (a-Si) films to form lateral grains larger than 60 µm. By applying ZMR on a-Si strip patterns with widths <3 µm, single liquid-solid interfaces move inside the strips and formation of random grain boundaries (GBs) are significantly suppressed. Applying such strip patterns to active channels of thin-film-transistors (TFTs) results in a demonstrated field effect mobility (µFE) higher than 300 cm2/V*s because they contain minimal grain-boundaries. These a-Si strip pattern were then used to characteristic variability of n- and p-channel TFTs and CMOS ring oscillators. The strip patterns showed improved uniformities and defect densities, in general. A 9-stage ring oscillator fabricated with conventional TFTs had a maximum frequency (Fmax) of operation of 58 MHz under supply voltage (Vdd) of 5V which corresponds to a 1-stage delay (τ) of 0.94 ns, while strip channel TFTs demonstrated 108 MHz Fmax and τ decreased to 0.52 ns.

Ebrahim  Najafi, et al., from the California Institute of Technology, showed how “Ultrafast Imaging of Carrier Dynamics at the p-n Junction Interface” based on scanning ultrafast electron microscopy (SUEM) combines the spatial resolution of an electron probe with the temporal resolution of an optical pulse to enable unprecedented studies of carrier dynamics in spatially complex geometries. Observing the behavior of carriers in both space and time provides direct imaging of carrier excitation, transport, and recombination in the silicon p-n junction and the ability to follow their spatiotemporal behavior. Carrier separation on the surface of the p-n junction extends tens of microns beyond the depletion layer, as explained by a model using a ballistic-type transport. With the invention of SUEM, it should now be possible to study density profiles and electric potentials at surfaces and interfaces at the ultrafast time scale with the spatial resolution of the electron probe.

As a reminder, the Call For Paper for the MRS Fall 2015 meeting closes on June 18.


Solid State Watch: March 6-12, 2015

Friday, March 13th, 2015
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MicroWatt Chips shown at ISSCC

Thursday, March 5th, 2015


By Ed Korczynski, Sr. Technical Editor

With much of future demand for silicon ICs forecasted to be for mobile devices that must conserve battery power, it was natural for much of the focus at the just concluded 2015 International Solid State Circuits Conference (ISSCC) in San Francisco to be on ultra-low-power circuits that run on mere microWatts (µW). From analog to digital logic to radio-frequency (RF) chips and extending to complete system-on-chip (SoC) prototypes, silicon IC functionality is being designed with evolutionary and even revolutionary reductions in the operational power needed.

The figure shows a multi-standard 2.4 GHz radio that was co-developed by imec, Holst Centre, and Renesas using a 40nm node CMOS process. This was detailed in session 13.2 when Y.H. Liu presented “A 3.7mW-RX 4.4mW-TX Fully Integrated Bluetooth Low-Energy/IEEE802.15.4/Proprietary SoC with an ADPLL-Based Fast Frequency Offset Compensation in 40nm CMOS.” It uses a digital-intensive RF architecture tightly integrated with the digital baseband (DBB) and a microcontroller (MCU), and the digital-intensive RF design reduces the analog core area to 1.3mm2, and the DBB/MCU/SRAM occupies an area of 1.1mm2. This is an evolution of a previous 90nm RF front-end design that results in a reduced supply voltage (20 percent), power consumption (25 percent), and chip area (35 percent).

Ultra-low-power multi-standard 2.4 GHz radio compliant with Bluetooth Low Energy and ZigBee, co-developed by imec, Holst Centre, and Renesas. (Source: Renesas)

“From healthcare to smart buildings, ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life,” said Harmke De Groot, Department Director at imec. “The radio consumes the majority of the power of the total system and is one of the most critical components to enable these emerging applications. Moreover, a low-cost area-efficient radio design is an important catalyst for developing small sensor applications, seamlessly integrated into the environment. Implementing an ultra-low power radio will increase the autonomy of the sensor device, increase its quality, functionality and performance and enable the reduction of the battery size, resulting in a smaller device, which in case of wearable systems, adds to user’s comfort.”

When most ICs were used in devices and systems that were powered by line current there was no advantage to minimizing power consumption, and so digital CMOS circuits could be designed with billions of transistors switching billions of times each second resulting in sufficient brute-force power to solve most problems. With power-consumption now a vital aspect of much of the demand for future chips, this year’s ISSCC offered the following tutorials on low-power chips:

  • “Ultra Low Power Wireless Systems” by Alison Burdett of Toumaz Group (UK),
  • “Low Power Near-threshold Design” by Dennis Sylvester of University of Michigan, and
  • “Analog Techniques for Low-Power Circuits” by Vadim Ivanov of Texas Instruments.

Then on Thursday the 26th, an entire short course was offered on “Circuit Design in Advanced CMOS Technologies:  How to Design with Lower Supply Voltages.” with lectures on the following:

  • “A Roadmap to Lower Supply Voltages – A System Perspective” by Jan M. Rabaey of UC Berkeley,
  • “Designing Ultra-Low-Voltage Analog and Mixed-Signal Circuits” by Peter Kinget of Columbia University,
  • “ACD Design in Scaled technologies” by Andrea Baschirotto of University of Milan-Bicocca, and
  • “Ultra-Low-Voltage RF Circuits and Transceivers” by Hyunchoi Shin of Kwangwoon University.

µW SoC Blocks

Session 5.10 covered “A 4.7MHz 53µW Fully Differential CMOS Reference Clock Oscillator with -22dB Worst-Case PSNR for Miniaturized SoCs” by J. Lee et al. of the Institute of Microelectronics (Singapore) along with researchers from KAIST and Daegu Gyeongbuk Institute of Science and Technology in Korea. While many SoCs for the IoT are intended for machine-to-machine networks, human interaction will still be needed for many applications so session 6.7 covered “A 2.3mW 11cm-Range Bootstrapped and Correlated-Double-Sampling (BCDS) 3D Touch Sensor for Mobile Devices” by L. Du et. al. from UCLA (California).

As indicated by the low MHz speed of the clock circuit referenced above, the only way that these ICs can consume 1/1000th of the power of mainstream chips is to operate at 1/1000th the speed. Also note that most of these chips will be made using 90nm- and 65nm-node fab processes, instead of today’s leading 22nm- and 14nm-node processes, as evidenced by session 8.3 covered “A 10.6µA/MHz at 16MHz Single-Cycle Non-Volatile Memory-Access Microcontroller with Full State Retention at 108nA in a 90nm Process” by V.K. Singhal et al. from the Kilby Labs of Texas Instruments (Bangalore, India). Session 18.3 covered “A 0.5V 54µW Ultra-Low-Power Recognition Processor with 93.5% Accuracy Geometric Vocabulary Tree and 47.5 Database Compression” by Y. Kim et al. of KAIST (Daejeon, Korea).

In the Low Power Digital sessions it was natural that ARM Cortex chips were the basis for two different presentations on ultra-low power functionality, since ARM cores power most of the world’s mobile processors, and since the RISC architecture of ARM was deliberately evolved for mobile applications. Session 8.1 covered “An 80nW Retention 11.7pJ/Cycle Active Subthreshold ARM Cortex-M0+ Subsystem in 65nm CMOS for WSN Applications” by J. Myers et al. of ARM (Cambridge, UK). In the immediately succeeding session 8.2, W. Lim et al. of the University of Michigan (Ann Arbor) presented on the possibilities for “Batteryless Sub-nW Cortex-M0+ Processor with Dynamic Leakage-Suppression Logic.”

nW Beyond Batteries

Session 5.4 covered “A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-Low Power Systems” by A. Shrivastava et al. of PsiKick (Charlottesville, VA). PsiKick’s silicon-proven ultra-low-power wireless sensing devices are based on over 10 years of development of Sub-Threshold (Sub-Vt) devices. They are claimed to operate at 1/100th to 1/1000th of the power budget of other low-power IC sensor platforms, allowing them to be powered without a battery from a variety of harvested energy sources. These SoCs include full sensor analog front-ends, programmable processing and memory, integrated power management, programmable hardware accelerators, and full RF (wireless) communication capabilities across multiple frequencies, all of which can be built with standard CMOS processes using standard EDA tools.

Extremely efficient energy harvesting was also shown by S. Stanzione et al. of Holst Centre/ imec/KU Leuven working with OMRON (Kizugawa, Japan) in session 20.8 “A 500nW Battery-less Integrated Electrostatic Energy Harvester Interface Based on a DC-DC Converter with 60V Maximum Input Voltage and Operating From 1μW Available Power, Including MPPT and Cold Start.” Such energy harvesting chips will power ubiquitous “smarts” embedded into the literal fabric of our lives. Smart clothes, smart cars, and smart houses will all augment our lives in the near future.


Solid State Watch: January 16-22, 2015

Thursday, January 22nd, 2015
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