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Applied Materials Releases Selective Etch Tool

Wednesday, June 29th, 2016


By Ed Korczynski, Sr. Technical Editor

Applied Materials has disclosed commercial availability of new Selectra(TM) selective etch twin-chamber hardware for the company’s high-volume manufacturing (HVM) Producer® platform. Using standard fluorine and chlorine gases already used in traditional Reactive Ion Etch (RIE) chambers, this new tool provides atomic-level precision in the selective removal of materials in 3D devices structures increasingly used for the most advanced silicon ICs. The tool is already in use at three customer fabs for finFET logic HVM, and at two memory fab customers, with a total of >350 chambers planned to have been shipped to many customers by the end of 2016.

Figure 1 shows a simplified cross-sectional schematic of the Selectra chamber, where the dashed white line indicates some manner of screening functionality so that “Ions are blocked, chemistry passes through” according to the company. In an exclusive interview with Solid State Technology, company representative refused to disclose any hardware details. “We are using typical chemistries that are used in the industry,” explained Ajay Bhatnagar, managing director of Selective Removal Products for Applied Materials. “If there are specific new applications needed than we can use new chemistry. We have a lot of IP on how we filter ions and how we allow radicals to combine on the wafer to create selectivity.”

FIG 1: Simplified cross-sectional schematic of a silicon wafer being etched by the neutral radicals downstream of the plasma in the Selectra chamber. (Source: Applied Materials)

From first principles we can assume that the ion filtering is accomplished with some manner of electrically-grounded metal screen. This etch technology accomplishes similar process results to Atomic Layer Etch (ALE) systems sold by Lam, while avoiding the need for specialized self-limiting chemistries and the accompanying chamber throughput reductions associated with pulse-purge process recipes.

“What we are doing is being able to control the amount of radicals coming to the wafer surface and controlling the removal rates very uniformly across the wafer surface,” asserted Bhatnagar. “If you have this level of atomic control then you don’t need the self-limiting capability. Most of our customers are controlling process with time, so we don’t need to use self-limiting chemistry.” Applied Materials claims that this allows the Selectra tool to have higher relative productivity compared to an ALE tool.

Due to the intrinsic 2D resolutions limits of optical lithography, leading IC fabs now use multi-patterning (MP) litho flows where sacrificial thin-films must be removed to create the final desired layout. Due to litho limits and CMOS device scaling limits, 2D logic transistors are being replaced by 3D finFETs and eventually Gate-All-Around (GAA) horizontal nanowires (NW). Due to dielectric leakage at the atomic scale, 2D NAND memory is being replaced by 3D-NAND stacks. All of these advanced IC fab processes require the removal of atomic-scale materials with extreme selectivity to remaining materials, so the Selectra chamber is expected to be a future work-horse for the industry.

When the industry moves to GAA-NW transistors, alternating layers of Si and SiGe will be grown on the wafer surface, 2D patterned into fins, and then the sacrificial SiGe must be selectively etched to form 3D arrays of NW. Figure 2 shows the SiGe etched from alternating Si/SiGe stacks using a Selectra tool, with sharp Si corners after etch indicating excellent selectivity.

FIG 2: SEM cross-section showing excellent etch of SiGe within alternating Si/SiGe layers, as will be needed for Gate-All-Around (GAA) horizontal NanoWire (NW) transistor formation. (Source: Applied Materials)

“One of the fundamental differences between this system and old downstream plasma ashers, is that it was designed to provide extreme selectivity to different materials,” said Matt Cogorno, global product manager of Selective Removal Products for Applied Materials. “With this system we can provide silicon to titanium-nitride selectivity at 5000:1, or silicon to silicon-nitride selectivity at 2000:1. This is accomplished with the unique hardware architecture in the chamber combined with how we mix the chemistries. Also, there is no polymer formation in the etch process, so after etching there are no additional processing issues with the need for ashing and/or a wet-etch step to remove polymers.”

Systems can also be used to provide dry cleaning and surface-preparation due to the extreme selectivity and damage-free material removal.  “You can control the removal rates,” explained Cogorno. “You don’t have ions on the wafer, but you can modulate the number of radicals coming down.” For HVM of ICs with atomic-scale device structures, this new tool can widen process windows and reduce costs compared to both dry RIE and wet etching.


Technologies for Advanced Systems Shown at IMEC Tech Forum USA

Tuesday, July 14th, 2015


By Ed Korczynski, Sr. Technical Editor

Luc Van den hove, president and CEO, imec opened the Imec Technology Forum – USA in San Francisco on July 13 by reminding us of the grand vision and motivation behind the work of our industry to empower individuals with micro- and nano-technologies in his talk, “From the happy few to the happy many.” While the imec consortium continues to lead the world in pure materials engineering and device exploration, they now work on systems-integration complexities with over 100 applications partners from agriculture, energy, healthcare, and transportation industries.

We are now living in an era where new chip technologies require trade-offs between power, performance, and bandwidth, and such trade-offs must be carefully explored for different applications spaces such as cloud clusters or sensor nodes. An Steegen, senior vice president process technology, imec, discussed the details of new CMOS chip extensions as well as post-CMOS device possibilities for different applications spaces in her presentation on “Technology innovation: an IoT era.” EUV lithography technology continues to be developed, targeting a single-exposure using 0.33 Numerical Aperture (NA) reflective lenses to pattern features as small as 18nm half-pitch, which would meet the Metal1 density specifications for the industry’s so-called “7nm node.” Patterning below 12nm half-pitch would seem to need higher-NA which is not an automatic extension of current EUV technology.

So while there is now some clarity regarding the pre-competitive process-technologies that will be needed to fabricate next-generation device, there is less clarity regarding which new device structures will best serve the needs of different electronics applications. CMOS finFETs using strained silicon-doped-with-Germanium Si(Ge) will eventually be replaced by gate-all-around (GAA) nano-wires (NW) using alternate-channel materials (ACM) with higher mobilities such as Ge and indium-gallium-arsenide (InGaAs). While many measures of CMOS performance improve with scaling to smaller dimensions, eventually leakage current and parasitic capacitances will impede further progress.

Figure 1 shows a summary of energy-vs.-delay analyses by imec for all manner of devices which could be used as switches in logic arrays. Spin-wave devices such as spin-transfer-torque RAM (STT-RAM) can run at low power consumption but are inherently slower than CMOS devices. Tunnel-FET (TFET) devices can be as fast or faster than CMOS while running at lower operating power due to reduced electrostatics, leading to promising R&D work.

Fig.1: Energy vs. delay for various logic switches. (Source: imec)

In an exclusive interview, Steegen explained how the consortium balances the needs of all partners in R&D, “When you try to predict future roadmaps you prefer to start from the mainstream. Trying to find the mainstream, so that customers can build derivatives from that, is what imec does. We’re getting closer to systems, and systems are reaching down to technology,” said Steegen. “We reach out to each other, while we continue to be experts in our own domains. If I’m inserting future memory into servers, the system architecture needs to change so we need to talk to the systems people. It’s a natural trend that has evolved.”

Network effects from “the cloud” and from future smart IoT nets require high-bandwidth and so improved electrical and optical connections at multiple levels are being explored at imec. Joris Van Campenhout, program director optical I/O, imec, discussed “Scaling the cloud using silicon photonics.” The challenge is how to build a 100Gb/s bandwidth in the near term, and then scale to 400G and then 1.6T though parallelism of wavelength division multiplexing; the best results to date for a transmitter and receiver reach 50Gb/s. By leveraging the existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon photonics platform enables high integration density and reduced power consumption, as well as high yield and low manufacturing cost. Supported by EDA tools including those from Mentor Graphics, there have been 7 tape-outs of devices in the last year using a Process Design Kit (PDK). When combined with laser sources and a 40nm node foundry CMOS chip, a complete integrated solution exists. Arrays of 50Gb/s structures can allow for 400Gb/s solutions by next year, and optical backplanes for server farms in another few years. However, to bring photonics closer to the chip in an optical interposer will require radical new new approaches to reduce costs, including integration of more efficient laser arrays.

Alexander Mityashin, project manager thin film electronics, imec, explained why we need, “thin film electronics for smart applications.” There are billions of items in our world that could be made smarter with electronics, provided we can use additive thin-film processes to make ultra-low-cost thin-film transistors (TFT) that fit different market demands. Using amorphous indium-gallium-zinc-oxide (a-IGZO) deposited at low-temperature as the active layer on a plastic substrate, imec has been able to produce >10k TFTs/cm2 using just 4-5 lithography masks. Figure 2 shows these TFT integrated into a near-field communications (NFC) chip as first disclosed at ISSCC earlier this year in the paper, “IGZO thin-film transistor based flexible NFC tags powered by commercial USB reader device at 13.56MHz.” Working with Panasonic in 2013, imec showed a flexible organic light-emitting diode (OLED) display of just 0.15mm thickness that can be processed at 180°C. In collaboration with the Holst Center, they have worked on disposable flexible sensors that can adhere to human skin.

Fig.2: Thin-Film Transistors (TFT) fabricated on plastic using Flat Panel Display (FPD) manufacturing tools. (Source: imec/Holst Center)

Jim O’Neill, Chief Technology Officer of Entegris, expanded on the systems-level theme of the forum in his presentation on “Putting the pieces together – Materials innovation in a disruptive environment.” With so many additional materials being integrated into new device structures, there are inherently new yield-limiting defect mechanisms that will have to be controlled. With demand for chips now being driven primarily by high-volume consumer applications, the time between first commercial sample and HVM has compressed such that greater coordination is needed between device, equipment, and materials companies. For example, instead of developing a wet chemical formulation on a tool and then optimizing it with the right filter or dispense technology, the Process Engineer can start envisioning a “bottle-to-nozzle wetted surface solution.” By considering not just the intended reactions on the wafer but the unintended reactions that can occur up-steam and down-stream of the process chamber, full solutions to the semiconductor industry’s most challenging yield problems can be more quickly found.


5nm Node Needs EUV for Economics

Thursday, January 29th, 2015


By Ed Korczynski, Sr. Technical Editor


At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.

Fig. 1: Panelists discuss future IC manufacturing and design possibilities in San Francisco on December 16, 2014. (Source: Pete Singer)

Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:

  • Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
  • Michael Guillorn, Ph.D. – research staff member, IBM,
  • Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
  • Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
  • Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.

Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.

Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.

Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm:  gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.

Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.

Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:

  1. everything is an interface requiring precision materials engineering,
  2. film depositions are either atomic-layer or selective films or even lattice-matched,
  3. pattern definition using dry selective-removal and directed self-assembly, and
  4. architecture in 3D means high aspect-ratio processing and non-equilibrium processing.

An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.

Fig. 2: ElectroMigration (EM) lifetimes for on-chip interconnects made with either conventional Cu or Cu lined and capped with Co, showing 10 times improvement with the latter. (Source: Applied Materials)

“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.

There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.

However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”

Experts at the Table: Focus on Semiconductor Materials

Monday, November 3rd, 2014

By Jeff Dorsch

The cutting edge in semiconductor manufacturing has meant not only big changes in IC design and process technology, but also in semiconductor materials. What follows are responses from Linde Electronics; Kate Wilson of Edwards Vacuum; David Thompson, Technology Director, Process Chemistries, Silicon Systems Group, Applied Materials; and Ed Shober, General Manager, Advanced Materials, Air Products and Chemicals.

1. What changes are being made in materials in fabrication of FinFETs, gate-all-around transistors, vertical NAND and fully-depleted silicon-on-insulator processes? Are there other new developments and trends in semiconductor materials (in interconnects, for example)?

Kate Wilson: We are seeing an increase in MOCVD precursors, low-temperature precursors and switching of process gases for ALD and multilayer films.

Linde Electronics: These devices will be implemented at aggressive nodes, e.g., 14/16 nm and below. Due to the unavailability of EUV lithography in HVM for at least the next 2—3 years, chip makers are forced to use multiple patterning techniques, which have led to several additional deposition and etch steps being incorporated relative to previous generations.

Of the devices mentioned, FinFETs and vertical NAND are becoming or will soon become mainstream in leading-edge logic and NAND fabs. Given that key parts of the device structures are approaching dimensions that are tens of atoms across, the tolerance for variability in the manufacturing process is significantly reduced, which in turn imposes special demands on materials suppliers to control variation in the quality of the electronic materials (EM) products supplied to a fab. This requires additional metrology and quality control techniques to be used across the EM supply chain, from incoming raw material to in-process material to finished product.

In addition, these advanced devices are more sensitive to any unspecified species in the EM products, and it is crucial to measure trace levels of unspecified impurities and understand their potential interactions with the thin films and interfaces involved in these devices. Collaboration across all the supply chain participants is thus key. Looking ahead, novel channel materials such as germanium and III-V compound semiconductors will be required, which bring their own set of challenges in deposition and etch.

David Thompson: For all these architectures the big trends are the introduction of new materials to enable scaling and the increasing criticality of interfacial materials. Consistently meeting new material innovation and interface engineering requirements is what we call precision materials engineering. Numerous new materials are being used today to enable low-power, high-performance foundry/logic devices. Selective epitaxy and metal gate films deliver >2 nodes of performance scaling with no litho-scaling. The introduction of CVD Cobalt liner and selective Cobalt cap layers in interconnect improves device reliability by 80x by completely encapsulating interconnect with Cobalt. More potential new materials are being evaluated at 10nm and beyond in transistors and interconnect. In 3D NAND, SiN film is used to store electrons using charge trap storage technology, compared to planar NAND where polycrystalline Si film is used using floating-gate MOSFET technology.

Interface engineering is also becoming increasingly critical. Whether it’s the transistor metal films, the interconnect cladding, or 3D NAND, there are essential enabling films that require sub-angstrom uniformity control across the wafer that have thicknesses between 10 and 40 angstroms – that’s less than the diameter of an atom. Additionally, while the bulk properties of materials are a useful roadmap, developing an understanding of how barrier, electrical, and other properties are impacted when the material is so thin that it doesn’t exhibit bulk properties is the challenge of the day. In many cases, a very particular pretreatment is required to enable the specific material interface to tune these properties. We’re finding that increasingly these steps need to be carried out sequentially within a vacuum environment with no air breaks.

Ed Shober: For logic devices and the adoption of 3D transistors, such as FinFETs, there are many needs for new chemical precursors to deposit — for example, silicon nitride and silicon oxide at temperatures far lower than previously required. In earlier nodes the thermal budget was in the 450 to 600C range, now the budget has been reduced to the 250 to 400C range, and the expectation is that it will go lower in the future. The shallow dopant profiles around the fin structure is one of the reasons for this drive to lower temperatures. Atomic layer deposition (ALD) is playing a greater role in depositing films. Thus, the chemistries employed must adsorb and react on the surface quickly and allow for deposition of highly conformal films over high aspect ratio features. More metal precursors are being employed in the FEOL for logic in order to tune the work function of the transistors. In the BEOL the biggest metal change has been the adoption of cobalt as a copper capping film and as a barrier liner film.

Needs for CMP are also increasing with 3D transistor structures. There are at least three new CMP steps that need to be performed to fabricate the fin. Finally, cleaning continues to play a major role in preparing the structures for the next deposition step.

Vertical NAND is moving memory off the lithography road map and onto a track that is driven by number of SiO/SiN films in a stack. The material needs here are again ALD-based precursors for lining and filling the channels etches into these film stacks. A major driver in cleans is products that limit particles left on the wafer and the scale of these particles must be in the nm size range.

For all devices, but especially DRAM and logic, the delays in adopting EUV are driving the need for self-aligned double, triple and quadruple patterning. These patterning strategies require new materials for forming the structures needed to reduce the pattern dimensions.
2. What changes are necessary in pumps and abatement?

Wilson: Increased variety of precursors requires flexible product operating range and tailored set-ups by process. Collaboration with semiconductor tool manufacturers, collaborative research organizations and end-customer development facilities is becoming more critical to ensure best known methods are applied.

Shober: Compatibility with the chemical precursors which can be highly reactive is one necessary requirement. Particle generation by the components is also a major concern and must be addressed by the suppliers to the same scales as discussed in the above answer around semi materials.

3.  What are the risks involved with certain materials? Can they be disposed of safely? What about EPA regulation of these materials?

Wilson: Metal byproducts can be very toxic and containment of them can be challenging. Special care needs to be applied to their capture and disposal.  Many of the new precursors are flammable and pyrophoric as well as being highly toxic so abatement is essential. Safe handling of new flammable or pyrophoric deposition precursors puts additional challenges on the process equipment and its maintenance – leaks of material out of, and air leaks into, process equipment can have serious consequences and therefore have to be diligently avoided to prevent accidents. It’s essential that sub-fab equipment designed to support advanced CVD processes should be designed from the outset with safe operation and servicing in mind. Better yet, an integrated sub-fab system design and a single point of ownership for the whole sub-fab system provide some assurance that the system can be operated with the minimum risk of accidents due to inadequate maintenance. Advanced integrated dry-pump/exhaust system/abatement/thermal management systems are available from at least one reputable equipment supplier to support such advanced processes, and have been widely adopted by several top-tier device manufacturers to provide exactly such assurance of maximized risk reduction in their advanced CVD processes.

Shober: With the drive to lower thermal budget there is a trend to using chemical precursors that are more reactive and stable. Thus, how they are produced, packaged, shipped and used by the customers are risks that we must address as new products are introduced. Shipping is especially a concern because there are more limitations on what materials can be flown from one point to another. This is driving for more localization of production/purification to shorten supply chains. BCP is of course another concern. Customers are looking for multiple and secure supply of materials.

4. How can semi materials be made “greener”?

Wilson: Once upon a time there was a concerted effort by a number of companies to find greener alternatives to persistent PFC gases used in etching processes to address the “green problem” at source – in general they weren’t very successful and attention switched to abating the PFCs effectively instead. In the current environment, where increasingly exotic CVD precursors are being introduced into advanced device node manufacturing, it’s also likely that “greenness” will be more a result of diligent treatment of the waste precursors, their decomposition products and the solid residues left behind in the process equipment than efforts to make the materials themselves “green.” That puts the onus on abatement and waste treatment system manufacturers to develop suitable products to meet the emerging challenges, and the end-user community to accept responsibility for installing suitable waste treatment facilities.

In some instances, careful consideration has to be given to the balance between risk of gas release and cost to the environment of treating it – abatement of nitrous oxide (N2O) being a case in point. N2O is a greenhouse gas widely used in oxide CVD processes, and device manufacturers would prefer to abate it to reduce their GHG emissions. However, combustion of N2O consumes natural gas, generates carbon dioxide (CO2) and under adverse conditions can generate significant quantities of nitrogen oxides (NOx); so the question arises – which is the least bad situation?

Linde Electronics: Materials suppliers can contribute to greening of semi materials by:

  • Limiting emissions and waste over product life cycle

This includes material production, delivery and return/reclamation/disposal.

  • Substituting

Sometimes, despite the material selection constraints, direct, process-compatible substitutions can be made such as F2 (fluorine). See reference to this in the article “Material Support: Helping Displays Deliver Higher Performance” in the September, 2012 issue of Solid State Technology.

  • Packaging and processing for efficient use

Often headspaces are exhausted and heels are unused to prevent light and heavy contaminants. Better purification, quality control, packaging, and material property knowledge can reduce the amount of material lost to safeguarding quality.

  • Recovering material from waste streams

Examples of this are He (Helium), Ar (Argon), Xe (Xenon), H2SO4 (Sulphuric Acid). See reference to this in the blog post “Sustainability through Materials Recovery” at

Thompson: In many respects, semi materials are the greenest materials known and need to be taken in the context of not just as the materials in the chip but in what they end up consuming, for instance, power. A good example is the UNIVAC that ran at 1,905 floating point operations-per-second on 125 kW, while processors like today’s Tegra K1 run at 326 GFLOPS on 10 W – which uses a number of different materials that in effect reduce the power required per floating point operation by a factor of 1 trillion. Net reduced environmental impact will almost always favor choices that continue the power scaling trajectory. That being said, we need to be vigilant in managing the dangers and impact of some of the more hazardous materials that are being used which provide this net green benefit.

Shober: The industry made a major step to become greener when NF3 was adopted rather than fluorocarbons for cleaning CVD reactors. Solvent recovery and re-purposing for other use in either the fab or other industries is now being adopted. More and more cleaning processes are employing water-based formulations which reduces solvent usage at the fab. In the future IDMs will be looking for more ways to recapture and purify, recycle and/or re-purpose wastes into other uses at the site or outside into other industries.

5.  How are advanced processes, such as atomic-level deposition, affecting materials use?

Wilson: Diverting precursor and low utilization rates in the process cause higher unreacted material and waste.

Linde Electronics: Both atomic layer deposition (ALD) and atomic layer etch (ALEt) are key new processes required in leading-edge device manufacture because of the new elements being incorporated and the aggressive geometries being adopted to keep Moore’s Law on track. Several new EM products are now used in ALD, e.g. organometallic molecules. For ALEt, quite a few traditionally used EM products (e.g. chlorinated gases) are currently being evaluated. The selection of process materials becomes very challenging when multiple films are in close proximity, e.g. requiring high selectivity for etching one thin film without affecting two or more nearby materials.

Thompson: What we find is that the deposition technique or specific chemistries employed strongly impact material properties. There are almost no situations where when we migrate from one technology to another – say PVD to ALD – where we don’t see significant change in materials properties associated with the technique.

Additionally, in many cases the materials that the industry is accustomed to using are no longer available for a new technique. Usually, there’s a ripple effect on retuning other materials or processes to enable the new material. It’s an exciting time – there’s a renaissance of metallurgy in both the front end and back end.

Shober: ALD does have a tendency to reduce material consumption, but not to the degree one may expect as a result of the process itself. The biggest impact ALD is having is on chemical costs. Materials capable of being deposited by ALD are oftentimes novel and there only use is within the semi industry. Thus, the cost on a gram basis can be much higher than what the industry has come to expect from use of materials like TEOS.

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