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Air-Gaps for FinFETs Shown at IEDM

Friday, October 28th, 2016

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By Ed Korczynski, Sr. Technical Editor

Researchers from IBM and Globalfoundries will report on the first use of “air-gaps” as part of the dielectric insulation around active gates of “10nm-node” finFETs at the upcoming International Electron Devices Meeting (IEDM) of the IEEE (ieee-iedm.org). Happening in San Francisco in early December, IEDM 2016 will again provide a forum for the world’s leading R&D teams to show off their latest-greatest devices, including 7nm-node finFETs by IBM/Globalfoundries/Samsung and by TSMC. Air-gaps reduce the dielectric capacitance that slows down ICs, so their integration into transistor structures leads to faster logic chips.

History of Airgaps – ILD and IPD

As this editor recently covered at SemiMD, in 1998, Ben Shieh—then a researcher at Stanford University and now a foundry interface for Apple Corp.—first published (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) on the use of controlled pitch design combined with CVD dielectrics to form “pinched-off keyholes” in cross-sections of inter-layer dielectrics (ILD).

In 2007, IBM researchers showed a way to use sacrificial dielectric layers as part of a subtractive process that allows air-gaps to be integrated into any existing dielectric structure. In an interview with this editor at that time, IBM Fellow Dan Edelstein explained, “we use lithography to etch a narrow channel down so it will cap off, then deliberated damage the dielectric and etch so it looks like a balloon. We get a big gap with a drop in capacitance and then a small slot that gets pinched off.

Intel presented on their integration of air-gaps into on-chip interconnects at IITC in 2010 but delayed use until the company’s 14nm-node reached production in 2014. 2D-NAND fabs have been using air-gaps as part of the inter-poly dielectric (IPD) for many years, so there is precedent for integration near the gate-stack.

Airgaps for finFETs

Now researchers from IBM and Globalfoundries will report in (IEDM Paper #17.1, “Air Spacer for 10nm FinFET CMOS and Beyond,” K. Cheng et al) on the first air-gaps used at the transistor level in logic. Figure 1 shows that for these “10nm-node” finFETs the dielectric spacing—including the air-gap and both sides of the dielectric liner—is about 10 nm. The liner needs to be ~2nm thin so that ~1nm of ultra-low-k sacrificial dielectric remains on either side of the ~5nm air-gap.

Fig.1: Schematic of partial air-gaps only above fin tops using dielectric liners to protect gate stacks during air-gap formation for 10nm finFET CMOS and beyond. (source: IEDM 2016, Paper#17.1, Fig.12)

These air-gaps reduced capacitance at the transistor level by as much as 25%, and in a ring oscillator test circuit by as much as 15%. The researchers say a partial integration scheme—where the air-gaps are formed only above the tops of fin— minimizes damage to the FinFET, as does the high-selectivity etching process used to fabricate them.

Figure 2 shows a cross-section transmission electron micrograph (TEM) of what can go wrong with etch-back air-gaps when all of the processes are not properly controlled. Because there are inherent process:design interactions needed to form repeatable air-gaps of desired shapes, this integration scheme should be extendable “beyond” the “10-nm node” to finFETs formed at tighter pitches. However, it seems likely that “5nm-node” logic FETs will use arrays of horizontal silicon nano-wires (NW), for which more complex air-gap integration schemes would seem to be needed.

Fig.2: TEM image of FinFET transistor damage—specifically, erosion of the fin and source-drain epitaxy—by improper etch-back of the air-gaps at 10nm dimensions. (source: IEDM 2016, Paper#17.1, Fig.10)

—E.K.

Mentor Graphics Extends Offering to Support TSMC 7nm and 16FFC FinFET Process Technologies

Wednesday, September 21st, 2016

Mentor Graphics Corp. (NASDAQ: MENT) today announced further enhancements and optimizations for various products within the Calibre Platform, and Analog FastSPICE (AFS) Platform, as well as the completion of further certifications and reference flows for Taiwan Semiconductor Manufacturing Corporation (TSMC) 16FFC FinFET and 7nm FinFET processes. Moreover, the Calibre offering has been extended on additional established TSMC processes in support of the growing Internet of Things (IoT) design market requirements.

The AFS Platform, including AFS Mega simulation, has been certified for the TSMC 16FFC FinFET and the TSMC 7nm FinFET process technologies through TSMC’s SPICE Simulation Tool Certification Program. The AFS Platform supports TSMC design platforms for mobile, HPC, automotive, and IoT/wearables. Analog, mixed-signal, and RF design teams at leading semiconductor companies worldwide will benefit from using Analog FastSPICE to efficiently verify their chips designed in 16FFC and 7nm FinFET technologies.

Mentor’s Calibre xACT™ extraction offering is now certified for the TSMC 16FFC FinFET and the TSMC 7nm FinFET process technologies. Calibre xACT extraction leverages its built-in deterministic fast field-solver engine to deliver needed accuracy around three-dimensional FinFET devices and local interconnect. Its scalable multiprocessing delivers sufficient punch for large leading-edge digital designs. In addition, both companies continue extraction collaboration in established process nodes, with additional corner variation test cases and tighter criteria to ensure tool readiness for IoT applications.

The Calibre PERC™ reliability platform has also been enhanced to enable TSMC 7nm customers to run point-to-point resistance checks at full chip. This greater capacity allows customers to quickly analyze interconnect robustness at all levels (IP, block, and full chip) while verifying lower resistance paths on critical electrostatic discharge (ESD) circuitry, helping ensure long-term chip reliability. Likewise, Calibre Multi-Patterning functionality has been enhanced for 7nm, including new analysis, graph reduction and visualization capabilities which are essential to customers designing and debugging this completely new multi-patterning technique.

The Calibre YieldEnhancer ECOFill solution, initially developed for 20nm, has now been extended to all TSMC process nodes from 7nm to 65nm. Designers at all process nodes will now be able to minimize fill runtimes, manage fill hierarchy, and minimize shape removal when implementing changes to the initial design.

Mentor’s Nitro-SoC P&R platform has also been enhanced to support advanced 7nm requirements, such as floorplan boundary cell insertion, stacking via routing, M1 routing and cut-metal methodology, tap cell insertion and swapping, and ECO flow methodology. Certification of the flow integration of these N7 features are on-going. For 16FFC, the needed tool features have been validated by TSMC, and Mentor is optimizing its correlation with sign-off analysis.

“Today’s chip design teams are looking at different process nodes to implement their complete solution,” said Joe Sawicki, vice president and general manager of Mentor Graphics Design-to-Silicon Division. “By working with TSMC, Mentor is able to provide mutual customers with a single solution that is not only certified, but also includes the latest tool capabilities, for whichever TSMC process node they choose.”

“TSMC’s long-standing collaboration with Mentor Graphics enables both companies to work together effectively to identify new challenges and develop innovative solutions across all process nodes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The Mentor Analog FastSPICE Platform, AFS Mega, and Calibre xACT tools have successfully met the accuracy and compatibility requirements for 16FFC and 7nm FinFET technologies. That certification, along with the Calibre Platform’s provision of fast, accurate physical verification, and extraction solutions critical to 7nm, ensures mutual customers they have access to EDA tools that are optimized for the newest process technologies.”

Applied Materials Releases Selective Etch Tool

Wednesday, June 29th, 2016

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By Ed Korczynski, Sr. Technical Editor

Applied Materials has disclosed commercial availability of new Selectra(TM) selective etch twin-chamber hardware for the company’s high-volume manufacturing (HVM) Producer® platform. Using standard fluorine and chlorine gases already used in traditional Reactive Ion Etch (RIE) chambers, this new tool provides atomic-level precision in the selective removal of materials in 3D devices structures increasingly used for the most advanced silicon ICs. The tool is already in use at three customer fabs for finFET logic HVM, and at two memory fab customers, with a total of >350 chambers planned to have been shipped to many customers by the end of 2016.

Figure 1 shows a simplified cross-sectional schematic of the Selectra chamber, where the dashed white line indicates some manner of screening functionality so that “Ions are blocked, chemistry passes through” according to the company. In an exclusive interview with Solid State Technology, company representative refused to disclose any hardware details. “We are using typical chemistries that are used in the industry,” explained Ajay Bhatnagar, managing director of Selective Removal Products for Applied Materials. “If there are specific new applications needed than we can use new chemistry. We have a lot of IP on how we filter ions and how we allow radicals to combine on the wafer to create selectivity.”

FIG 1: Simplified cross-sectional schematic of a silicon wafer being etched by the neutral radicals downstream of the plasma in the Selectra chamber. (Source: Applied Materials)

From first principles we can assume that the ion filtering is accomplished with some manner of electrically-grounded metal screen. This etch technology accomplishes similar process results to Atomic Layer Etch (ALE) systems sold by Lam, while avoiding the need for specialized self-limiting chemistries and the accompanying chamber throughput reductions associated with pulse-purge process recipes.

“What we are doing is being able to control the amount of radicals coming to the wafer surface and controlling the removal rates very uniformly across the wafer surface,” asserted Bhatnagar. “If you have this level of atomic control then you don’t need the self-limiting capability. Most of our customers are controlling process with time, so we don’t need to use self-limiting chemistry.” Applied Materials claims that this allows the Selectra tool to have higher relative productivity compared to an ALE tool.

Due to the intrinsic 2D resolutions limits of optical lithography, leading IC fabs now use multi-patterning (MP) litho flows where sacrificial thin-films must be removed to create the final desired layout. Due to litho limits and CMOS device scaling limits, 2D logic transistors are being replaced by 3D finFETs and eventually Gate-All-Around (GAA) horizontal nanowires (NW). Due to dielectric leakage at the atomic scale, 2D NAND memory is being replaced by 3D-NAND stacks. All of these advanced IC fab processes require the removal of atomic-scale materials with extreme selectivity to remaining materials, so the Selectra chamber is expected to be a future work-horse for the industry.

When the industry moves to GAA-NW transistors, alternating layers of Si and SiGe will be grown on the wafer surface, 2D patterned into fins, and then the sacrificial SiGe must be selectively etched to form 3D arrays of NW. Figure 2 shows the SiGe etched from alternating Si/SiGe stacks using a Selectra tool, with sharp Si corners after etch indicating excellent selectivity.

FIG 2: SEM cross-section showing excellent etch of SiGe within alternating Si/SiGe layers, as will be needed for Gate-All-Around (GAA) horizontal NanoWire (NW) transistor formation. (Source: Applied Materials)

“One of the fundamental differences between this system and old downstream plasma ashers, is that it was designed to provide extreme selectivity to different materials,” said Matt Cogorno, global product manager of Selective Removal Products for Applied Materials. “With this system we can provide silicon to titanium-nitride selectivity at 5000:1, or silicon to silicon-nitride selectivity at 2000:1. This is accomplished with the unique hardware architecture in the chamber combined with how we mix the chemistries. Also, there is no polymer formation in the etch process, so after etching there are no additional processing issues with the need for ashing and/or a wet-etch step to remove polymers.”

Systems can also be used to provide dry cleaning and surface-preparation due to the extreme selectivity and damage-free material removal.  “You can control the removal rates,” explained Cogorno. “You don’t have ions on the wafer, but you can modulate the number of radicals coming down.” For HVM of ICs with atomic-scale device structures, this new tool can widen process windows and reduce costs compared to both dry RIE and wet etching.

—E.K.

Technologies for Advanced Systems Shown at IMEC Tech Forum USA

Tuesday, July 14th, 2015

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By Ed Korczynski, Sr. Technical Editor

Luc Van den hove, president and CEO, imec opened the Imec Technology Forum – USA in San Francisco on July 13 by reminding us of the grand vision and motivation behind the work of our industry to empower individuals with micro- and nano-technologies in his talk, “From the happy few to the happy many.” While the imec consortium continues to lead the world in pure materials engineering and device exploration, they now work on systems-integration complexities with over 100 applications partners from agriculture, energy, healthcare, and transportation industries.

We are now living in an era where new chip technologies require trade-offs between power, performance, and bandwidth, and such trade-offs must be carefully explored for different applications spaces such as cloud clusters or sensor nodes. An Steegen, senior vice president process technology, imec, discussed the details of new CMOS chip extensions as well as post-CMOS device possibilities for different applications spaces in her presentation on “Technology innovation: an IoT era.” EUV lithography technology continues to be developed, targeting a single-exposure using 0.33 Numerical Aperture (NA) reflective lenses to pattern features as small as 18nm half-pitch, which would meet the Metal1 density specifications for the industry’s so-called “7nm node.” Patterning below 12nm half-pitch would seem to need higher-NA which is not an automatic extension of current EUV technology.

So while there is now some clarity regarding the pre-competitive process-technologies that will be needed to fabricate next-generation device, there is less clarity regarding which new device structures will best serve the needs of different electronics applications. CMOS finFETs using strained silicon-doped-with-Germanium Si(Ge) will eventually be replaced by gate-all-around (GAA) nano-wires (NW) using alternate-channel materials (ACM) with higher mobilities such as Ge and indium-gallium-arsenide (InGaAs). While many measures of CMOS performance improve with scaling to smaller dimensions, eventually leakage current and parasitic capacitances will impede further progress.

Figure 1 shows a summary of energy-vs.-delay analyses by imec for all manner of devices which could be used as switches in logic arrays. Spin-wave devices such as spin-transfer-torque RAM (STT-RAM) can run at low power consumption but are inherently slower than CMOS devices. Tunnel-FET (TFET) devices can be as fast or faster than CMOS while running at lower operating power due to reduced electrostatics, leading to promising R&D work.

Fig.1: Energy vs. delay for various logic switches. (Source: imec)

In an exclusive interview, Steegen explained how the consortium balances the needs of all partners in R&D, “When you try to predict future roadmaps you prefer to start from the mainstream. Trying to find the mainstream, so that customers can build derivatives from that, is what imec does. We’re getting closer to systems, and systems are reaching down to technology,” said Steegen. “We reach out to each other, while we continue to be experts in our own domains. If I’m inserting future memory into servers, the system architecture needs to change so we need to talk to the systems people. It’s a natural trend that has evolved.”

Network effects from “the cloud” and from future smart IoT nets require high-bandwidth and so improved electrical and optical connections at multiple levels are being explored at imec. Joris Van Campenhout, program director optical I/O, imec, discussed “Scaling the cloud using silicon photonics.” The challenge is how to build a 100Gb/s bandwidth in the near term, and then scale to 400G and then 1.6T though parallelism of wavelength division multiplexing; the best results to date for a transmitter and receiver reach 50Gb/s. By leveraging the existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon photonics platform enables high integration density and reduced power consumption, as well as high yield and low manufacturing cost. Supported by EDA tools including those from Mentor Graphics, there have been 7 tape-outs of devices in the last year using a Process Design Kit (PDK). When combined with laser sources and a 40nm node foundry CMOS chip, a complete integrated solution exists. Arrays of 50Gb/s structures can allow for 400Gb/s solutions by next year, and optical backplanes for server farms in another few years. However, to bring photonics closer to the chip in an optical interposer will require radical new new approaches to reduce costs, including integration of more efficient laser arrays.

Alexander Mityashin, project manager thin film electronics, imec, explained why we need, “thin film electronics for smart applications.” There are billions of items in our world that could be made smarter with electronics, provided we can use additive thin-film processes to make ultra-low-cost thin-film transistors (TFT) that fit different market demands. Using amorphous indium-gallium-zinc-oxide (a-IGZO) deposited at low-temperature as the active layer on a plastic substrate, imec has been able to produce >10k TFTs/cm2 using just 4-5 lithography masks. Figure 2 shows these TFT integrated into a near-field communications (NFC) chip as first disclosed at ISSCC earlier this year in the paper, “IGZO thin-film transistor based flexible NFC tags powered by commercial USB reader device at 13.56MHz.” Working with Panasonic in 2013, imec showed a flexible organic light-emitting diode (OLED) display of just 0.15mm thickness that can be processed at 180°C. In collaboration with the Holst Center, they have worked on disposable flexible sensors that can adhere to human skin.

Fig.2: Thin-Film Transistors (TFT) fabricated on plastic using Flat Panel Display (FPD) manufacturing tools. (Source: imec/Holst Center)

Jim O’Neill, Chief Technology Officer of Entegris, expanded on the systems-level theme of the forum in his presentation on “Putting the pieces together – Materials innovation in a disruptive environment.” With so many additional materials being integrated into new device structures, there are inherently new yield-limiting defect mechanisms that will have to be controlled. With demand for chips now being driven primarily by high-volume consumer applications, the time between first commercial sample and HVM has compressed such that greater coordination is needed between device, equipment, and materials companies. For example, instead of developing a wet chemical formulation on a tool and then optimizing it with the right filter or dispense technology, the Process Engineer can start envisioning a “bottle-to-nozzle wetted surface solution.” By considering not just the intended reactions on the wafer but the unintended reactions that can occur up-steam and down-stream of the process chamber, full solutions to the semiconductor industry’s most challenging yield problems can be more quickly found.

—E.K.

Silicon Summit speakers look at the future of chip technology

Friday, April 17th, 2015
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Gregg Bartlett

By Jeff Dorsch, Contributing Editor

Quick quiz: What topics do you think were discussed at length Wednesday at the Global Semiconductor Alliance’s Silicon Summit?

A. The Internet of Things.

B. Augmented reality and virtual reality.

C. Cute accessories for spring and summer looks.

The answers: A and B. C could be right if you count wearable electronics as “cute accessories.”

Wednesday’s forum at the Computer History Museum in Mountain View, Calif., not far from  Google’s headquarters, was dominated by talk of IoT, AR, VR, and (to a lesser extent) wearable devices.

Gregg Bartlett, senior vice president of the Product Management Group at GlobalFoundries, kicked off the morning sessions with a talk titled “IoT: A Silicon Perspective.” He said, “A lot of the work left in IoT is in the edge world.”

Bartlett noted, “A lot of the infrastructure is in place,” yet the lack of IoT standards is inhibiting development, he asserted.

“IoT demands the continuation of Moore’s Law,” Bartlett said, touting fully-depleted silicon-on-insulator technology as a cost-effective alternative to FinFET technology. FD-SOI “is the killer technology for IoT,” he added.

Next up was James Stansberry, senior vice president and general manager of IoT Products at Silicon Laboratories. Energy efficiency is crucial for IoT-related devices, which must be able to operate for 10 years with little or no external power, he said.

Bluetooth Smart, Thread, Wi-Fi, and ZigBee provide the connectivity in IoT networks, with a future role for Long-Term Evolution, according to Stansberry. He also played up the importance of integration in connected devices. “Nonvolatile memory has to go on the chip” for an IoT system-on-a-chip device, he said.

For 2015, Stansberry predicted a dramatic reduction in energy consumption for IoT devices; low-power connectivity standards will gain traction; and the emergence of more IoT SoCs.

Rahul Patel, Broadcom’s senior vice president and general manager of wireless connectivity, addressed health-care applications for the IoT. “Security is key,” he said. Reliability, interoperability, and compliance with government regulations are also required, Patel noted.

“My agenda is to scare everyone to death,” said Martin Scott, senior vice president and general manager of the Cryptography Research Division at Rambus. Cybersecurity with the IoT is causing much anxiety, he noted. “Silicon can come to the rescue again,” he said. “If your system relies on software, it’s hackable.”

To build trust in IoT devices and networks, the industry needs to turn to silicon-based security, according to Scott. “Silicon is the foundation of trusted services,” he concluded.

The second morning session was titled “The Future of Reality,” with presentations by Keith Witek, corporate vice president, Office of Corporate Strategy, Advanced Micro Devices; Mats Johansson, CEO of EON Reality; and Joerg Tewes, CEO of Avegant.

Augmented reality and virtual reality technology is “incredibly exciting,” Witek said. “I love this business.” He outlined four technical challenges for VR in the near future: Improving performance; ensuring low latency of images; high-quality consistency of media; and system-level advances. “Wireless has to improve,” Witek said.

VR is “starting to become a volume market,” Johansson said. What matters now is proceeding “from phone to dome,” where immersive experiences meet knowledge transfer, he added. Superdata, a market research firm, estimates there will be 11 million VR users by next year, according to Johansson.

Avegant had a successful Kickstarter campaign last year to fund its Glyph VR headset, with product delivery expected in late 2015, Tewes said. The Glyph has been in development for three years, he said, employing digital micromirror device technology, low-power light-emitting diodes, and latency of less than 12 microseconds to reduce or eliminate the nausea that some VR users have experienced, he said.

The afternoon session was devoted to “MEMS and Sensors, Shaping the Future of the IoT.” Attendees heard from Todd Miller, Microsystems Lab Manager at GE Global Research; Behrooz Abdi, president and CEO of InvenSense; Steve Pancoast, Atmel’s vice president of software and applications; and David Allan, president and chief operating officer of Virtuix.

Miller outlined the challenges for the industrial Internet – cybersecurity, interoperability, performance, and scale. “Open standards need to continue,” he said.

General Electric and other companies, including Intel, are involved in the Industrial Internet Consortium, which is developing use cases and test beds in the area, according to Miller.

He noted that GE plans to begin shipping its microelectromechanical system devices to external customers in the fourth quarter of this year.

Abdi said, “What is the thing in the Internet of Things? The IoT is really about ambient computing.” IoT sensors must continuously answer these questions: Where are you, what are you doing, and how does it feel, he said.

The IoT will depend upon “always on” sensors, making it more accurate to call the technology “the Internet of Sensors,” Abdi asserted. He cautioned against semiconductor suppliers getting too giddy about business prospects for the IoT.

“You’re not going to sell one billion sensors for a buck [each],” Abdi said.

Pancoast of Atmel said sensors would help provide “contextual computing” in IoT networks. “Edge/sensing nodes are a major part of IoT,” he noted. Low-power microcontrollers and microprocessors are also part of the equation, along with “an ocean of software” and all IoT applications, Pancoast added. He finished with saying, “All software is vulnerable.”

Allan spoke about what he called “the second machine age,” with the first machine age dating to 1945, marking the advent of the stored-program computer and other advances. “The smartphone is the first machine of the second machine age,” he said.

IoT involves wireless sensor networks and distributed computing, he said. Google has pointed the way over the past decade, showing how less-powerful computers, implemented in large volumes, have become the critical development in computing, Allan noted. Because of this ubiquity of distributed computing capabilities, “Moore’s Law doesn’t matter as much,” he said.

With the IoT, “new machines will augment human desires,” Allan predicted, facilitating such concepts as immortality, omniscience, telepathy, and teleportation. He explained how technology has helped along the first three – we know what people are thinking through Facebook and Twitter – and the last is just a matter of time, according to Allan.

TSMC Certifies Mentor Graphics Tools for Early Design Start in TSMC’s 10nm FinFET Technology

Monday, April 6th, 2015

Mentor Graphics Corp. (NASDAQ: MENT) announced that TSMC and Mentor Graphics have reached the first milestone of their collaboration on 10nm EDA certification. Calibre® physical verification and design for manufacturing (DFM) platform, and the Analog FastSPICE™ (AFS™) Circuit Verification Platform, including AFS Mega, are certified by TSMC based on the most current version of 10nm design rules and SPICE models.  New tool feature enhancement based on 10nm process requirements has been made in Olympus-SoC™ digital design platform with TSMC validation, and certification of full chip integration is actively on-going. In addition to 10nm, Mentor has also completed 16FF+ version 1.0 certification of the Calibre, Olympus-SoC and AFS platforms. These certifications provide designers with the earliest access to signoff technology optimized for TSMC’s most advanced process nodes, with improved performance and accuracy.

“The long-term partnership we have with Mentor Graphics enables us to work closely from the earliest phases of technology development so we can have production ready design kits and software available for our customers concurrently with the announcement of new process offerings,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “Mentor’s design solutions have successfully met the accuracy and compatibility requirements for TSMC 10nm FinFET technology, so customers can initiate their designs with accurate verification solutions.”

The Analog FastSPICE Platform provides fast circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. For large circuits the AFS Platform also delivers high capacity and fast mixed-signal simulation. For embedded SRAM and other array-based circuits, AFS Mega delivers highly accurate simulation results.

As circuit reliability remains a focus, Mentor and TSMC have enhanced the Calibre PERC™ product offering in 10nm to ensure that design and IP development teams have robust verification solutions for identifying sources of electrical error. Additionally, the Calibre xACT™ extraction suite includes updated models to deliver more accurate results to fulfill tighter accuracy requirements of 10nm.

For TSMC’s 16FF+ 1.0 Calibre design kit release, the Calibre team has worked with TSMC to speed up DRC performance by 30% on average. In addition, TSMC and Mentor released new filling use models that will improve first-pass fill runs, making ECO changes easier and faster. The new fill methodology will also help ensure consistent cycle times during post fill verification.

“Because Mentor and TSMC work together from the earliest stages of design rule development for a new process node, we learn what the new design and verification challenges are right along with TSMC.” said Joseph Sawicki, vice president and general manager of the Design to Silicon division at Mentor Graphics. “This gives us the ability to have the most advanced capabilities in place for ecosystem early adopters, and to continue to optimize performance as the new process moves to full production status.”

Time to “shift left” in chip design and verification, Synopsys founder says

Wednesday, March 4th, 2015

By Jeff Dorsch, contributing editor

The world is moving toward “Smart Everything,” according to Aart de Geus, founder, chairman, and co-CEO of Synopsys. “The door will open gradually, and then quickly,” he said in Tuesday’s keynote address at the Design and Verification Conference and Exhibition, or DVCon, in San Jose, Calif.

“The assisted brain is on the way,” de Geus told the standing-room-only audience. “This may be dreaming, but I don’t think so.”

Taking “Smart Design from Silicon to Software” as his official theme, the veteran executive urged attendees to “shift left” – in other words, “squeezing the schedule” to design, verify, debug, and manufacture semiconductors. “Schedules haven’t changed much,” de Geus said. The difference now is that the marketing department has as much influence in planning and scheduling a new product as the engineering department, he noted.

Chip designers also should “shift left” on semiconductor intellectual property, de Geus said. “IP reuse is the biggest change in 15 to 30 years,” he asserted. “Reuse leverages your innovation.”

After plugging the concepts of unified compilation and unified debugging architectures, de Geus touted the use of virtual prototypes in chip design. “Software guys are impatient with you,” he said. Synopsys, he noted, has created 400 million lines of software code.

Turning to the Internet of Things, de Geus said, “There are a lot of opportunities there.” The problem is “these things are full of cracks,” he added. There are significant engineering and security issues that must be addressed in networks of connected devices.

Developing the FinFET “was said to be impossible seven to eight years ago,” de Geus said. Nonetheless, the semiconductor industry was able to realize that advanced technology to move beyond the 28-nanometer process node, he noted. The future is likely to present similar challenges.

Solid State Watch: February 13-19, 2015

Friday, February 20th, 2015
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Blog review January 26, 2015

Monday, January 26th, 2015

Scott McGregor, President and CEO of Broadcom, sees some major changes for the semiconductor industry moving forward, brought about by rising design and manufacturing costs. Speaking at the SEMI Industry Strategy Symposium (ISS) in January, McGregor said the cost per transistor was rising after the 28nm, which he described as “one of the most significant challenges we as an industry have faced.” Pete Singer reports.

Matthew Hogan, Mentor Graphics writes a tongue-in-cheek blog about IP, saying chip designers need only to merely insert the IP into the IC design and make the necessary connections. Easy-peasey! Except…robust design requires more than verifying each separate block—you must also verify that the overall design is robust. When you are using hundreds of IPs sourced from multiple suppliers in a layout, how do you ensure that the integration of all those IPs is robust and accurate?

Dick James, Senior Analyst at Chipworks IEDM blogs that Monday was FinFET Day. He highlights three finFET papers, by TSMC, Intel, and IBM.

A research team led by folks at Cornell University (along with University of California, Berkeley; Tsinghua University; and Swiss Federal Institute of Technology in Zurich) have discovered how to make a single-phase multiferroic switch out of bismuth ferrite (BiFeO3) as shown in an online letter to Nature. Ed Korczynski reports.

SEMI praised the bipartisan effort in the United States Congress to pass the Revitalize American Manufacturing and Innovation (RAMI) Act as part of the year-end spending package. Since its introduction in August 2013, SEMI has been a champion and leading voice in support of the bill that would create public private partnerships to establish institutes for manufacturing innovation.

Phil Garrou takes a look at some of the key presentations at the 2014 IEEE 3DIC Conference recently held in Cork, Ireland.

Adele Hars writes that there were about 40 SOI-based papers presented at IEDM. In Part 1 of ASN’s IEDM coverage, she provides a rundown of the top SOI-based advanced CMOS papers.

Karen Lightman of the MEMS Industry Group says power is the HOLY GRAIL to both the future success of wearables and IoT/Everything.  Power reduction and management through sensor fusion, power generation through energy harvesting as well as basic battery longevity. It became very clear from conversations at the MIG conference as well as in talking with folks on the CES show floor that the issue of power is the biggest challenge and opportunity facing us now.

In order to keep pace with Moore’s Law, semiconductor market leaders have had to adopt increasingly challenging technology roadmaps, which are leading to new demands on electronic materials (EM) product quality for leading-edge chip manufacturing. Dr. Atul Athalye, Head of Technology, Linde Electronics, discusses the challenges.

Solid Doping for Bulk FinFETs

Monday, January 5th, 2015

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By Ed Korczynski, Sr. Technical Editor

In another example of the old one-liner that “all that is old is new again,” the old technique of solid-source doping is being used by Intel for a critical process step in so-called “14nm node” finFET manufacturing. In the 7th presentation in the 3rd session of this year’s IEDM, a late news paper written by 52 co-authors from Intel titled “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588m2 SRAM Cell Size” disclosed that solid source doping was used under the fins.

As reported by Dick James of Chipworks in his blog coverage of IEDM this year, the fins have a more vertical profile compared to the prior “22nm node” and are merely 8nm wide (Fig. 1). Since Intel is still using bulk silicon wafers instead of silicon-on-insulator (SOI), to prevent leakage through the substrate these 8nm fins required a new process to make punch-through stopper junctions, and the new sub-fin doping technique uses solid glass sources. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over the prior node, and Idlin by 30% for NMOS and 38% for PMOS.

FIGURE: Intel Corp’s “14nm node” finFETs show (in the left SEM) 8nm wide and 42nm high fins in cross-section, below which are located the punch-through stopper junctions. (Source: IEDM 2014, Late News 3.7)

Solid glass sources of boron (B) and phosphorous (P) dopants have been used for decades in the industry. In a typical application, a lithographically defined silicon-nitride hard-mask protects areas from a blanket deposition in a tube furnace of an amorphous layer containing the desired dopant. Additional annealing before stripping off the dopant layer allows for an additional degree of freedom in activating dopants and forming junctions.

In recent years, On Semiconductor published how solid-source doping on the sidewalls of Vertical DMOS transistors enable a highly phosphorous doped path for the drain current to be brought back to the silicon surface. The company shows that phosphorous-oxy-chloride (POCl) and phospho-silicate glass (PSG) sources can both be used to form heavily doped junctions 1-2 microns deep.

The challenge for solid-source doping of 8nm wide silicon fins is how to scale processes that were developed for 1-2 microns to be able to form repeatable junctions 1-2 nm in scale. Self-aligned lithographic techniques could be used to mask the tops of fins, and various glass sources could be used. It is likely that ultra-fast annealing is needed to form stable ultra-shallow junctions.

Intel is notoriously protective of process Intellectual Property (IP) and so has almost certainly ensured that any equipment and materials suppliers who work on the solid-source doping process sign Non-Disclosure Agreements (NDA) with amendments that forbid acknowledging signing the NDA itself, so it is pointless to directly ask for any further details at this point. However, slides from John Borland’s recent presentation at the NCCAVS Junction Technology Users Group meeting provide a great overview of the publicly available information on finFET junction formation, and include the following:

…higher dopant activation can be realized at low temperatures if the junction is amorphous and recrystalized by using SPE (solid phase epitaxy) recrystalization of the junction as also shown in the data by Intel.

Also seen at IEDM this year in the 7th presentation of the Advanced Process Modules section, Taiwanese researchers—National Nano Device Laboratories, National Chiao Tung University, and National Cheng Kung University—joined with Californian consultants—Current Scientific, Evans Analytical Group—to show “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing.” They claim an ideal subthreshold swing (~60 mV/dec) at a high doping level. Poly-Si n & p JLFinFETs (W/L=10/20 nm) with SDP experimentally exhibit superior gate control (Ion/Ioff >10E6) and improved device variation.

—E.K.

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