By Mark LaPedus

The complexity of today’s chips is forcing silicon foundries to expand on both the leading-edge and specialty-process fronts.

For example, GlobalFoundries is expanding in both areas. On the specialty process front, GlobalFoundries confirmed that it recently bought 300mm fab tools from Taiwan’s ProMos Technologies. Many of the tools will be used within GlobalFoundries’ 300mm fab in Singapore, which makes wafers based on various analog and mixed-signal processes. The idea behind this move is to offer “mixed-signal technologies with 300mm economies of scale,” said Michael Noonen, executive vice present of global sales, marketing, quality and design at GlobalFoundries.

On the leading-edge, the silicon foundry vendor recently expanded its technology platform offerings to five, including bulk planar, super-steep retrograde well (SSRW), fully-depleted silicon-on-insulator (minimum), fully-depleted silicon-on-insulator (maximum) and finFET.

Despite a recent setback with FD-SOI, GlobalFoundries will continue to offer the technology and also gave a ringing endorsement about FD-SOI. In March, Ericsson and STMicroelectronics announced plans to disband ST-Ericsson, a supplier of cell-phone chipsets, including an integrated applications processor based on FD-SOI. Ericsson will take on the design, development and sales of the LTE multimode modem products from ST-Ericsson. STMicroelectronics assumed the ownership of the integrated applications processor based on FD-SOI.

Meanwhile, for some time, GlobalFoundries and STMicroelectronics have had a foundry arrangement under which GlobalFoundries will make FD-SOI products on a foundry basis for STMicroelectronics. GlobalFoundries has not wavered in its support for FD-SOI, saying it will continue to provide the technology on a foundry basis for customers.

FD-SOI provides a viable option for customers, enabling them to differentiate their products, Noonen said. “We want to supply options to customers,” he said. “There is a tremendous amount of interest (for FD-SOI).”

Noonen is also seeing strong interest for its finFET process. GlobalFoundries, Samsung and TSMC have all accelerated their finFET process roadmaps. “We’ve accelerated it,” said Morris Chang, chairman and chief executive of Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), at a recent event. At the event, TSMC reiterated its finFET roadmap, saying it would move into “risk production” by the fourth quarter of 2013.

Like TSMC and Samsung, GlobalFoundries is in mass production for its 28nm processes and is ramping up its 20nm technology. “20nm will be a fast ramp,”  Noonen said. “In general, 28nm is going to be a long-lived node.”

On the specialty process front, meanwhile, GlobalFoundries recently disclosed an initiative called “Vision 2015.”  The initial phase of the plan will include a capacity expansion of its current Fab 7 300mm facility to be on a trajectory of nearly 1 million wafers per year, up from 600,000 wafers a year right now. The expansion is expected to be completed by the middle of 2014.

As part of that effort, GlobalFoundries wants to give analog- and mixed-signal customers a viable 300mm option to compete against the analog leader—Texas Instruments. For some time, TI has been in production within the world’s first 300mm analog fab, dubbed RFAB, based in Texas.

“We want to be the answer to that,” Noonen said.

By Mark LaPedus
A year ago, chipmakers were reeling from a severe shortage of 28nm foundry capacity, prompting foundries to ramp up their fabs at a staggering pace.

At the time, foundries were unable to keep up with huge and unforeseen demand for mobile chips. The shortfall was also caused by low yields and the overall lack of installed 28nm capacity.

Today, the 28nm crunch is largely over. The foundries have caught up with the demand and customers no longer are feeling the pinch. And as it turns out, 28nm is a sweet spot for many devices and the technology will remain a long-lasting node.

However, the overzealous foundries may have expanded too fast. In fact, there are some signs of a possible foundry glut, and falling fab utilization rates, for 28nm and other processes in 2013. “I don’t see a shortage problem,” said Samuel Wang, an analyst at Gartner. “But overall utilization rates for advanced technologies will go down this year.”

Mobile chipmakers represent the biggest customers for foundries, but pockets of the business are cooling off to some degree. So, unless there is a steep upturn in the near term, the foundry market may quickly turn into a buyers’ market in 2013. Average selling prices for wafers could steadily drop, putting a squeeze on foundry margins.

Besides 28nm, foundries are simultaneously developing 20nm planar and 14nm-class finFETs. In doing so, foundries are moving toward the long-awaited “virtual IDM” model, where vendors and customers collaborate more closely under the same roof.

The shift towards the “virtual IDM” model is easier said than done, however. “The foundries will have some obstacles,” said Robert Bruck, vice president and general manager of the Technology Manufacturing Engineering Group at Intel. “Design, process technology, development and equipment costs are going up.”

As the costs and challenges mount, there are signs that the leading-edge foundry business is ripe for a shakeout. Currently, there are six companies that provide leading-edge foundry services in one form or another: GlobalFoundries, IBM, Intel, Samsung, TSMC and UMC.

28nm glut?
In total, the IC market is expected to increase 6% in 2013, compared to a drop of 1% in 2012, said Bill McClean, president of IC Insights. Capital spending is expected to fall 10% in 2013, but foundry CapEx will remain flat this year, he added.

For 28nm alone, the foundries had a total capacity of 200,000 wafer starts per month (wspm) by the end of 2012, according to Barclays Capital. In 2013, the foundries are expected to add an additional capacity of 75,000 to 100,000 wspm for 28nm, according to Mike Splinter, chairman and chief executive of Applied Materials.

And at 20nm, the foundries are expected to have a total capacity of 25,000 wspm in 2013, Splinter said in a recent conference call. Most of that capacity will be added in the second half of 2013, he said.

Splinter projects that the worldwide wafer fab equipment (WFE) market will be flat to minus 10% in 2013, up from minus 5% to minus 15% from his previous forecast. “We think the foundries will be down, but not as low as we expected,” he said.

CapEx race
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is showing no signs of a slowdown. The world’s largest foundry vendor has increased its capital spending from $8.3 billion in 2012 to $9 billion or more in 2013.

For 28nm, TSMC is expanding its capacity threefold in 2013 over 2012, said Morris Chang, chairman and chief executive of TSMC. In 2012, the polysilicon version of 28nm represented 100% of TSMC’s output. TSMC is expanding its 28nm high-k/metal-gate technology, which will reach the crossover point in the third quarter of 2013, he said.

The company also sees strong demand for 20nm. Apple will have its upcoming 20nm A7 application processors made on a foundry basis by TSMC, according to Barclays Capital, which noted that Apple is switching foundry vendors from Samsung to TSMC.

Meanwhile, GlobalFoundries, the world’s second largest foundry vendor, has set its capital spending budget at $3.5 billion in 2013, said Ajit Manocha, chief executive of GlobalFoundries. In 2012, GlobalFoundries’ capital spending hit $3.2 billion, according to Barclays.

The spending will help GlobalFoundries’ efforts to become more of a “virtual IDM.” In January, GlobalFoundries announced plans to build a multi-billion dollar R&D facility at its Fab 8 campus in Saratoga County, N.Y. The company’s new Technology Development Center (TDC) will help accelerate its 10nm and 7nm process development.

The TDC will also house part of GlobalFoundries’ stacked-die packaging and advanced photomask efforts. As photomask complexities soar, “some customers want a turnkey solution,” Manocha said.

Within its new 300mm fab in New York, the company has begun ramping up 28nm and 20nm processes. In 2013, Fab 8 is expected to expand from 10,000 to 30,000 wafers a month. “That’s still on plan,” he said. “We are also expanding our fab production in Dresden and Singapore.”

In total, GlobalFoundries will offer five technology platforms: bulk planar, bulk finFET, super-steep retrograde well (SSRW), FD-SOI (minimum) and FD-SOI (maximum). Customer tapeouts for its 14nm-class finFETs are expected in 2013, with production slated for 2014.

The maximum version of FD-SOI is tuned for specific applications, said Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries. Meanwhile, the minimum version is a simple and an “out of the box” FD-SOI technology, Kengeri said.

The company will provide FD-SOI wafers on a foundry basis for STMicroelectronics and other customers. GlobalFoundries’ 28nm FD-SOI process will move into risk production in the fourth quarter of 2013, with production slated for the first quarter of 2014.

Meanwhile, amid the apparent loss of a major customer in Apple, Samsung has cut its logic capital spending from 8 trillion Korean won in 2012 to between 4 trillion and 4.5 trillion Korean won in 2013, according to Barclays. Apple accounts for roughly one-third of Samsung’s logic capacity.

Samsung’s main logic/foundry fab is called S1, which is in Korea. S1 is making 28nm devices and is capable of low-volume finFET production. “S1 has more than doubled its size over the last year,” said Ana Hunter, vice president of foundry services at Samsung Semiconductor.

In Austin, Texas, Samsung has two 300mm fabs, plus a copper metallization facility. One fab is a foundry/logic plant. The fab, dubbed S2, has been a dedicated foundry plant for Apple. The other fab in Austin was previously a NAND facility. Last year, Samsung converted that fab from NAND into a 28nm logic/foundry plant.

In 2012, the company put on the brakes on its new S3 fab, a 300mm plant in Korea. “S3 resumed construction at the end of January,” said Christian Gregor Dieseldorff, an analyst at SEMI. “Equipment may begin to move in by mid-year. I think this may be the earliest.”

The S3 fab, which is expected to ramp up in 2014, will manufacture 20nm planar devices and 14nm-class finFETs. With process design kits available today, Samsung is expected to sample finFETs in 2014. In addition, the company has deployed “training teams” to help customers with their finFET designs, Samsung’s Hunter said.

The complexity of new and advanced designs will require more handholding between the foundries and their customers. “The collaboration has to get deeper with customers,” she added.

In moving towards the virtual IDM model, the foundries face some challenges. “There are very large investments that are required,” Intel’s Bruck said. “How do you accelerate the yield learning? What about the IP issues? Another aspect in terms of the foundry model is the delay that we are seeing in terms of revenue on the leading-edge.”

All chipmakers, including Intel, face the same challenge: How to keep up with the soaring R&D costs associated with the new and emerging technologies? “R&D is weighing on every level on the supply chain in this industry,” he added.

Foundry companies are keeping a close eye on Intel. To date, Intel is only providing foundry services to a limited customer base, and shows no signs of expanding the offering to a broader audience. So far, the chip maker is providing its 22nm finFET technology on a foundry basis to flow processor supplier Netronome and two FPGA vendors, Achronix and Tabula. In addition, Intel recently announced capital spending of $13 billion in 2013, including $2 billion for 450mm development.

Meanwhile, Taiwan foundry vendor United Microelectronics Corp. (UMC) continues to fall behind, as the company said it is having yield issues with its 28nm process. In addition, UMC recently said it will move directly from 28nm to 14nm finFETs, thereby skipping the 20nm node.

By Ann Steffora Mutschler
Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node.

“They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant of this shape or this line width or whatever that is creating a yield problem or weak patterns,” observed Michael White, director of product marketing for Calibre physical verification at Mentor Graphics. “Starting at 40nm, even more so at 28nm and that much again at 20nm, is much more orientation-specific layout because folks are using more off-axis illumination. You pay a huge penalty for having optimized the aperture in your scanner for things that are oriented north-south. If you’ve got structures that are east-west they’re not going to resolve as well.”

One approach to deal with these issues termed ‘bad pattern flow’ is based on the idea that the designer can almost do anything they want, but certain 2D patterns are walled off as being bad and forbidden.

Coming at the problem from another perspective is the concept of ‘good pattern flow,’ based on the premise that, “in the future, maybe not everything is going to be manufacturable anymore,” explained Ya-Chieh Lai, engineering director at Cadence. “So the designer is going to be much more constrained moving forward, and the space of the design is really that most things are actually not going to print very well anymore. There’s a sense that maybe we need to have a better understanding of which things do manufacture well and come up with a set of patterns to represent that.”

While not in use at 20nm, this good pattern flow is being readied for the 14nm and 10nm nodes when design rule restrictions become even more severe. But to be enabled in the design flow will require the whole ecosystem to come together, he said.

“We’re working hard on having the core capabilities and tools. We need to work closely with the foundries, because they’re ultimately the source of all of these patterns and a lot of this analysis, to provide the right tools and capabilities to do the kinds of analyses they need to do. We also have to work in conjunction with the design side tools to enable this. This is all a work in progress.”

Specifically, Manoj Chacko, product marketing director at Cadence, pointed out that just as with bad pattern usage, the value to the designer of a good pattern flow is at the routing stage. “Find the issues early on and remove them before going through the signoff. The good pattern flow also mostly fits with the routing side and enforces certain patterns and makes the router enforce certain topologies.”

In terms of where the tools are now, work is being done with the foundries to make sure there is understanding about what the patterns are and how they are used. “A key part of what we are working on here is pattern analysis,” said Lai. “There’s been a lot of talk about pattern matching, but pattern analysis is a bigger story about understanding your layout. The foundries need to understand what designers are doing, be able to understand what patterns are in the design, what are the common cases and the outlier cases to make sure their manufacturing processes are tuned to be able to print what the designers are actually doing. A big part of that is analyzing what is actually in the design.”

Pushback is possible
Mentor’s White expects significant pushback to the good pattern flow strategy. “Over the last couple of years as we’ve been moving pattern matching out into the mainstream use for physical verification, we have some folks who love the ease of use of pattern matching and so on, and their foundry was headed down the path of trying to use more pattern matching to describe actual design rules. The frustration was that, ‘If I’m using patterns to describe only a very finite, small set of things that are manufacturable, you’re taking the design freedom away from the designer.’ They’d far prefer to have the foundry characterizing a broader application space of layout and maintain the designer’s freedom rather than solely focusing their attention on a smaller set of patterns that are known manufacturable.”

Lai agreed there’s always tension about being as restrictive as possible. “If it were up to the foundry they’d just want you to print grading—it’s just going to be straight lines because they know they can print that. But the designers want more flexibility to draw what they need to draw. So what we’re trying to do with the good patterns is to say, ‘We’re going to be as restrictive as possible but then we’re going to allow certain things to be used that would otherwise have been restricted by these restrictive design rules.’ That way it really is meant to help the designer where instead of putting on the brakes and saying, ‘No, you can’t do anything except use these very straight repeated structures,’ we are saying there are going to be certain things that are going to be allowed. These are allowed constructs that you as a designer can put in because this is what you need to make your design work, but everything else is going to be very locked in.”

At the end of the day, “the goal is to minimize patterning,” said Subramani Kengari, vice president of design solutions at GlobalFoundries. “But you also have to optimize a solution. That’s the main reason we’re using wide power rails on standard cells.”

Another consideration: As it stands, not all of the metal layers in a design at 20nm, or even the hybrid 20nm back-end of line (BEOL) process are coupled with 14nm finFETs. But as Moore’s Law continues, more layers will have to be at least double patterned, and with 14nm BEOL some parts of the chip will have to be triple or quadruple patterned.

With this just one example of the complexity that will be faced, a good pattern flow seems more reasonable. And given that designs are becoming much more regular at these advanced nodes is one reason a good pattern flow even becomes a possibility.

By Mark LaPedus

Raising the ante in the foundry business, GlobalFoundries has added a 10nm finFET process to its roadmap and expanded its technology platform offerings.

The foundry vendor plans to move into production with its 10nm finFET process in 2015, a year after its recently introduced 14nm finFET technology. In addition, the foundry vendor has also expanded its technology platform offerings to five, including bulk planar, super-steep retrograde well (SSRW), fully depleted silicon-on-insulator (minimum), fully depleted silicon-on-insulator (maximum) and finFET.

Perhaps the biggest surprise on the roadmap is SSRW, a technology that controls short-channel effects using a doping technique. For SSRW, GlobalFoundries has been talking to SuVolta about the technology, according to multiple sources, but it’s unclear if the companies  have reached a deal.

Ajit Manocha, chief executive of GlobalFoundries, disclosed the company’s new roadmap during a keynote presentation at the 2012 IEEE International Electron Devices Meeting (IEDM) in San Francisco on Tuesday. During the keynote, Manocha also addressed GlobalFoundries’ capacity plans, 450mm fabs and EUV.  In fact, GlobalFoundries is not counting on EUV for the 10nm node.

His keynote was entitled, “Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!” During the keynote, Manocha said the fabless/foundry model is alive and well in spite of recent comments from an undisclosed party.  “Somebody said the foundry business is dead,” he said. “The same company wants to get into the foundry business. Something doesn’t add up.”

The comments may have been directed towards Intel. In a recent interview with SemiMD, Mark Bohr, senior fellow at Intel, said: “The traditional foundry model is running into problems. In order to survive, the foundries will have to become more like an integrated device manufacturer. Being an IDM, we have design and process development under one roof. That’s really a significant advantage.”

At IEDM, Manocha agreed the foundries must act more like IDMs or virtual IDMs, saying the old model simply doesn’t work. “The traditional foundry model is that you work in isolation,” he said. “It doesn’t work.”

In the new model, dubbed Foundry 2.0, there is a deeper and earlier collaboration between foundries and their customers, he said. GlobalFoundries refers to its strategy as a “collaborative device manufacturer.”

New Technologies

As part of its strategy, GlobalFoundries continues to expand and accelerate its foundry offerings.  Within its new 300mm fab in New York, the company has begun ramping the plant for 28nm and 20nm technology. In 2013, the New York fab will be capable of running 30,000 wafers a month. At some point, the fab will capable of running 50,000 wafers a month.

Meanwhile, in September, GlobalFoundries rolled out its finFET technology for the 14nm node. GlobalFoundries is taking a “modular fin” approach with its bulk finFET offering, dubbed 14nm-XM. The 14nm-XM combines a 14nm-class fin with its 20nm back-end-of-line (BEOL) interconnect flow.

By taking the modular approach, the company has accelerated its process roadmap by a year. Early process design kits (PDKs) are available, with customer product tape-outs expected in 2013. Production, which is slated for 2014, will take place within GlobalFoundries’ new 300mm fab in New York.

Then, in October, rival Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) updated and accelerated its process roadmap. The world’s largest silicon foundry has accelerated its 16nm finFET efforts by one quarter and added a 10nm finFET technology to the roadmap. TSMC’s 10nm finFET process, dubbed CLN10FF, is expected to move into risk production close to the end of 2015.

GlobalFoundries moved to keep pace with TSMC. At IEDM, GlobalFoundries disclosed a 10nm finFET process, which is due out in 2015, or a year after 14nm finFET.  “We have accelerated (the 10nm finFET process),” Manocha said after his keynote at IEDM.

At 10nm, GlobalFoundries and others may be forced to extend 193nm immersion, while also going with a multiple patterning scheme. EUV is late to the party and may miss the 10nm node. “10nm will be optical,” he said. “We have evidence that we can do 7nm with immersion.”

GlobalFoundries did not describe the details of its 10nm process. The foundry vendor did disclose it would offer several new technology platforms. Besides planar bulk and finFETs, the company is moving to offer FD-SOI.  In July, GlobalFoundries agreed to manufacture STMicroelectronics’ FD-SOI technology in both the 28nm and 20nm nodes. The SOI substrates are supplied by Soitec.

As part of its technology offerings, GlobalFoundries plans to offer two versions of FD-SOI: minimum and maximum. The maximum version is a technology tuned for a specific application. IBM and STMicroelectronics are examples of companies that would utilize maximum versions of FD-SOI. Meanwhile, the minimum version is a simple and an “out of the box” FD-SOI technology, said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries.

In addition, GlobalFoundries also plans to offer SSWR, a doping technology. “You add a ground plane below the channel,”  Kengeri said. The technology is a 20nm planar process at 28nm costs. For years, several companies have been working on the technology to solve a major issue. A phenomenon called random dopant fluctuation (RDF) causes more than 70% of all random variations at 65nm and the problems are getting worse at each node.

To solve RDF and other problems, one company, SuVolta, recently rolled out a new transistor option that extends conventional bulk CMOS technology. SuVolta’s Deeply Depleted Channel (DDC) technology works by forming a deeply depleted channel when a voltage is applied to the gate.

In the distant future, GlobalFoundries is also looking at 450mm. It is part of the recently-announced Global 450 Consortium. The G450C group includes five IC manufacturers, with IBM and GlobalFoundries joining the original “International Sematech” members, Intel, Samsung, and TSMC. Those companies, along with Sematech and the SUNY-Albany College of Nanoscale Science and Engineering (CNSE), will sit on the board of directors that will govern the consortium.

The G450C demonstration line in Albany is targeted for 14nm design rules in early 2013. “Do I want to be the first one (on 450mm)? No. Do I want to be the last? No. I would like to be behind the first,” Manocha added.

By Mark LaPedus

In response to its foundry rivals, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has updated and accelerated its process roadmap. The world’s largest silicon foundry has accelerated its 16nm finFET efforts by one quarter and added a 10nm finFET technology to the roadmap.

TSMC also plans to take the “modular fin” approach for its 16nm finFET. It is also looking at 450mm fabs at the 10nm node, according to a TSMC executive, who also stressed that collaboration is a key to success. Customers must collaborate earlier in the design cycle and “at a new level,” said Mark Liu, executive vice president and co-chief operating officer at TSMC, during a keynote at the company’s Open Innovation Platform Ecosystem Forum in San Jose, Calif. on Tuesday (Oct. 16). “We need to align strategically.”

At present, TSMC is ramping up its 28nm process technology. The next process on the roadmap, dubbed CLN20, is a 20nm planar technology. The reference flow for CLN20 is ready and the process is due out in 2013.

Then, as previously announced, TSMC will enter the finFET transistor era. The company’s initial finFET process, dubbed CLN16FF, is being targeted and branded for the 16nm node. TSMC’s 16nm finFET process is slated for risk production in November of 2013, Liu said. Risk production has been accelerated from February of 2014 to November of 2013.

In an interview after the keynote, Liu said TSMC will take a “modular fin” approach in finFETs. TSMC will marry a 16nm fin with a 20nm backend. “It has 20nm design rules,” he said.

TSMC will also implement a triple-patterning strategy for 16nm finFETs. The company is also keeping its options open. It is exploring 193nm immersion extensions, extreme ultraviolet (EUV) lithography and multi-beam. “At this point, we have both (193nm extensions and EUV) under development,” he said. “Maybe multi-beam will save the day.”

TSMC’s 16nm finFET design solutions, including the EDA tools and IP, will be ready by the first quarter of 2013.  “We have pulled in our design enablement solutions,” said Cliff Hou, senior vice president of TSMC, during a separate keynote at the event. The first version of the design solutions, dubbed V0.1, is slated for introduction in January. The second version, V1.0, is due out in October of 2013.

Meanwhile, during his keynote, Liu presented a slide that denoted CLN10FF, which is a second-generation finFET for the 10nm node.  TSMC’s 10nm finFET process is expected to move into risk production “close to the end of 2015,” he said.

Also at 10nm, TSMC is looking to enter the 450mm fab era. It is likely TSMC will have a 450mm fab or pilot line in the second phase of 10nm. “There are no show stoppers,” he said. “All of the equipment companies are developing 450mm.”

Other foundries have also accelerated their finFET roadmaps. For example, GlobalFoundries Inc. recently rolled out its finFET technology for the 14nm node. GlobalFoundries is taking a “modular fin” approach with its bulk finFET offering, dubbed 14nm-XM. The 14nm-XM combines a 14nm-class fin with its 20nm back-end-of-line (BEOL) interconnect flow.

By taking the modular approach, the company has accelerated its process roadmap by a year. Early process design kits (PDKs) are available, with customer product tape-outs expected in 2013. Production, which is slated for 2014, will take place within GlobalFoundries’ new 300mm fab in New York.

Another foundry vendor, United Microelectronics Corp. (UMC), is taking a similar modular finFET approach. UMC licensed finFET technology from IBM. Samsung Electronics Co. Ltd. has yet to elaborate on its finFET strategy.  Meanwhile, Intel Corp. is already ramping up its 22nm process, which is based on finFET transistors. Intel is providing foundry services for select customers, who plan to ship products based on finFETs.

By Mark LaPedus

IC makers have been looking at the electric vehicle industry for growth. So whatever happened to the electric car? Toyota has scaled back the sales targets for its electric car. According to Lux Research, the head of Toyota’s vehicle development gave a vote of no confidence for the technology, by saying the “capabilities of electric vehicles do not meet society’s needs.” Meanwhile, Tesla Motors recently lowered its sales targets. Another car maker, Nissan, is offering big discounts on the Leaf because of slow sales. GM’s Chevy Volt has struggled to win customers, even though it’s not purely electric. And Fisker Automotive, which uses the same approach as Chevy, has experienced an assortment of problems.

At the 2012 IEEE International Electron Devices Meeting (IEDM), slated for Dec. 10-12 in San Francisco, Applied Materials and Synopsys are expected to submit a paper entitled, “Is strain engineering scalable in FinFET era? Teaching the old dog some new tricks.” “Strain technology has been a key enabler for improving transistor performance in the past decade. With the industry moving toward a 3-D FinFET structure from a planar MOSFET, the corresponding implications on stressor design needs to be analyzed afresh due to strong orientation dependence of stress enhancements,” according to the IEDM abstract from the companies. “In this work we have tried to address both issues; stressor design for FinFETs and scalability of corresponding stress enhancements. We found that the S/D epi remains an effective and scalable source of strain engineering for FinFETs. Contact and gate metals provide new knobs for engineering strain in FinFETs and remain effective with conservative scaling of contact/gate CD.”

Altatech, a subsidiary of Soitec, has introduced a multi-chamber chemical vapor deposition (CVD) system that enables photovoltaic (PV) cell manufacturers to develop and optimize their solar cell designs using advanced thin-film deposition of amorphous silicon and other materials. By performing all deposition processes within a single system, the new AltaCVD Solarlab tool reduces cycle times and materials consumption in fabricating advanced single-junction, tandem-junction and triple-junction PV cells.

GlobalFoundries is preparing to build a three-story, 565,000-square-foot manufacturing research center, according to a report.

While over-capacity continues to plague the global solar industry, the Taiwan PV industry is operating at high-capacity, according to SEMI.

SVTC Technologies is struggling and has apparently cut workers, according to reports, which added that the R&D foundry is mulling plans to close its sites in Austin, Texas and San Jose.  Multiple sources say SVTC may completely shut down. In an e-mail, SVTC declined to comment on the reports. A spokesman for Oak Hill Capital declined to comment. Oak Hill is an investor in SVTC. In 2007, Cypress sold its R&D fab unit to Oak Hill and Tallwood Venture for approximately $53 million. SVTC became a “lab-to-fab” facility aimed at third-party engineering groups.

As it turns out, Tezzaron Semiconductor has signed a contract to purchase the assets of a semiconductor technology development and wafer fabrication facility in Austin, Texas, previously run by SVTC. Tezzaron will continue the operations of this facility while adding capabilities to assemble its own 3D devices.

Struggling Renesas has obtained a $6 billion bailout from various banks. The chipmaker announced the execution of an agreement of a syndicate loan, with Mizuho, The Bank of Tokyo-Mitsubishi UFJ, Sumitomo Mitsui Trust Bank and Mitsubishi UFJ Trust and Banking Corporation.

Sharp has obtained a syndicated loan as it struggles to find investors.

For its 2012 fiscal year, Micron reported a net loss of $1.03 billion. C.J. Muse, an analyst with Barclays, said: “While Micron was hesitant to provide any speculative commentary around the potential Elpida acquisition, management did note that the deal is expected to close in [the first half of calendar year 2013].”

The JEDEC Solid State Technology Association has announced the initial publication of its Synchronous DDR4 standard.

Intel and its OEM partners unveiled the first wave of new tablets and tablet convertible designs based on Intel processors, including the new Atom Z2760, formerly codenamed “Clover Trail.”

Samsung’s foundry business has been selected by STMicroelectronics to provide it with products at the 32/28nm process node.

X-Fab plans to invest more than $50 million in its MEMS operations over the next three years.

Diodes plans to acquire Power Analog Microelectronics.

Gartner says Windows 8 is a big gamble Microsoft must make to stay relevant.

IC Insights believes that the more profitable foundries will be those that keep at the leading-edge of the process technology roadmap.

The average amount of DRAM in each smartphone shipped worldwide is expected to surge by nearly 50 percent this year, according to iSuppli.

By Mark LaPedus
The 14nm node represents an inflection point for leading-edge foundries.

The foundries hope to make a monumental shift from conventional planar transistors at 20nm to finFET structures at 14nm. And to accelerate their finFET efforts, leading-edge foundries are looking at hybrid integration schemes and “modular fin” strategies.

Using this approach, a foundry would devise a fin structure at the front-end with 14nm design rules. The fin structure itself is modular, meaning it can be plugged into a newly developed and corresponding 14nm back-end-of-line (BEOL) interconnect flow.

But by being modular, vendors also have the option to plug in the 14nm fin into an existing planar 20nm BEOL flow. This hybrid integration approach could enable a vendor to accelerate its finFET introduction date, but there are also some die-cost disadvantages.

“There are no challenges from a process point of view,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “What you are doing is taking a fin module and making it compatible at 14nm and 20nm.”

By going the modular fin route, foundries hope to provide fast and flexible solutions for customers. “It has to be competitive,” he said. Foundries appear to be taking a “modular fin” approach for good reason: They must speed up their finFET efforts to play catch up with Intel and satisfy increasing customer demand for the technology.

Challenges mount at 14nm
The foundries face some challenges to integrate “modular fins,” not to mention bringing up finFET structures in the first place. At 14nm, there are other manufacturing challenges, such as etch, deposition, inspection and lithography. The net result is that there must be a closer collaboration between foundries and customers. “The key is to have a tighter integration between product design and manufacturing,” Kengeri said.

Clearly, the leader in finFETs is Intel Corp., which is already using the technology for its microprocessors at 22nm. At that node, Intel is also providing foundry services to a limited set of fabless chip makers.

Right now, the foundries are still ramping up their 28nm processes, with planar at 20nm and finFETs at 14nm in the works. At 14nm, the industry is not banking on extreme ultraviolet (EUV) lithography. The EUV power source is simply not ready.

Instead, the industry is gearing up for 193nm immersion and multi-patterning. “If EUV was ready today, people would use it,” said David Hemker, chief technology officer in the corporate technology development group at Lam Research. “The industry is confident using double pattering.”

Beside lithography, there is another pressing issue for finFETs: variability. Intel proved that a chipmaker could ramp up finFETs using bulk CMOS technology. Attempting to follow Intel’s successful formula, the foundries have decided to extend bulk CMOS into the finFET era.

But because of fin height variability, there are fears that the foundries could struggle making bulk finFETs. “People are just waking up to this,” said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. The foundries should take a harder look at silicon-on-insulator (SOI) technology, which can reduce fin height variability, Patton said. And because there are fewer process steps with SOI-based finFETs, the traditional cost penalty associated with SOI disappears, he added.

The finFET transition also will cause a spike for process-control tools. Given the soaring costs of IC designs, there is little margin for error. It will become more critical to spot killer defects much earlier in the process.

One of the emerging areas in process control involves non-visual defects. Non-visual defects do not scatter light and are not detectable by current optical or e-beam inspection tools. “Up to 30% of yield loss in today’s fabs are not traceable to physical defects,” said Robert Newcomb, executive vice president at Qcept Technologies, a metrology tool vendor.

Non-visual defects are cropping up in some new and unforeseen areas in finFET designs. In development work for one customer, for example, Qcept’s tools detected horizontal defect patterns in the outer 20nm to 30nm of the wafer in a finFET design.

Get out the scorecards
And if that isn’t enough, chipmakers will need a scorecard just to keep track of the foundries and their latest finFET roadmaps. The nodes at which vendors will introduce finFETs are a bit misleading and don’t necessarily tell which company is ahead in the race.

For example, United Microelectronics Corp. (UMC) is rolling out finFETs at 20nm. UMC is marrying a 14nm front-end fin with a 20nm backend. Rival Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is talking about finFETs at the 16nm half-node. So far, Samsung is sticking to its plans to launch finFETs at 14nm.

GlobalFoundries, meanwhile, has devised a modular fin with 14nm front-end design rules, but it has not decided whether it will insert the structure to a 14nm or 20nm BEOL scheme. “We’ve been analyzing to see what is the right approach,” Kengeri said. “We may put it on 20nm. We may put it at 14nm. We may put it on both.”

In all cases, chipmakers still are able to devise new and innovative IC designs with finFETs. “To achieve this, there are many aspects of finFET technology,” he said. “Optimization and upfront planning are key. The ratio of contacted poly pitch, metal layers and fin pitch are critical. The choice of fin pitch will impact fin efficiency, resistance-capacitance, cost, process complexity, scalability and many other metrics. Therefore, it is important to architect the finFET process with a fin pitch optimal for both 20nm and 14nm and targeted for specific applications.”

Still, the modular fin strategy has some tradeoffs. The first option is to combine a 14nm front-end modular fin to a corresponding middle-of-the-line (MEOL) and BEOL flow at 14nm. The fin structure can be easily manufactured using 193nm immersion, multi-pattering and other steps.

The real challenge is to devise an entire new MEOL and BEOL infrastructure at 14nm, which could be an expensive proposition. Chip manufacturers could extend their existing physical vapor deposition (PVD) tools to devise the interconnect at 14nm. But for the capping layers, chipmakers may need to move to new deposition tools as well as materials like cobalt, said Sree Kesapragada, global product manager for metal deposition products at Applied Materials.

Until foundries bring up a new 14nm MEOL/BEOL flow, they may opt to go with the less expensive hybrid approach. This marries a 14nm fin with a 20nm planar MEOL/BEOL flow. The idea behind this approach is that foundries can leverage and use their existing and mature 20nm tools.

There are also some time-to-market and tool cost-of-ownership advantages with the hybrid approach. “There are some pros and cons,” Kengeri said. “You can bring up the technology faster.”

The disadvantage is that the die cost is roughly similar between a 20nm planar device and a hybrid 14nm/20nm finFET. “You don’t get the die cost advantage” of a homogenous 14nm finFET structure, he said. There also could be some integration challenges in terms of the different capacitances between the 14nm front-end fin and the 20nm planar BEOL. “It’s something you have to account for and model,” he said.

By Mark LaPedus
As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model.

Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the foundries are not only manufacturing partners, but there is a deeper collaboration within a customer’s design team.

In fact, given the variability challenges with finFETs, there is a school of thought that chipmakers must reside at the same physical location as their foundry partners’ fabs to ensure that design and manufacturing are on the same page. Otherwise, according to some experts, the chances for first-silicon success are shaky.

For this reason and others, Taiwan Semiconductor Manufacturing Co. (TSMC) may take the “virtual IDM” model a step further. TSMC is considering a plan to build separate fabs for individual companies. And as part of its strategy, TSMC has accelerated its finFET roadmap.

Rival GlobalFoundries is considering a plan to offer dedicated modules within a fab for customers. And taking another approach, United Microelectronics Corp. has floated an equity placement under which companies can buy a 10% stake in UMC. UMC also has licensed IBM’s 20nm and finFET technologies.

Another foundry vendor, Samsung Electronics Co, has perhaps set the tone for the industry: It has already built a dedicated fab for Apple. And separately, in a surprise move, fabless chipmaker Qualcomm is considering the idea of building its own fab to gain better control of the manufacturing process.

Qualcomm CEO “Paul Jacobs has discussed it openly of late,” said G. Dan Hutcheson, president of VLSI Research. “Qualcomm certainly has the revenues to build its own fab and start making its own wafers. The chance of success is still low. It would cost at least three times, and possibly as much as five times, to successfully get your first fab to viable production, or approximately $15 billion to $25 billion. In other words, it would be an out-of-body experience for the management team that tries it.”

Sea of change
In any case, there could be a sea of change taking place in the traditional fabless-foundry model. “The traditional foundry model, where you throw a GDS2 file over the wall, no longer works,” said Mojy Chian, senior vice president of design enablement at GlobalFoundries. “We have to work closer with the fabless guys. New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the time-to-market. In fact, the collaboration should start two to two-and-a-half years ahead of tape out.”

In the late 1980s, the pure-play foundries emerged, which spawned a plethora of fabless companies. One of the drawbacks with the fabless-foundry model is that the design houses and foundries sometimes work in silos and do not cooperate. In some cases, fabless vendors will throw a clunky design “over the wall” to the foundries, which are still expected to make the chip on time. This brute-force methodology has experienced mixed success.

The fabless and foundry firms began to change their ways at the 130nm node amid soaring IC design and manufacturing costs. “130nm is when process and design began to be recoupled. The result was the rise of DFM, which didn’t exist before then,” said VLSI’s Hutcheson.

Then, starting in the early part of this decade, several foundries billed themselves as “virtual IDMs,” claiming they would work more closely with customers. But some of those efforts have fallen short of expectations. “The leading fabless suppliers got hurt badly when the leading foundries hadn’t dealt well with variability at 40nm, and more recently, with design-manufacturing interactive yield losses at 28nm,” Hutcheson said.

Now, as the IC industry moves toward the 20nm node and beyond, the foundries have become more serious about embracing the “virtual IDM” model and for good reason: The stakes are higher. At 130nm, a fab was $1.45 billion, process R&D costs were $250 million, and design costs were $15 million. But at 22nm, a fab runs $6.7 billion, process R&D is $1.3 billion, and design costs are $150 million.

Simply put, the traditional foundry model must evolve. “You can’t do it in silos,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “The key is to have a tighter integration between product design and manufacturing.”

This is especially true in the finFET era. Intel has moved finFETs into production at 22nm. Given the variability issues, the foundries face challenges to put finFETs into production at 14nm.

Intel and the foundries are in the bulk finFET camp. But to make the finFET transition easier, the foundries should look at silicon-on-insulator (SOI) technology, said Chenming Calvin Hu, professor of electrical engineering at the University of California at Berkeley. “We are going to see (both bulk and SOI finFETs) in volume manufacturing,” Hu said. “[SOI] is easier. The supply chain is the one thing that manufacturers need to be assured of.”

New business models
On the business side, the industry could take one of two routes: Maintain the fabless-foundry status quo or move toward a “virtual IDM” model. Morris Chang, chairman and chief executive of TSMC, sees yet another model: Build dedicated fabs or joint-venture fabs for larger customers.

“We made our mark serving many customers (in multiple fabs). We will retain that capability,” Chang said during a recent conference call. “There are going to be larger customers. So it makes complete sense to have one dedicated fab, or more than one fab, for one customer.”

GlobalFoundries, meanwhile, is considering a slightly different model. “This is hypothetical,” said GlobalFoundries’ Kengeri. “Within a fab, we have modules. If one of our customers wants a dedicated module, it’s open for discussion.”

In that arrangement, a chipmaker may have to share the risk and cost. And it must make economic sense. Clearly, though, Apple is one candidate for a dedicated fab. In fact, Samsung already has built a dedicated fab for Apple in Austin, Texas.

Altera, Broadcom, Nvidia, Qualcomm and Xilinx are also possible candidates to occupy part or all of a fab. Qualcomm, for one, has the volumes and already is sourcing parts from all of the leading-edge foundries to keep up with 28nm demand.

Qualcomm’s multi-foundry sourcing strategy “is a very expensive approach today, as designs don’t port to multiple foundries like they used to,” said VLSI’s Hutcheson. “Yields are far more difficult to obtain at these advanced nodes, and splitting production across multiple fabs means either less relevant data per learning cycle or longer learning cycle times. That results in longer time-to-money and higher costs, making going the IDM route seem more attractive.”

It’s unlikely that Qualcomm will build its own fab, but it is possible it will end up with a joint venture fab with a foundry. In addition, Qualcomm and others would like the foundries to speed up their process roadmaps. The foundries are falling behind Intel, which also offers foundry services on a limited basis.

TSMC, for one, plans to accelerate its finFET efforts. Originally, TSMC planned to introduce finFETs at 14nm by late 2014. Now, the company has no plans to brand its finFETs at 14nm, but rather it will introduce the technology at 16nm. TSMC’s finFET “risk production” is slated for the end of 2013 or early 2014, with production scheduled for the second half of 2015, Chang said.

TSMC is not banking on extreme ultraviolet (EUV) lithography for 16nm. “We are very confident we can make 16nm finFETs without EUV,” he said. “I think EUV will come in at 10nm.”

To accelerate 450mm fabs and EUV in the market, Intel recently inked a deal with ASML. ASML has also enabled customers to take a 25% stake in the company. Intel plans to acquire up to a 15% stake in ASML.

TSMC and Samsung are also negotiating with ASML to take separate stakes in ASML. Taking a page from the ASML-Intel deal, UMC separately floated private equity shares under which strategic partners can take up to a 10% stake in UMC.

This represents a change for UMC. The company has developed its own processes and has shied away from forming strategic alliances. UMC has controlled its own destiny, but it also has fallen behind its rivals.

To jumpstart its process roadmap, UMC recently licensed 20nm and finFET technology from IBM. UMC’s finFET technology is reportedly a 14nm or 16nm front-end, with 20nm backend. “For UMC to do a finFET from scratch is very challenging,” said Shih-Wei Sun, chief executive of UMC, in a recent conference call. “This will kick start our finFET efforts.”

GlobalFoundries and Samsung have yet to change their finFET strategies. GlobalFoundries still plans to roll out a finFET at the 14nm node in the fourth quarter of 2014 or first quarter of 2015, according to Kengeri.

Soitec (Bernin, France) has joined Sematech’s front end processes (FEP) and advanced metrology programs, located at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany.

Sematech and Soitec plan to develop dimensional and films metrology on Soitec’s SOI wafers as part of a wider collaboration aimed at extending CMOS and high-mobility FinFET technologies. The effort will include advanced metrology, materials, process technology, and device characterization.

The partnership aims to foster the development of advanced processes and devices, based on Soitec’s silicon-on-insulator (SOI) wafers and other engineered substrates. The collaboration also will focus on applying Sematech’s metrology expertise towards extending current transistor designs.

Soitec and Sematech are working to extend SOI technology. (Source: Symposium on VLSI Technology).

Christophe Maleville, senior vice president of Soitec’s Microelectronics Business Unit, said, “Due to their expertise in advanced CMOS and FinFET transistor modules, Sematech was a natural choice to partner with in developing advanced metrology techniques and device characterization for mobility performance.”

Raj Jammy, Sematech’s vice president of emerging technologies, said, “Soitec’s expertise in substrate fabrication methodology will complement our own device and process expertise, as well as enable us to offer our experience in developing leading-edge metrology capabilities to characterize these advanced devices and evaluate critical defects. We will work together to develop practical and promising high-mobility non-planar and metrology approaches to speed the transition of these new innovations to mainstream semiconductor production.”

Sematech’s FEP program is exploring new materials and transistor structures, and alternative non-volatile memories. Sematech’s Advanced Metrology program seeks to identify key gaps in measurement technology for advanced devices and to develop solutions to meet the needs of the sub-20 nm technology node and beyond.

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) held a groundbreaking ceremony in Taichung’s Central Taiwan Science Park for Phase 3 of its Fab 15 GigaFab.

Fab 15, Phase 3 will be TSMC’s second GigaFab equipped for 20nm process technology. The first 300mm GigaFab, Fab 12 module 5, is located in Hsinchu.

Capacity for the Fab 15 Phase 3 is 40,000 300mm wafers per month. In the future, TSMC will make 450mm wafers as well as finFETs at 14nm in Fab 15.

TSMC began construction on Fab 15, Phase 1, in July 2010, and completed equipment move-in in mid-2011 with volume production scheduled for early 2012.

At the same time, Fab 15, Phase 2 started construction in mid-2011 and is expected to begin volume production next year. Fab 15 Phases 1 and 2 are forecast to generate as much as $3 billion in revenue per year once they enter volume production, and Phase 3 will also reach a similar scale in the future. Fab 15 currently employs approximately 1,400 employees.

Billed as a “green” fab, Fab 15, Phase 3 applies numerous pollution prevention and energy conservation methods, including classification of process wastewater into 25 categories, an effective process water recycling rate of 90 percent, water use reduction of 62 percent, and 5 percent less power consumption than earlier facilities.

In addition, Fab 15, Phase 3 has a rainwater collection surface of 40,000 square meters, and all collected rainwater is used in landscaping, consuming no water from public utilities. In addition, TSMC aims to create a benchmark in high-quality green buildings with treatment effectiveness of cleanroom exhaust reaching as high as 98 percent.

TSMC Chairman Morris Chang said: “Fab 15, Phase 3 plays an important role in our plans for advanced technology development and capacity expansion.”

TSMC also announced its net sales for November 2011. On an unconsolidated basis, net sales were approximately NT$35.22 billion, a decrease of 5.4 percent over October 2011 and a decrease of 1.4 percent over November 2010. Revenues for January through November 2011 totaled NT$387.68 billion, an increase of 3.9 percent compared to the same period in 2010.