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Posts Tagged ‘EUV’

Blog review February 10, 2014

Monday, February 10th, 2014

Dick James of ChipWorks blogs that when Intel launched their Haswell series chips last June, they stated that the high-end systems would have embedded DRAM, as a separate chip in the package. “It took us a while to track down a couple of laptops with the requisite Haswell version, but we did and now we have a few images that show it’s a very different structure from the other e-DRAMs that we’ve seen,” he notes.

Phil Garrou continues his look at the 2013 Georgia Tech Interposer Conference, focusing on presentations from Amkor and GlobalFoundries. He writes that Ron Huemoeller of Amkor projects that in the high end silicon will dominate; in the mid-end, silicon will be prominent and organic /glass may play a role; in the low end, organic, or low cost glass or silicon if they exist will play a role. Dave McCann of GlobalFoundries examined market needs for interposers.

Semico’s review of the latest and greatest from the Consumer Electronics Show highlights five technologies they think you should pay attention to as game changers: 3D Printing, the Bosch wireless sensor network for IoT; Bionics: Thought-controlled prosthetics; Aging in place: Pain relief; and LED Lighting.

Vivek Bakshi, of EUV Litho, Inc., ponders some interesting questions, such as how important is the semiconductor industry relative to other industries, and how did we get to where we are, the continuation of Moore’s Law and why have there been so few Nobel prizes given to the chip industry?

Karen Lightman of the MEMS Industry Group says the upcoming MEMS Executive Congress Europe “checks all the boxes” with great content and speakers, networking time with MEMS industry execs and OEM users, and an unbeatable location in Munich.

Pete Singer takes a look back at February 1964 through the pages of Solid State Technology, when wafers were small, dreams were big and The Beatles were on the Ed Sullivan show. The issue discussed thermionic energy convertors, the potential of which is still being explored today by Stanford.

Blog Review November 11, 2013

Monday, November 11th, 2013

Karen Savala of SEMI notes that the semiconductor industry is uncharted waters without the benefit of a GPS system. She says mega-mergers, massive supply chain investments by manufacturers and governments, new consortia and collaboration models are changing the rules for everyone in the ecosystem. Pervasive Computing, the theme of this blog post, is also the theme for the upcoming Industry Strategy Symposium (ISS), to be held January 12-14, 2014 in Half Moon Bay, California.

In Karen Lightman’s MEMS Industry Group blog, she turns the reins over to Silex Microsystem’s Peter Himes, vice president marketing & strategic alliances. Peter reflects on MEMS and while other might lament at the conundrum of the uniqueness of all MEMS process, Peter instead sees opportunity. In this example he describes Silex’s partnership with A.M. Fitzgerald and Associates and their Rocket MEMS program.

Phil Garrou covers several topics related to 3D integration in this week’s blog: A new report from Yole on flip chip (FC) technology, ASE’s report ASE – Board Level Reliability of Bump on Polymer (BoP) WLCSPs, and chip embedding at IMS.

Should the lifetime of EUV optics be a concern? Upon hearing about how EUV sources contaminate the optics inside the tool, Pete Singer blogs that there still must be lots of questions about the ultimate cost of ownership and how that will compare to double and triple patterning approaches with 193nm immersion.

Are we using Moore’s name in vain? That question is posed by Zvi Or-Bach, President & CEO of MonolithIC 3D in his blog post, where he notes that dimensional scaling was not an integral part of Moore’s assertion in 1965 – cost was. But dimensional scaling became the “law of the land” and, just like other laws, the industry seems fully committed to follow it even when it does not make sense anymore, he writes.

The Solid State Technology 2014 Editorial Calendar is out, blogs Pete Singer, noting the editorial mission remains that same: we’re dedicated to covering mainstream semiconductor manufacturing technology, with a strong focus on transistors, interconnects and packaging. We also cover other types of advanced electronics, including MEMs, LEDs, displays, bioelectronics, photonics and power electronics.

Blog Review November 5 2013

Tuesday, November 5th, 2013

New blogs delve into the packaging technology of Apple’s A7, the road ahead for bulk FinFETs as defined by imec, with EUV is a gating factor for 450mm, split-manufacturing for U.S. trusted IC (TIC) program and Japan’s growing market for equipment and materials.

For the 10nm node and beyond, transistor research efforts are focused on high mobility designs with Ge and III-V channel, reducing VDD supply voltage as well as the subthreshold slope in transistors and optimizing multi-Vt designs. Pete Singer reports on work underway at imec in Belgium.

At the IEEE 3DIC in San Francisco Dan Radack of the Institute of Defense Analysis gave an update on the IARPA trusted Integrated Chip Program. Phil Garrou reports how it is now focused on split-manufacturing with FEOL done off-shore and BEOL done by trusted facilities in the U.S.

The A7 is manufactured by Samsung on a high-κ metal gate (HKMG) 28 nm process and the chip includes over 1 billion transistors on a die 102 mm2 in size. Phil Garrou reports on observations on the Package-on-Package (PoP) design as noted by fellow blogger Dick James. In an earlier blog, Dick described how the Apple A7 is using Samsung’s 28nm process.

Simon Favre of Mentor Graphics notes how EUV could possibly be a gating factor for 450mm. “Would you put in 450mm immersion steppers, and then yank them out to put in EUV before they’re fully depreciated?” he asks.

In advance of Semicon Japan, to be hold December 4-6 at the Makuhari Messe, SEMI’s Dan Tracy and Yoichiro Ando report that restructuring and consolidation has led to a new focus for the semiconductor manufacturers in Japan. As a result, the semiconductor equipment market in Japan will experience double-digit growth in both 2013 and 2014, driven by higher spending for memory production and in spending increases planned for the manufacturing of power semiconductors and “More than Moore” semiconductor technologies. Total equipment spending in Japan is estimated to reach $4.6 billion by 2014. Combining this with the $8 billion-plus spending on semiconductor materials, Japan represents a $12 billion market in 2014 for the suppliers of equipment and materials.

Research Bits: Oct. 22, 2013

Tuesday, October 22nd, 2013

Size matters in the giant magnetoresistance effect in semiconductors

Professors at Georgia State University reported that a giant magnetoresistance effect depends on the physical size of the device in the GaAs/AlGaAs semiconductor system.

In research that is supported by grants from the U.S. Department of Energy and the U.S. Army Research Office, Dr. Ramesh Mani, professor of physics and astronomy, studied the magnetoresistance in flat, very thin sheets of electrons in the ultra high quality GaAs/AlGaAs semiconductor with his colleagues Annika Kriisa from Emory University and Werner Wegscheider from the ETH-Zurich in Switzerland.

The researchers found that the change in the resistance or resistivity with the magnetic field depends on the size of the device. They demonstrated that, under the application of a magnetic field, wide devices develop a smaller and quicker change, while small devices develop a bigger but slower change in the resistivity. The resistance or resistivity of a material to the flow of electricity is a technologically important property, especially in semiconductors.

This research team developed a model to understand the observations and deduced that when the semiconductor system becomes of even better quality, the change in the resistance under the application of a magnetic field will become even bigger. Indeed, the change might become so big that the resistance vanishes entirely in the small magnetic field.

Thin film semiconductors that will drive production of next-generation displays

Researchers at the National Institute for Materials Science have developed a pixel switching semiconductor, which will be the key to driving next-generation displays, by using an oxide film with a new elemental composition.

When an oxide film contains metal with low bond dissociation energy, the thin film absorbs or desorbs oxygen easily and the conductivity of the film changes. For example, zinc has very low bond dissociation energy, so a thin film using zinc absorbs or desorbs oxygen easily when heated or cooled. This finding suggests that the manufacturing conditions for oxide semiconductors can be controlled by focusing on the bond dissociation energy. In fact, the research team confirmed that film deposition conditions can be broadened by adding silicon oxide with high bond dissociation energy to indium oxide. We also confirmed stabilization of thin-film conductivity in post-deposition heat treatment.

The research results are expected to be effective not only for reducing the power consumption of displays which consume about half of the power in rapidly diffusing smartphones, but also for achieving higher frequencies to realize higher-definition TVs. Additionally, the thin film developed in this research contributes to conserving precious resources by not using zinc, which is a trace element of concern, or high-cost gallium which is used in large quantities for galvanized steel sheets or as a rubber vulcanizing agent, while it also enables the manufacture of flat panel displays not affected by wild fluctuations in raw material prices.

Ultraviolet light to the extreme

When you heat a tiny droplet of liquid tin with a laser, plasma forms on the surface of the droplet and produces extreme ultraviolet (EUV) light, which has a higher frequency and greater energy than normal ultraviolet.Now, for the first time, researchers have mapped this EUV emission and developed a theoretical model that explains how the emission depends on the three-dimensional shape of the plasma. In doing so, they found a previously untapped source of EUV light, which could be useful for various applications including semiconductor lithography, the process used to make integrated circuits.

In the experiments, Andrea Giovannini and Reza Abhari from ETH-Zurich in Switzerland blasted a 30-micron-diameter droplet of tin with a high-powered laser 6,000 times a second. They measured the spatial distribution of the resulting EUV emission and found that 30 percent of it came from behind the region of the droplet that was struck by the laser. According to their model, this unexpected distribution was due to the fact that the plasma partially surrounding the droplet was elongated in the direction of the laser pulse.

Devices that produce narrow beams of EUV for purposes like in semiconductor lithography use mirrors to focus the emission. But, until now, no one knew to collect the EUV light radiating from behind the droplet.

Key Trends at Semicon West 2013

Saturday, July 27th, 2013

By Pete Singer

At Semicon West last week (and at The ConFab a few weeks ago) some key trends were clearly evident in the semiconductor industry.

It’s apparent that the world’s appetite for electronics has never been greater. That has increasingly taken the form of mobile electronics, including smartphones, tablets and tablets and the new “phablets.” People want to watch movies and live sports on their phones. They want their mobile devices to be “situationally aware” and even capable of monitoring their health through sensors. That drives higher bandwidth (6G is on the drawing board), faster data rates and a demand for reduced power consumption to conserve battery life. At the same time, “big data” and the internet of things (IoT) are here, which drives the demand for server networks and high performance semiconductors, as well as integrated sensors and inventive gadgets such as flexible displays and human biosensor networks.

It’s also pushing the semiconductor manufacturing industry in new directions. Chip makers typically face tradeoffs between power, performance, area and cost/complexity (PPAC). For mobile devices, the push is to low power, high performance, small area and low cost.

For me, one of the main themes of Semicon West was the demand for mobile devices and how they might impact what has become standard thinking in the semiconductor industry in terms of scaling, performance, power and cost.

At Semicon West 2013, Karen Savala, president of SEMI Americas, kicked things off, noting that it was the 43rd year of Semicon West (32nd consecutive one for me personally). “While much has changed over the years, the one that has been constant is the power of our industry to continually drive innovation, to overcome technical challenges and economic challenges, and develop new processes, new materials and technologies that continue to move Moore’s Law forward,” Savala said. “2013 is no different. The industry finds itself at a critical juncture where multiple technology developments, including 450mm, FinFETs, 3D ICs, advanced materials and processes, and EUV just to name a few, promise to move Moore’s Law ahead. But as we have done before, we will address these challenges, bring new technologies to market, and continue to amaze the world with the power of our collective innovation.”

Karen then introducde the keynote, Ajit Monacha, CEO of Global Foundries, who expanded on his Foundry 2.0 concept, and talked about how the requirements of mobile devices were, in fact, changing the entire semiconductor industry. He noted that the mobile business is forecast to be double the size of the PC market in 2016. The mobile business drives many new requirements, said Manocha, including power, performance and features, higher data rates, high resolution multicore processors and thinner form factors.

This incredible growth is driving new dynamics, said Manocha, and pushing the industry to the new technology node each year, which is presenting the industry with what Manocha deems the Big Five Challenges. Manocha believes these challenges are: cost, device architectures, lithography and EUV, packaging and the 450mm wafer transition. I don’t recall when cost wasn’t an issue, but an audience poll revealed that most people believe economic challenges will be the main factor limiting industry growth, not technical challenges, so cost moves to the top of the list.

After his talk, Ajit was presented with the “SEMI Outstanding EHS Achievement Award — Inspired by Akira Inoue” by Denny McGuirk, president and CEO of SEMI. During Semicon West, SEMI also honored 14 industry leaders for their outstanding accomplishments in developing standards for the microelectronics and related industries

Part of “the buzz” at the show was the rosy prediction issued by SEMI about growth in capital equipment for next year. SEMI forecasts semiconductor equipment sales will reach $43.98 billion in 2014, a 21 percent increase over estimated 2013 equipment spending, according to the mid-year edition of the SEMI Capital Equipment Forecast, released during the show.

EUV Flare And Proximity Modeling And Model-Based Correction

Thursday, May 16th, 2013

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. This paper focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based.

To view this white paper, click here.

EUV OPC For 56nm Metal Pitch

Thursday, October 18th, 2012

For the logic generations of the 15 nm node and beyond, the printing of pitches at 64nm and below are needed. For EUV lithography to replace ArF-based multi-exposure techniques, it is required to print these patterns in a single exposure process. The k1 factor is roughly 0.6 for 64nm pitch at an NA of 0.25, and k1  0.52 for 56nm pitch. These k1 numbers are of the same order at which model based OPC was introduced in KrF and ArF lithography a decade or so earlier. While we have done earlier work that used model-based OPC for the 22nm node test devices using EUV,1 we used a simple threshold model without further resist model calibration. For 64 nm pitch at an NA of 0.25, the OPC becomes more important, and at 56nm pitch it becomes critical. For 15 nm node lithography, we resort to a full resist model calibration using tools that were adapted from conventional optical lithography. We use a straight shrink 22 nm test layout to assess post-OPC printability.

To read more, click here.