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EUV Resists and Stochastic Processes

Friday, March 4th, 2016

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By Ed Korczynski, Sr. Technical Editor

In an exclusive interview with Solid State Technology during SPIE-AL this year, imec Advanced Patterning Department Director Greg McIntyre said, “The big encouraging thing at the conference is the progress on EUV.” The event included a plenary presentation by TSMC Nanopatterning Technology Infrastructure Division Director and SPIE Fellow Anthony Yen on “EUV Lithography: From the Very Beginning to the Eve of Manufacturing.” TSMC is currently learning about EUVL using 10nm- and 7nm-node device test structures, with plans to deploy it for high volume manufacturing (HVM) of contact holes at the 5nm node. Intel researchers confirm that they plan to use EUVL in HVM for the 7nm node.

Recent improvements in EUV source technology— 80W source power had been shown by the end of 2014, 185W by the end of 2015, and 200W has now been shown by ASML—have been enabled by multiple laser pulses tuned to the best produce plasma from tin droplets. TSMC reports that 518 wafers per day were processed by their ASML EUV stepper, and the tool was available ~70% of the time. TSMC shows that a single EUVL process can create 46nm pitch lines/spaces using a complex 2D mask, as is needed for patterning the metal2 layer within multilevel on-chip interconnects.

To improve throughput in HVM, the resist sensitivity to the 13.54nm wavelength radiation of EUV needs to be improved, while the line-width roughness (LWR) specification must be held to low single-digit nm. With a 250W source and 25 mJ/cm2 resist sensitivity an EUV stepper should be able to process ~100 wafer-per-hour (wph), which should allow for affordable use when matched with other lithography technologies.

Researchers from Inpria—the company working on metal-oxide-based EUVL resists—looked at the absorption efficiencies of different resists, and found that the absorption of the metal oxide based resists was ≈ 4 to 5 times higher than that of the Chemically-Amplified Resist (CAR). The Figure shows that higher absorption allows for the use of proportionally thinner resist, which mitigates the issue of line collapse. Resist as thin as 18nm has been patterned over a 70nm thin Spin-On Carbon (SOC) layer without the need for another Bottom Anti-Reflective Coating (BARC). Inpria today can supply 26 mJ/cm2 resist that creates 4.6nm LWR over 140nm Depth of Focus (DoF).

To prevent pattern collapse, the thickness of resist is reduced proportionally to the minimum half-pitch (HP) of lines/spaces. (Source: JSR Micro)

JEIDEC researchers presented their summary of the trade-off between sensitivity and LWR for metal-oxide-based EUV resists:  ultra high sensitivity of 7 mJ/cm2 to pattern 17nm lines with 5.6nm LWR, or low sensitivity of 33 mJ/cm2 to pattern 23nm lines with 3.8nm LWR.

In a keynote presentation, Seong-Sue Kim of Samsung Electronics stated that, “Resist pattern defectivity remains the biggest issue. Metal-oxide resist development needs to be expedited.” The challenge is that defectivity at the nanometer-scale derives from “stochastics,” which means random processes that are not fully predictable.

Stochastics of Nanopatterning

Anna Lio, from Intel’s Portland Technology Development group, stated that the challenges of controlling resist stochastics, “could be the deal breaker.” Intel ran a 7-month test of vias made using EUVL, and found that via critical dimensions (CD), edge-placement-error (EPE), and chain resistances all showed good results compared to 193i. However, there are inherent control issues due to the random nature of phenomena involved in resist patterning:  incident “photons”, absorption, freed electrons, acid generation, acid quenching, protection groups, development processes, etc.

Stochastics for novel chemistries can only be controlled by understanding in detail the sources of variability. From first-principles, EUV resist reactions are not photon-chemistry, but are really radiation-chemistry with many different radiation paths and electrons which can be generated. If every via in an advanced logic IC must work then the failure rate must be on the order of 1 part-per-trillion (ppt), and stochastic variability from non-homogeneous chemistries must be eliminated.

Consider that for a CAR designed for 15mJ/cm2 sensitivity, there will be just:

145 photons/nm2 for 193, and

10 photons/nm2 for EUV.

To improve sensitivity and suppress failures from photon shot-noise, we need to increase resist absorption, and also re-consider chemical amplification mechanisms. “The requirements will be the same for any resist and any chemistry,” reminded Lio. “We need to evaluate all resists at the same exposure levels and at the same rules, and look at different features to show stochastics like in the tails of distributions. Resolution is important but stochastics will rule our world at the dimensions we’re dealing with.”

—E.K.

Many Mixes to Match Litho Apps

Thursday, March 3rd, 2016

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By Ed Korczynski, Sr. Technical Editor

“Mix and Match” has long been a mantra for lithographers in the deep-sub-wavelength era of IC device manufacturing. In general, forming patterns with resolution at minimum pitch as small as 1/4 the wavelength of light can be done using off-axis illumination (OAI) through reticle enhancement techniques (RET) on masks, using optical proximity correction (OPC) perhaps derived from inverse lithography technology (ILT). Lithographers can form 40-45nm wide lines and spaces at the same half-pitch using 193nm light (from ArF lasers) in a single exposure.

Figure 1 shows that application-specific tri-layer photoresists are used to reach the minimum resolution of 193nm-immersion (193i) steppers in a single exposure. Tighter half-pitch features can be created using all manner of multi-patterning processes, including Litho-Etch-Litho-Etch (LELE or LE2) using two masks for a single layer or Self-Aligned Double Patterning (SADP) using sidewall spacers to accomplish pitch-splitting. SADP has been used in high volume manufacturing (HVM) of logic and memory ICs for many years now, and Self-Aligned Quadruple Patterning (SAQP) has been used in HVM by at least one leading memory fab.

Fig.1: Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

Next-Generation Lithography (NGL) generally refers to any post-optical technology with at least some unique niche patterning capability of interest to IC fabs:  Extreme Ultra-Violet (EUV), Directed Self-Assembly (DSA), and Nano-Imprint Lithography (NIL). Though proponents of each NGL have dutifully shown capabilities for targeted mask layers for logic or memory, the capabilities of ArF dry and immersion (ArFi) scanners to process >250 wafers/hour with high uptime dominates the economics of HVM lithography.

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

It is looking most likely that the answer is “all of the above.” EUV and NIL could be used for single layers. For other unique patterning application, ArF/ArFi steppers will be used to create a basic grid/template which will be cut/trimmed using one of the available NGL. Each mask layer in an advanced fab will need application-specific patterning integration, and one of the rare commonalities between all integrated litho modules is the overwhelming need to improve pattern overlay performance.

Naga Chandrasekaran, Micron Corp. vice president of Process R&D, provided a fantastic overview of the patterning requirements for advanced memory chips in a presentation during Nikon’s LithoVision technical symposium held February 21st in San Jose, California prior to the start of SPIE-AL. While resolution improvements are always desired, in the mix-and-match era the greatest challenges involve pattern overlay issues. “In high volume manufacturing, every nanometer variation translates into yield loss, so what is the best overlay that we can deliver as a holistic solution not just considering stepper resolution?” asks Chandrasekaran. “We should talk about cost per nanometer overlay improvement.”

Extreme Ultra-Violet (EUV)

As touted by ASML at SPIE-AL, the brightness and stability and availability of tin-plasma EUV sources continues to improve to 200W in the lab “for one hour, with full dose control,” according to Michael Lercel, ASML’s director of strategic marketing. ASML’s new TWINSCAN NXE:3350B EUVL scanners are now being shipped with 125W power sources, and Intel and Samsung Electronics reported run their EUV power sources at 80W over extended periods.

During Nikon’s LithoVision event, Mark Phillips, Intel Fellow and Director of Lithography Technology Development for Logic, summarized recent progress of EUVL technology:  ~500 wafers-per-day is now standard, and ~1000 wafer-per-day can sometimes happen. However, since grids can be made with ArFi for 1/3 the cost of EUVL even assuming best productivity for the latter, ArFi multi-patterning will continue to be used for most layers. “Resolution is not the only challenge,” reminded Phillips. “Total edge-placement-error in patterning is the biggest challenge to device scaling, and this limit comes before the device physics limit.”

Directed Self-Assembly (DSA)

DSA seems most suited for patterning the periodic 2D arrays used in memory chips such as DRAMs. “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node” was the title of a presentation at SPIE-AL by researchers from Coventor, in which DSA compared favorably to SAQP.

Imec presented electrical results of DSA-formed vias, providing insight on DSA processing variations altering device results. In an exclusive interview with Solid State Technology and SemiMD, imec’s Advanced Patterning Department Director Greg McIntyre reminds us that DSA could save one mask in the patterning of vias which can all be combined into doublets/triplets, since two masks would otherwise be needed to use 193i to do LELE for such a via array. “There have been a lot of patterning tricks developed over the last few years to be able to reduce variability another few nanometers. So all sorts of self-alignments.”

While DSA can be used for shrinking vias that are not doubled/tripled, there are commercially proven spin-on shrink materials that cost much less to use as shown by Kaveri Jain and Scott Light from Micron in their SPIE-AL presentation, “Fundamental characterization of shrink techniques on negative-tone development based dense contact holes.” Chemical shrink processes primarily require control over times, temperatures, and ambients inside a litho track tool to be able repeatably shrink contact hole diameters by 15-25 nm.

Nano-Imprint Litho (NIL)

For advanced IC fab applications, the many different options for NIL technology have been narrowed to just one for IC HVM. The step-and-pattern technology that had been developed and trademarked as “Jet and Flash Imprint Lithography” or “J-FIL” by, has been commercialized for HVM by Canon NanoTechnologies, formerly known as Molecular Imprints. Canon shows improvements in the NIL mask-replication process, since each production mask will need to be replicated from a written master. To use NIL in HVM, mask image placement errors from replication will have to be reduced to ~1nm., while the currently available replication tool is reportedly capable of 2-3nm (3 sigma).

Figure 2 shows normalized costs modeled to produce 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. Key to throughput is fast filling of the 26mmx33mm mold nano-cavities by the liquid resist, and proper jetting of resist drops over a thin adhesion layer enables filling times less than 1 second.

Fig.2: Relative estimated costs to pattern 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

Researchers from Toshiba and SK Hynix described evaluation results of a long-run defect test of NIL using the Canon FPA-1100 NZ2 pilot production tool, capable of 10 wafers per hour and 8nm overlay, in a presentation at SPIE-AL titled, “NIL defect performance toward high-volume mass production.” The team categorized defects that must be minimized into fundamentally different categories—template, non-filling, separation-related, and pattern collapse—and determined parallel paths to defect reduction to allow for using NIL in HVM of memory chips with <20nm half-pitch features.

—E.K.

What’s the Next-Gen Litho Tech? Maybe All of Them

Thursday, February 25th, 2016

By Jeff Dorsch, Contributing Editor

The annual SPIE Advanced Lithography symposium in San Jose, Calif., hasn’t offered a clear winner in the next-generation lithography race. It’s becoming clearer, however, that 193i immersion and extreme-ultraviolet lithography will co-exist in the future, while directed self-assembly, nanoimprint lithography, and maybe even electron-beam direct-write technology will fit into the picture, too.

At the same time, plasma deposition and etching processes are assuming a greater interdependence with 193i, especially when it comes to multiple patterning, such as self-aligned double patterning, self-aligned quadruple patterning, and self-aligned octuple patterning (yes, there is such a thing!).

“We’ve got to go down to the sub-nanometer level,” Richard Gottscho, Lam Research’s executive vice president of global products, said Monday morning in his plenary presentation at the conference. “We must reduce the variability in multiple patterning,” he added.

Gottscho touted the benefits of atomic level processing in continuing to shrink IC dimensions. Atomic level deposition has been in volume production for a decade or more, he noted, and atomic level etching is emerging as an increasingly useful technology.

When it comes to EUV, “it’s a matter of when, not if,” the Lam executive commented. “EUV will be complementary with 193i.”

Anthony Yen, director of nanopatterning technology in the Infrastructure Division of Taiwan Semiconductor Manufacturing, followed Gottscho in the plenary session. “The fat lady hasn’t sung yet, but she’s on the stage,” he said of EUV.

Harry Levinson, senior director of GlobalFoundries, gave the opening plenary presentation, with the topic of “Evolution in the Concentration of Activities in Lithography.” He was asked after his presentation, “When is the end?” Levinson replied, “We’re definitely not going to get sub-atomic.”

With that limit in mind, dozens of papers were presented this week on what may happen before the semiconductor industry hits the sub-atomic wall.

There were seven conferences within the symposium, on specific subjects, along with a day of classes, an interactive poster session, and a two-day exhibition.

The Alternative Lithographic Technologies conference was heavy on directed self-assembly and nanoimprint lithography papers, while also offering glimpses at patterning with tilted ion implantation and multiphoton laser ablation lithography.

“Patterning is the battleground,” said David Fried, Coventor’s chief technology officer, semiconductor, in an interview at the SPIE conference. He described directed self-assembly as “an enabler for optical lithography.”

Mattan Kamon of Coventor presented a paper on Wednesday afternoon on “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node.”

DSA could be used in conjunction with SAQP or LELELELE, according to Fried. While some lithography experts remain leery or skeptical about using DSA in high-volume manufacturing, the Coventor CTO is a proponent of the technology’s potential.

“Unit process models in DSA are not far-fetched,” he said. “I think they’re pretty close.  The challenges of EUV are well understood. DSA challenges are a little less clear. There’s no ‘one solution fits all’ with DSA.” Fried added, “There are places where DSA can still win.”

Franklin Kalk, executive vice president of technology for Toppan Photomasks, is open to the idea of DSA and imprint lithography joining EUV and immersion in the lithography mix. “It will be some combination,” he said in an interview, while adding, “It’s a dog’s breakfast of technologies. Don’t ever count anything out.”

Richard Wise, Lam’s technical managing director in the company’s Patterning, Global Products Groups CTO Office, said EUV, when ready, will likely be complementary with multipatterning for 7 nanometer.

Self-aligning quadruple patterning, for example, was once considered “insanity” in the industry, yet it is a proven production technology now, he said.

While EUV technology is “very focused on one company,” ASML Holding, there is a consensus at SPIE that EUV’s moment is at hand, Wise said. Intel’s endorsement of the technology and dedication to advancing it speaks volumes of EUV’s potential, he asserted.

“Lam’s always excelled in lot-to-lot control,” an area of significant concern, Wise said, especially with all of this week’s talk about process variability.

What will be the final verdict on the future of lithography technology? Stay tuned.

ASML Details Advances in DUV, Metrology, EUV

Thursday, February 25th, 2016

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By Jeff Dorsch, Contributing Editor

ASML Holding is glad to talk about its continuing progress in extreme-ultraviolet lithography technology. But first, the company has some information about its deep-ultraviolet scanners, as well.

ASML continues to ship its TWINSCAN NXT: 1980Di immersion lithography systems, which are capable of processing 275 wafers per hour, according to Michael Lercel, ASML’s director of strategic marketing.

Since shipments began last year, the 1980Di is exhibiting overlay numbers that are “slightly better than expected,” Lercel said Wednesday at the SPIE Advanced Lithography conference in San Jose, Calif. ASML aimed to make the 193i litho system “ a little bit more robust” than its predecessor, the TWINSCAN NXT: 1970Ci, he added. The 1970Ci can be upgraded in the field to the 1980Di’s capabilities, according to the company.

The 1980Di can be utilized in a combination of lithography techniques, including single exposure, lithography-etch-lithography-etch, sidewall spacers, and self-aligned double patterning, Lercel said. It offers the kind of variability control needed for self-aligned quadruple patterning, he added.

The ASML executive also addressed the company’s new YieldStar 350E metrology system, which he said can “correct for overlay errors” and “apply corrections to upstream and downstream problems,” using “a lot of overlay data.”

On the EUV front, Lercel said ASML has made “a lot of progress in the last 12 to 18 months.” At its facilities in Veldhoven, the Netherlands, the company has been able to operate a power source for its EUV systems at 200 watts “for one hour, with full dose control,” he noted.

That’s approaching its high-volume manufacturing target of 250W, according to Lercel. ASML continues to predict its EUV scanners will move into volume production applications in the 2018-19 timeframe, he said.

Intel and Samsung Electronics this week reported running their EUV power sources at 80W over extended periods.

The new TWINSCAN NXE:3350B scanners are now being shipped with 125W power sources, Lercel noted. ASML has demonstrated 80 percent availability in the field, including scheduled downturns, bringing EUV close to matching immersion lithography, Lercel said. Regarding availability, “we need to do better in consistency,” he acknowledged.

ASML has “multiple EUV systems at multiple customers,” Lercel said. In addition to Intel and Samsung, the company’s EUV scanners are also being used at GlobalFoundries, SK Hynix, and Taiwan Semiconductor Manufacturing, among others not yet identified by the equipment vendor.

ASML this week reported reaching a deal with Nippon Control System on integrating optical proximity correction to mask data preparation on a common platform.

Laser Suppliers Move Past the Neon Gas Crisis

Wednesday, February 24th, 2016

By Jeff Dorsch, Contributing Editor

That neon gas shortage? So 2015.

The supply issue continues, as armed conflict heats up in eastern Ukraine, site of a plant that supplies a majority of the neon gas used in the world. Cymer and Gigaphoton, the big suppliers of excimer lasers for lithography that use neon as a buffer gas, have worked around the shortage, including the recycling of gas exhaust from their lasers.

“Prices have somewhat stabilized,” said Joe Ganeshan, sales manager for Gigaphoton USA. “We’re still in a crisis.”

Pricing for neon gas last year rose by 10 to 20 times, according to Ted Cacouris, product marketing director at the Cymer subsidiary of ASML Holding. One gas supplier in Ukraine was behind more than half of the world’s supply, and transporting the gas out of the conflict zone became haphazard, he noted.

The spike in neon gas prices peaked in 2015’s late summer and early fall, Cacouris said. As semiconductor manufacturers adjusted to the shortage, “prices started rolling over,” he added.

Cymer and Gigaphoton both implemented recycling programs in response to the supply situation, dramatically reducing neon gas consumption for their customers. Ganeshan estimated his company’s customers saved around $90 million a year as a result, while Cacouris put the figure at about $200 million.

In addition to reducing neon-gas consumption, Gigaphoton is moving to eliminate the use of helium in chipmaking, citing the U.S. government’s plans to cut off supply of the unrenewable gas in the near future. Used as a purging gas in argon fluoride 193i immersion lithography scanners, helium will be replaced with nitrogen, Ganeshan said.

Putting the neon-gas crisis in the rearview mirror, Cymer and Gigaphoton are turning to other pressing issues as suppliers of the light sources used in immersion and extreme-ultraviolet lithography systems.

Gigaphoton claimed to have improved its market share in excimer lasers for semiconductor manufacturing to 60 percent or more in 2015.

Cymer’s Cacouris cast doubt on that figure, without disclosing his company’s market share last year. Japan-based Gigaphoton greatly benefited from the exchange rate on the yen, gaining a 20 percent pricing advantage as a result, he asserted.

He described Gigaphoton’s claim as “a bit optimistic,” adding, “They’ve had some progress; they’ve had a few wins.” Cacouris vowed, “We’re going to do a lot better this year.”

Before the SPIE Advanced Lithography conference in San Jose, Calif., Gigaphoton announced that it is establishing new support bases in Dalian and Xiamen, China. The company also said it has received supplier awards from United Microelectronics and Taiwan Semiconductor Manufacturing.

Canon, Toshiba Join eBeam Initiative Group

Wednesday, February 24th, 2016

By Jeff Dorsch, Contributing Editor

The eBeam Initiative announced that Canon and Toshiba are new members of the industry organization, which seeks to promote the use of electron-beam technology in semiconductor manufacturing and design.

Canon Nanotechnologies and Toshiba are closely collaborating on the development of nanoimprint lithography technology. Both companies presented papers on Tuesday morning at the SPIE Advanced Lithography conference in the session devoted to “Nanoimprint Lithography Production Readiness.”

The eBeam Initiative additionally announced that it will expand its education efforts in 2016 to support the development of extreme-ultraviolet lithography, multi-beam mask writing, and nanoimprint lithography, all of which employ e-beam techniques in producing photomasks, or master templates in the case of NIL.

“People believe multi-beam is going to happen,” said Aki Fujimura, chief executive officer of D2S, the managing company sponsor of the e-beam group. He cited the group’s annual survey of industry figures, who last year predicted multi-beam mask-writing tools would be used in high-volume manufacturing for critical-layer photomasks by the end of 2018. This industry acknowledgement of advances in multi-beam mask writing “gives confidence,” Fujimura said at the eBeam Initiative’s annual luncheon at the SPIE Advanced Lithography symposium.

More than 100 luncheon attendees heard presentations by representatives of Dai Nippon Printing, the photomask manufacturer; imec, the research and development organization based in Belgium; and NuFlare Technology, a supplier of e-beam mask writers, mask inspection systems, and epitaxial reactors.

Naoya Hayoshi of DNP reported on the basics of NIL, which he said faces “some challenges, as in mask making.”

Praveen Raghavan of imec spoke about the organization’s development of test chips with 5-nanometer features. One was made with self-aligned quadruple patterning, using a 193i immersion scanner, while the other was fabricated with an EUV scanner.

The EUV technology offers “significant wafer cost benefit and enables 2D BEOL,” Raghavan said.

NuFlare’s Hiroshi Matsumoto spoke about the company’s forthcoming MBM-1000 multi-beam mask-writing system, an alpha version of which is currently in operation at the NuFlare facilities in Yokohama, Japan. NuFlare plans to offer a HVM version of the MBM-1000 by the end of this year, he said, with delivery in the fourth quarter of 2017.

The MBM-1000 is targeted at production of 5nm chips, while its successor, the MBM-2000, will address fabrication of 3nm ICs, according to Matsumoto. The MBM-2000 will be released in 2019, he said.

ASML Has Record Revenue for 2015; Will Raise Dividend, Buy Back More Stock

Wednesday, January 20th, 2016

By Jeff Dorsch, Contributing Editor

ASML Holding today reported net income of about $1.5 billion on revenue of $6.855 billion for 2015. That compared with 2014’s net income of $1.3 billion on revenue of $6.385 billion.

In the fourth quarter, the company posted net income of $318.3 million on revenue of $1.563 billion. Those figures were lower than the third quarter.

ASML said it sold 144 new lithography systems last year, up from 116 in 2014. It also sold 25 used systems, against 20 units a year earlier.

The 2015 sales represented a record for the supplier of advanced lithography equipment. ASML forecast sales for 2016’s first quarter would exceed $1.4 billion.

The company said it would raise its annual dividend to shareholders by 50 percent, to 1.05 euros per share, and will spend an additional $1.09 billion in 2016-2017 repurchasing its shares.

“As we indicated three months ago, we expect our logic customers to take shipments of our leading-edge immersion tools in the second quarter in preparation of their 10-nanometer node ramp. As a result, we expect second-quarter sales to increase significantly from the first-quarter level,” ASML President and Chief Executive Officer Peter Wennink said in a statement.

ASML stated that its extreme-ultraviolet lithography line “met its 2015 productivity and availability targets. We had already achieved a productivity of more than 1,000 wafers per day early in 2015 on the NXE:3300B system and improved this to more than 1,250 wafers per day in the fourth quarter on the successor system, the NXE:3350B. In addition, the availability of systems in the field improved, with the majority of systems achieving a four-week availability of more than 70 percent in recent months; the best result was more than 80 percent over four weeks. We also shipped two of our latest NXE:3350B EUV systems and started shipping the third in 2015. They will be used in our customers’ fabs for preparing the introduction of EUV into volume production. Our goals for 2016 are to continue improving productivity and availability and shipping six to seven EUV systems.”

Regarding deep-ultraviolet lithography systems, “we began ramping shipments of the TWINSCAN NXT:1980, our most advanced immersion system, in the fourth quarter, shipping five systems. The installation of the first systems is complete,” ASML stated.

Holistic lithography “grew by over 20 percent in revenue in 2015; we saw increased adoption of our latest metrology systems and control software at both logic and memory customers. These applications play a more and more critical role in helping our customers achieve the best possible patterning performance on advanced nodes,” the company added.

“The first-quarter outlook disappoints,” SNS Securities analyst Edwin de Jong told Bloomberg News. “It is good that you return cash to shareholders, but you need to improve operationally.”

Neon Gas Supply Issues Dog the Semiconductor Industry

Thursday, August 20th, 2015

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By Jeff Dorsch, Contributing Editor

The armed conflict in Ukraine, where most of the world’s supply of neon gas for semiconductor manufacturing and other industrial applications is produced, is leading lithography equipment vendors to offer ways to reduce use of neon, which is utilized as a buffer gas for argon fluoride and krypton fluoride gases employed in lasers for chip production.

While a shaky cease-fire has been observed in Ukraine since February, combat has restricted factory activity there in the past year.

Cymer and Gigaphoton, the two leading suppliers of laser light sources for advanced lithography, last month announced measures intended to address the limited supply of neon gas.

The situation has escalated to a neon gas supply shortage, according to Joe Ganeshan, sales manager for Gigaphoton USA. “Seventy-five percent of production comes from Ukraine,” he said. “Prices are going up drastically.”

“Chipmakers are concerned about recent escalation of neon prices and supply continuity,” David Knowles, vice president and general manager of Cymer Light Source, said in a statement. “We have worked in close cooperation with our customers on an aggressive program to develop, qualify, and introduce improvements for the installed base of ArF and KrF light sources that enable significant reductions in neon consumption while ensuring system performance.”

Risto Puhakka, president of VLSI Research, agrees that the neon gas shortage represents “a critical situation” for the semiconductor industry, which is the world’s leading consumer of neon gas. The chip business is “a materials-heavy industry,” he says. Similar crises emerged in recent years with rare earths and helium, he notes.

“It’s part of this business,” Puhakka observes. “Some materials are quite exotic.”

Commodity supply issues naturally result in higher pricing, according to Puhakka. “When the price is right, they’ll find more of it,” he adds.

Puhakka speculates that “shrewd chipmakers” were cognizant of the neon supply issue as it unfolded. “They understand the risks in the supply chain,” he says. While supply chain management is a constant concern for semiconductor manufacturers, they still have to deal with supply shortages and rising prices. “At the end of the day, they don’t have a choice,” Puhakka concludes.

Gigaphoton made a move last November, offering its eTGM technology on a free-of-charge, limited basis for new and existing GT series ArF immersion lasers. Last month, Gigaphoton stepped up its efforts with what it called the Neon Gas Rescue Program. Among other measures, the company is helping customers qualify gas suppliers on an accelerated basis and pushing up implementation of its hTGM gas recycling technology to 2016.

Cymer last month said it is helping with qualifying gas suppliers, while providing software for its installed base of light sources to reduce neon consumption. The company is aiding customers through its OnPulse support program, which brought out a helium reduction kit earlier this year.

Technologies for Advanced Systems Shown at IMEC Tech Forum USA

Tuesday, July 14th, 2015

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By Ed Korczynski, Sr. Technical Editor

Luc Van den hove, president and CEO, imec opened the Imec Technology Forum – USA in San Francisco on July 13 by reminding us of the grand vision and motivation behind the work of our industry to empower individuals with micro- and nano-technologies in his talk, “From the happy few to the happy many.” While the imec consortium continues to lead the world in pure materials engineering and device exploration, they now work on systems-integration complexities with over 100 applications partners from agriculture, energy, healthcare, and transportation industries.

We are now living in an era where new chip technologies require trade-offs between power, performance, and bandwidth, and such trade-offs must be carefully explored for different applications spaces such as cloud clusters or sensor nodes. An Steegen, senior vice president process technology, imec, discussed the details of new CMOS chip extensions as well as post-CMOS device possibilities for different applications spaces in her presentation on “Technology innovation: an IoT era.” EUV lithography technology continues to be developed, targeting a single-exposure using 0.33 Numerical Aperture (NA) reflective lenses to pattern features as small as 18nm half-pitch, which would meet the Metal1 density specifications for the industry’s so-called “7nm node.” Patterning below 12nm half-pitch would seem to need higher-NA which is not an automatic extension of current EUV technology.

So while there is now some clarity regarding the pre-competitive process-technologies that will be needed to fabricate next-generation device, there is less clarity regarding which new device structures will best serve the needs of different electronics applications. CMOS finFETs using strained silicon-doped-with-Germanium Si(Ge) will eventually be replaced by gate-all-around (GAA) nano-wires (NW) using alternate-channel materials (ACM) with higher mobilities such as Ge and indium-gallium-arsenide (InGaAs). While many measures of CMOS performance improve with scaling to smaller dimensions, eventually leakage current and parasitic capacitances will impede further progress.

Figure 1 shows a summary of energy-vs.-delay analyses by imec for all manner of devices which could be used as switches in logic arrays. Spin-wave devices such as spin-transfer-torque RAM (STT-RAM) can run at low power consumption but are inherently slower than CMOS devices. Tunnel-FET (TFET) devices can be as fast or faster than CMOS while running at lower operating power due to reduced electrostatics, leading to promising R&D work.

Fig.1: Energy vs. delay for various logic switches. (Source: imec)

In an exclusive interview, Steegen explained how the consortium balances the needs of all partners in R&D, “When you try to predict future roadmaps you prefer to start from the mainstream. Trying to find the mainstream, so that customers can build derivatives from that, is what imec does. We’re getting closer to systems, and systems are reaching down to technology,” said Steegen. “We reach out to each other, while we continue to be experts in our own domains. If I’m inserting future memory into servers, the system architecture needs to change so we need to talk to the systems people. It’s a natural trend that has evolved.”

Network effects from “the cloud” and from future smart IoT nets require high-bandwidth and so improved electrical and optical connections at multiple levels are being explored at imec. Joris Van Campenhout, program director optical I/O, imec, discussed “Scaling the cloud using silicon photonics.” The challenge is how to build a 100Gb/s bandwidth in the near term, and then scale to 400G and then 1.6T though parallelism of wavelength division multiplexing; the best results to date for a transmitter and receiver reach 50Gb/s. By leveraging the existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon photonics platform enables high integration density and reduced power consumption, as well as high yield and low manufacturing cost. Supported by EDA tools including those from Mentor Graphics, there have been 7 tape-outs of devices in the last year using a Process Design Kit (PDK). When combined with laser sources and a 40nm node foundry CMOS chip, a complete integrated solution exists. Arrays of 50Gb/s structures can allow for 400Gb/s solutions by next year, and optical backplanes for server farms in another few years. However, to bring photonics closer to the chip in an optical interposer will require radical new new approaches to reduce costs, including integration of more efficient laser arrays.

Alexander Mityashin, project manager thin film electronics, imec, explained why we need, “thin film electronics for smart applications.” There are billions of items in our world that could be made smarter with electronics, provided we can use additive thin-film processes to make ultra-low-cost thin-film transistors (TFT) that fit different market demands. Using amorphous indium-gallium-zinc-oxide (a-IGZO) deposited at low-temperature as the active layer on a plastic substrate, imec has been able to produce >10k TFTs/cm2 using just 4-5 lithography masks. Figure 2 shows these TFT integrated into a near-field communications (NFC) chip as first disclosed at ISSCC earlier this year in the paper, “IGZO thin-film transistor based flexible NFC tags powered by commercial USB reader device at 13.56MHz.” Working with Panasonic in 2013, imec showed a flexible organic light-emitting diode (OLED) display of just 0.15mm thickness that can be processed at 180°C. In collaboration with the Holst Center, they have worked on disposable flexible sensors that can adhere to human skin.

Fig.2: Thin-Film Transistors (TFT) fabricated on plastic using Flat Panel Display (FPD) manufacturing tools. (Source: imec/Holst Center)

Jim O’Neill, Chief Technology Officer of Entegris, expanded on the systems-level theme of the forum in his presentation on “Putting the pieces together – Materials innovation in a disruptive environment.” With so many additional materials being integrated into new device structures, there are inherently new yield-limiting defect mechanisms that will have to be controlled. With demand for chips now being driven primarily by high-volume consumer applications, the time between first commercial sample and HVM has compressed such that greater coordination is needed between device, equipment, and materials companies. For example, instead of developing a wet chemical formulation on a tool and then optimizing it with the right filter or dispense technology, the Process Engineer can start envisioning a “bottle-to-nozzle wetted surface solution.” By considering not just the intended reactions on the wafer but the unintended reactions that can occur up-steam and down-stream of the process chamber, full solutions to the semiconductor industry’s most challenging yield problems can be more quickly found.

—E.K.

SPIE Advanced Lithography conference concludes

Friday, February 27th, 2015

By Jeff Dorsch, contributing editor

Exposures, and reducing their cost, were a theme running through the 2015 SPIE Advanced Lithography Symposium this week in San Jose, Calif., the center of Silicon Valley.

Doubts about the continued viability of Moore’s Law abound as the 50th anniversary of Gordon Moore’s historic article for Electronics magazine draws near. Lithographers are under immense industry pressure to lower the operating costs of lithography cells in the fab while increasing wafer throughput.

“Enabling,” “productivity,” and “stability” were watchwords frequently repeated throughout the conference. The various merits (and occasional demerits) of electron-beam, extreme-ultraviolet, 193i immersion and nanoimprint lithography technologies were debated and touted over four days.

One of the technical sessions closing out Wednesday at the San Jose Convention Center was devoted to papers on “Multibeam Lithography,” especially e-beam direct-write technology, which has been seen as “pie in the sky” for many years, yet seems closer to realization than before.

Hans Loeschner of IMS Nanofabrication described how his company’s e-beam tool has progressed from alpha to beta status this year, and predicted it would be ready for production applications in 2016. Altera, CEA-Leti, and MAPPER Lithography presented a total of three papers on MAPPER’s FLX-1200 e-beam direct-write system, saying it is better able to make chips with 20-nanometer features than an immersion lithography system.

The eBeam Initiative held its annual luncheon at SPIE Advanced Lithography on Tuesday, emphasizing how multibeam mask writing, model-based mask data preparation, and complex inverse lithography technology can enable continued density scaling at the 10-nanometer process node.

“We have reached a point with traditional rules-based designs where the rules are so conservative and the implementation costs are so high that the semiconductor industry has started to lose the economic benefits of scaling to smaller design nodes for system-on-chip designs,” D2S CEO Aki Fujimura said in a statement. “A simulation-based approach combining complex ILT, MB-MDP and existing variable shaped beam mask writers in parallel with the impending emergence of multibeam mask writing are providing platforms to enable the semiconductor industry to reverse this trend and reactivate the density benefits associated with Moore’s Law.”

EUV, another technology that has had a long gestation, was the subject of a conference track over all four days, with photomask and photoresist issues being discussed in several sessions.

The news that Taiwan Semiconductor Manufacturing was able to process 1,022 wafers in 24 hours with ASML Holding’s NXE:3300B scanner was the talk of the SPIE conference on Tuesday, the first day of the two-day exhibition, which had about 60 companies occupying booths. ASML didn’t declare an end to development of its EUV systems, saying there is more work to be done. This includes development of a pellicle for the scanner’s reticles and working with resist suppliers on formulas for EUV resists.

While improvements in all types of lithographies were discussed at the conference, there was increased interest in directed self-assembly, which employs polymers to get molecules to arrange themselves in lines and spaces with a patterning guide. Advances in reducing the defectivity of DSA were reported by imec, Merck, and Tokyo Electron.

Global interest in DSA over the past four years has accelerated due to “other things getting delayed,” said Tom Ferry of Synopsys. Among other initiatives, the electronic design automation software and services company was talking about how its S-Litho molecular simulator, S-Litho shape optimizer, and Proteus ILT guide patterning tool can help enable DSA research and development, design, and manufacturing.

The Belgium-based imec was a big contributor to conference presentations, with a first author on 18 papers and posters, and a co-author of 25 publications.

While EUV garnered headlines during SPIE Advanced Lithography, the Cymer subsidiary of ASML was at the conference to talk about its third-generation XLR 700ix light source for deep-ultraviolet lithography systems. Ted Cacouris of Cymer said, “10 nanometer is basically done with DUV. It could go to 7 nanometer; immersion could be extended. It could be complementary to EUV.”

Cymer also announced its DynaPulse program, an upgrade for its OnPulse subscription service for maintenance and repair of light sources. In 2012, prior to the company’s acquisition by ASML, Cymer derived nearly 70 percent of its light-source revenue from the OnPulse service program.

It’s been an interesting week, with about 2,400 attendees from around the world gathering for the premier lithography conference of the year. They will convene again a year from now to learn what’s new in lithography.

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