Part of the  

Solid State Technology

  Network

About  |  Contact

Posts Tagged ‘EUV’

Next Page »

Blog review August 18, 2014

Monday, August 18th, 2014

Vivek Bakshi provides a deeper look at the ASML/IBM announcement on EUV progress. ASML and IBM reconfirmed the benchmarking in press and via social media. In short, 637 wafers per day throughput stands, resulting from the successful upgrade of source power by 100%, to its targeted level of ~43 W.

Dick James of Chipworks finally has his hands on Samsung’s V-NAND vertical flash. The vertical flash was first released in an enterprise solid-state drive (SSD) last year, in 960 GB and 480 GB versions. Then in May this year they announced a second-generation V-NAND SSD, with a stack of 32 cell layers.

Phil Garrou provides an overview of controlling warpage in packaging as discussed at ECTC by Hitachi Chemical, Amkor, Qualcomm, and imec.

Anand Sundaram, Senior Associate for PwC’s PRTM Management Consulting writes that software that controls and powers embedded devices is playing a key role in making possible the highly integrated, multi-functional ‘smart’ devices we take for granted in our daily lives – from the ubiquitous smart phones/tablet to ‘smart’ home appliances and wearable electronics.

Pete Singer posted an IoT infographic, courtesy of Jabil. The global IoT market is poised for explosive growth. By 2020, the market is expected to soar to $7.1 trillion. This infographic, courtesy of Jabil, gives an good overview of what will be connected (even garbage bins!).

Bob Smith, Senior Vice President of Marketing and Business Development, Uniquify blogs that these days, chip design may seem like an intricately connected jigsaw puzzle, including small, oddly shaped interlocking pieces.

Solid State Watch: July 31-August 7, 2014

Friday, August 8th, 2014
YouTube Preview Image

Blog review August 4, 2014

Monday, August 4th, 2014

Innovation is alive and well in the semiconductor industry. That was a key takeaway from the strategic investor panel at the second annual Silicon Innovation Forum at SEMICON West, and one I can’t reinforce enough within the venture capital (VC) community. Eileen Tanghal of Applied Materials reports.

At SEMICON West this year in Thursday morning’s Yield Breakfast sponsored by Entegris, top executives from Qualcomm, GlobalFoundries, and Applied Materials discussed the challenges to achieving profitable fab yield for atomic-scale devices. In his blog, Ed Korzynski reports on what was discussed.

Phil Garrou blogs that Apple has acquired 24 tech companies in the last 18 months. Recently, Apple acquired LuxVue, a start-up focused on low power micro-LED displays. Although Apple has not disclosed any details of the acquisition, not even the purchase price, one can easily envision where micro LED displays could play a big part in Apples thrust into wearable electronics such as the i-watch, Phil says.

Adele Hars continued a report on the SOI papers at the VLSI Symposia in this Part 2 installment. The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry.

Vivek Bakshi created a EUV stir, blogging about IBM’s NXE3300B scanner, at the EUV Center of Excellence in Albany, which recently completed a “40W” EUV light source upgrade.  The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.

The Week in Review: August 1, 2014

Friday, August 1st, 2014

Semiconductors providing wireless connectivity in health and fitness devices are set for solid double-digit growth in 2014 and beyond, especially as a clutch of wireless technologies make their way into a growing number of wearable devices, according to a new report from IHS Technology.

This week, IBM reported that its NXE3300B scanner, at the EUV Center of Excellence in Albany, recently completed a 40 Watt EUV light source upgrade.  The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.  In the first 24 hours of operation after the upgrade six hundred thirty seven wafer exposures were completed in normal production lot mode. Vivek Bakshi of EUV Litho, Inc. said that this is a watershed moment for EUV as it establishes the benchmark capability of the EUV source and scanner to support semiconductor technology node development.

Cambridge Nanotherm, a producer of semiconductor heatsink technology, this week announced that it has appointed semiconductor industry veteran Ralph Weir as its CEO. This follows just a few months after news of the initiation of its first production line, allowing the company to roll out its advanced nano-ceramic heat dissipation technology at high volumes to meet the growing needs of LED makers. Cambridge Nanotherm also announces the appointment of a new Business Development Director, Andrew Duncan, as well as ISO 9000 accreditation of its production line.

IHS Technology also reported that the number of smart cities worldwide will quadruple within a 12-year period that started last year, proliferating as local governments work with the private sector to cope with a multitude of challenges confronting urban centers. There will be at least 88 smart cities all over the world by 2025, up from 21 in 2013. While the combined Europe-Middle East-Africa region represented the largest number of smart cities last year, Asia-Pacific will take over the lead in 2025. In all, Asia-Pacific will account for 32 smart cities of the total in nine years’ time, Europe will have 31, and the Americas will contribute 25.

TriQuint Semiconductor, Inc., a RF solutions supplier and technology innovator, announced that it is the first gallium nitride (GaN) RF chip manufacturer to achieve Manufacturing Readiness Level (MRL) 9. This achievement means TriQuint’s GaN manufacturing processes have met full performance, cost and capacity goals, and that the company has the capability in place to support full rate production.

Blog review July 21, 2014

Monday, July 21st, 2014

Matthew Hogan, a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, blogs that SoC Reliability Verification Doesn’t Just Happen, You Know. He says the best way to verify multi-IP, multiple power domain SoCs, is with the Unified Power Format (UPF), which enables a repeatable, comprehensive, and efficient design verification methodology, using industry standards, at the transistor level.

Dick James, Senior Technology Analyst, Chipworks, has a TSMC-fabbed 20-nm part in-house, and is looking forward to the analysis results. Wondering what changes TSMC has made from the 28-nm process, Dick says he expects mostly a shrink of the latter process, with no change to the materials of the high-k stack, though maybe to the sequence.

Ed Korczynski continues his theme of “Moore’s Law is Dead” with a third installment that looks at when that might happen. He says that at ~4nm pitch we run out of room “at the bottom,” after patterning costs explode at 45nm pitch.

Vivek Bakshi, EUV Litho, Inc. blogs about The 2014 EUVL Workshop which was held late last month amid some positive highlights and lots of R&D updates. The keynote talks this year were from Intel, Gigaphoton and Toshiba.

In his 201st Insights from The Leading Edge (IFTLE) blog post, Phil Garrou takes a look at some of the presentations at this year’s ConFab. Subramani Kengeri, Vice President, Advanced Technology Architecture for GlobalFoundries discussed the techno-economics of the semiconductor industry. Gary Patton, VP of IBM Semiconductor Research & Development Center addressed “Semiconductor Technology: Trends, Challenges, & Opportunities.” Adrian Maynes, 450C program manager, discussed the “450mm Transition Toward Sustainability: Facility & Infrastructure Requirements.”

Zvi Or-Bach, President and CEO of MonolithIC 3D Inc., blogs that over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.

Blog review July 14, 2014

Monday, July 14th, 2014

Ed Korzynski blogs that Moore’s Law is dead – including what and when in the first two parts of a four part series that reference an interview with Gordon Moore and the “so-called” Moore’s Law (by Moore himself).

Pete Singer also blogs on continued scaling, as discussed by IBM’s Gary Patton at The ConFab in June. Patton said scaling will continue but the industry needs to address costs in addition to continued technology innovation.

Many of the developments in the semiconductor industry have stemmed from the continued progress in lithography. However, with the persistent uncertainty of extreme ultraviolet EUV for future-generation patterning, the industry has developed techniques such as self-alignment double patterning (SADP) to extend optical lithography. In a video produced by SPIETV, Chris Bencher of Applied Materials Office of the Chief Technology Officer, reviews the evolution of SADP and looks to its future.

The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu. Adele Hars reports.

The 5th annual Suss Technology Forum was recently held at SEMICON West focused on trends in 3DIC and WLP. Phil Garrou reports in his latest blog.

Blog review June 2, 2014

Monday, June 2nd, 2014

The Internet of Things alone will surpass the PC, tablet and phone market combined by 2017, with a global internet device installed base of around 7,500,000,000 devices. Speaking at ASMC, TSMC’s John Lin said in addition to a continued push to smaller geometries and ultra-low power, the company will focus on “special” technologies such as image sensor, embedded DRAMs, high-voltage power ICs, RF, analog, and embedded flash. “All this will support all of the future Internet of Things,” he said.

Kavita Shah of Applied Materials blogs about the company’s new Volta system. She says desighed to alleviate roadblocks to copper interconnect scaling beyond the 2Xnm node through two enabling applications—a conformal cobalt liner and a selective cobalt capping layer, which together completely encapsulate the copper wiring.

In an interview, Christophe Maleville, Senior Vice President of Soitec’s Microelectronics Business Unit, talks about why FD-SOI provides a much better combination of power consumption, performance and cost than any alternative. Talking about Samsung’s move to FDSOI, he said “at 28nm, FD-SOI gets them an unprecedented combination of performance and power consumption for a cost comparable to that of standard low-power 28nm technology, making 28FD an extremely attractive alternative to any flavor of bulk CMOS at this node.”

Phil Garrou continues his analysis of presentations from the recent SEMI 2.5/3D IC forum in Singapore. In his third blog post on the topic, he reviews Nanium’s presentation “Wafer Level Fan-Out as Fine-Pitch Interposer” which focused on the premise that FO-WLP technology, eWLB, has closed the gap caused by the delay in the introduction of Si or glass interposers as mainstream high volume commodity technology.

Vivek Bakshi blogs that it takes a large infrastructure to make EUVL a manufacturing technology. So many tool suppliers, large and small, want to know when EUVL will be inserted into fabs for production and how and how much it will be used. Their business depends on these answers and some, especially smaller suppliers, are getting cold feet as delays in EUVL readiness continue. The answers to these questions mostly depend on knowing what we can expect from sources in the short- and near term, but there are many additional questions one must ask as well.

Karen Lightman of the MEMS Industry Group blogs about recent events in Japan, including the MIG Conference Japan. The focus of the conference was on navigating the challenges of the global MEMS supply chain. Several of the speakers gave their no-holds-barred view of these challenges, including the keynote from Sony Communications, Takeshi Ito, Chief Technology Officer, Head of Technology, Sony Mobile Communications.

Blog review February 10, 2014

Monday, February 10th, 2014

Dick James of ChipWorks blogs that when Intel launched their Haswell series chips last June, they stated that the high-end systems would have embedded DRAM, as a separate chip in the package. “It took us a while to track down a couple of laptops with the requisite Haswell version, but we did and now we have a few images that show it’s a very different structure from the other e-DRAMs that we’ve seen,” he notes.

Phil Garrou continues his look at the 2013 Georgia Tech Interposer Conference, focusing on presentations from Amkor and GlobalFoundries. He writes that Ron Huemoeller of Amkor projects that in the high end silicon will dominate; in the mid-end, silicon will be prominent and organic /glass may play a role; in the low end, organic, or low cost glass or silicon if they exist will play a role. Dave McCann of GlobalFoundries examined market needs for interposers.

Semico’s review of the latest and greatest from the Consumer Electronics Show highlights five technologies they think you should pay attention to as game changers: 3D Printing, the Bosch wireless sensor network for IoT; Bionics: Thought-controlled prosthetics; Aging in place: Pain relief; and LED Lighting.

Vivek Bakshi, of EUV Litho, Inc., ponders some interesting questions, such as how important is the semiconductor industry relative to other industries, and how did we get to where we are, the continuation of Moore’s Law and why have there been so few Nobel prizes given to the chip industry?

Karen Lightman of the MEMS Industry Group says the upcoming MEMS Executive Congress Europe “checks all the boxes” with great content and speakers, networking time with MEMS industry execs and OEM users, and an unbeatable location in Munich.

Pete Singer takes a look back at February 1964 through the pages of Solid State Technology, when wafers were small, dreams were big and The Beatles were on the Ed Sullivan show. The issue discussed thermionic energy convertors, the potential of which is still being explored today by Stanford.

Blog Review November 11, 2013

Monday, November 11th, 2013

Karen Savala of SEMI notes that the semiconductor industry is uncharted waters without the benefit of a GPS system. She says mega-mergers, massive supply chain investments by manufacturers and governments, new consortia and collaboration models are changing the rules for everyone in the ecosystem. Pervasive Computing, the theme of this blog post, is also the theme for the upcoming Industry Strategy Symposium (ISS), to be held January 12-14, 2014 in Half Moon Bay, California.

In Karen Lightman’s MEMS Industry Group blog, she turns the reins over to Silex Microsystem’s Peter Himes, vice president marketing & strategic alliances. Peter reflects on MEMS and while other might lament at the conundrum of the uniqueness of all MEMS process, Peter instead sees opportunity. In this example he describes Silex’s partnership with A.M. Fitzgerald and Associates and their Rocket MEMS program.

Phil Garrou covers several topics related to 3D integration in this week’s blog: A new report from Yole on flip chip (FC) technology, ASE’s report ASE – Board Level Reliability of Bump on Polymer (BoP) WLCSPs, and chip embedding at IMS.

Should the lifetime of EUV optics be a concern? Upon hearing about how EUV sources contaminate the optics inside the tool, Pete Singer blogs that there still must be lots of questions about the ultimate cost of ownership and how that will compare to double and triple patterning approaches with 193nm immersion.

Are we using Moore’s name in vain? That question is posed by Zvi Or-Bach, President & CEO of MonolithIC 3D in his blog post, where he notes that dimensional scaling was not an integral part of Moore’s assertion in 1965 – cost was. But dimensional scaling became the “law of the land” and, just like other laws, the industry seems fully committed to follow it even when it does not make sense anymore, he writes.

The Solid State Technology 2014 Editorial Calendar is out, blogs Pete Singer, noting the editorial mission remains that same: we’re dedicated to covering mainstream semiconductor manufacturing technology, with a strong focus on transistors, interconnects and packaging. We also cover other types of advanced electronics, including MEMs, LEDs, displays, bioelectronics, photonics and power electronics.

Blog Review November 5 2013

Tuesday, November 5th, 2013

New blogs delve into the packaging technology of Apple’s A7, the road ahead for bulk FinFETs as defined by imec, with EUV is a gating factor for 450mm, split-manufacturing for U.S. trusted IC (TIC) program and Japan’s growing market for equipment and materials.

For the 10nm node and beyond, transistor research efforts are focused on high mobility designs with Ge and III-V channel, reducing VDD supply voltage as well as the subthreshold slope in transistors and optimizing multi-Vt designs. Pete Singer reports on work underway at imec in Belgium.

At the IEEE 3DIC in San Francisco Dan Radack of the Institute of Defense Analysis gave an update on the IARPA trusted Integrated Chip Program. Phil Garrou reports how it is now focused on split-manufacturing with FEOL done off-shore and BEOL done by trusted facilities in the U.S.

The A7 is manufactured by Samsung on a high-κ metal gate (HKMG) 28 nm process and the chip includes over 1 billion transistors on a die 102 mm2 in size. Phil Garrou reports on observations on the Package-on-Package (PoP) design as noted by fellow blogger Dick James. In an earlier blog, Dick described how the Apple A7 is using Samsung’s 28nm process.

Simon Favre of Mentor Graphics notes how EUV could possibly be a gating factor for 450mm. “Would you put in 450mm immersion steppers, and then yank them out to put in EUV before they’re fully depreciated?” he asks.

In advance of Semicon Japan, to be hold December 4-6 at the Makuhari Messe, SEMI’s Dan Tracy and Yoichiro Ando report that restructuring and consolidation has led to a new focus for the semiconductor manufacturers in Japan. As a result, the semiconductor equipment market in Japan will experience double-digit growth in both 2013 and 2014, driven by higher spending for memory production and in spending increases planned for the manufacturing of power semiconductors and “More than Moore” semiconductor technologies. Total equipment spending in Japan is estimated to reach $4.6 billion by 2014. Combining this with the $8 billion-plus spending on semiconductor materials, Japan represents a $12 billion market in 2014 for the suppliers of equipment and materials.

Next Page »