Part of the  

Solid State Technology

  Network

About  |  Contact

Posts Tagged ‘EUV’

Next Page »

The Week in Review: September 19, 2014

Friday, September 19th, 2014

Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

North America-based manufacturers of semiconductor equipment posted $1.35 billion in orders worldwide in August 2014 (three-month average basis) and a book-to-bill ratio of 1.04, according to the August EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.04 means that $104 worth of orders were received for every $100 of product billed for the month.

Rudolph Technologies has introduced its new SONUS Technology for measuring thick films and film stacks used in copper pillar bumps and for detecting defects, such as voids, in through silicon vias (TSVs).

Samsung Electronics announced this week that it has begun mass producing its six gigabit (Gb) low-power double data rate 3 (LPDDR3) mobile DRAM, based on advanced 20 nanometer (nm) process technology. The new mobile memory chip will enable longer battery run-time and faster application loading on large screen mobile devices with higher resolution.

ProPlus Design Solutions, Inc. announced this week it expanded its sales operations to Europe.

Mentor Graphics this week announced the appointment of Glenn Perry to the role of vice president of the company’s Embedded Systems Division. The Mentor Graphics Embedded Systems Division enables embedded development for a variety of applications including automotive, industrial, smart energy, medical devices, and consumer electronics.

SPIE panel tackles mask complexity issues

Friday, September 19th, 2014

Photomasks that take two-and-a-half days to write. Mask data preparation that enters into Big Data territory. And what happens when extreme-ultraviolet lithography really, truly arrives?

These were among the issues addressed by eight panelists in a Thursday session at the SPIE Photomask Technology conference in Monterey, Calif. Participants in the “Mask Complexity: How to Solve the Issues?” panel discussion came from multiple segments of the photomask food chain, although only one, moderator Naoya Hayashi of Dai Nippon Printing, represented a company that actually makes masks.

The panelists were generally optimistic on prospects for resolving the various issues in question. Dong-Hoon Chung of Samsung Electronics said solutions to the thorny challenges in designing, preparing, and manufacturing masks were “not impossible.”

Bala Thumma of Synopsys said he was “going to take the optimistic view” regarding mask-making challenges. “Scaling is going to continue,” he added.

“We are not at the breaking point yet,” Thumma said. “Far from it!” Electronic design automation companies like Synopsys will continue to improve their software tools, he asserted. Mask manufacturers will also benefit from “strong partnerships” with vendors of semiconductor manufacturing equipment, and “strong support from semiconductor companies,” he said.

“There is a lot of complexity,” he acknowledged. Still, going by past experience, “this group of people has been able to work together and solve these issues,” Thumma concluded.

To resolve the issue of burgeoning data volumes in mask design and manufacture, Suichiro Ohara of Nippon Control System (NCS) proposed the solution of a unified data format – specifically MALY and OASIS.MASK software. Shusuke Yoshitake of NuFlare Technology later said, “OASIS is gaining, but GDSII still predominates.”

Several panelists took the long-term view and looked beyond the coming era of EUV lithography to when multiple-beam mask writers and actinic inspection of masks will be required. EUV and actinic technology, it was generally agreed, will arrive at the 7-nanometer process node, possibly in 2017 or 2018. Multi-beam mask writers are also several years away, it was said.

As the floor was opened to questions and comments, consultant Ken Rygler noted that commercial mask makers have “very low margins” and asked, “How does the mask maker pay for the inspection tools, the EDA, materials?” Yalin Xiong of KLA-Tencor said the mask business is in “a tough time economically.” He added, “We have to look at where the high-end business is going. Captive [mask shops] should step up.”

ASML on EUV: Available at 10nm

Wednesday, September 17th, 2014

thumbnail

By Jeff Dorsch, contributing editor

Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

Giving the keynote presentation Tuesday at the SPIE Photomask Technology conference in Monterey, Calif., Martin offered a lengthy update on his company’s progress with EUV technology.

Sources for the next-generation lithography systems are now able to produce 77 watts of power, and ASML is shooting for 81W by the end of 2014, Martin said.

The power figure is significant since it indicates how many wafers the litho system can process, a key milestone in EUV’s progress toward becoming a volume manufacturing technology. With an 80W power source, ASML’s EUV systems could turn out 800 wafers a day, he noted.

The goal is to get to 1,000 wafers per day. ASML has lately taken to specifying throughput rates in daily production, not wafers per hour, since many wafer fabs are running nearly all the time at present.

ASML’s overarching goal is providing “affordable scaling,” Martin asserted, through what he called “holistic lithography.” This involves both immersion litho scanners and EUV machines, he said.

Martin offered a product roadmap over the next four years, concluding with manufacturing of semiconductors with 7nm features in 2018.

The ASML president acknowledged that the development of EUV has been halting over the years, while asserting that his company has made “major progress” with EUV. He said the EUV program represented “a grinding project, going on for 10 years.”

For all of EUV’s complications and travails, “nothing is impossible,” Martin told a packed auditorium at the Monterey Conference Center.

With many producers of photomasks in attendance at the conference, Martin promised, “We are not planning to make a significant change in mask infrastructure” for EUV. He added, “What you are investing today will be useful next year, and the year after that.”

Lithography: What are the alternatives to EUV?

Thursday, August 28th, 2014

By Pete Singer, Editor-in-Chief

EUV received a recent boost with IBM reporting good results on a 40W light source upgrade to its ASML NXE3300B scanner, at the EUV Center of Excellence in Albany. The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.  In the first 24 hours of operation after the upgrade, 637 wafer exposures were completed in normal production lot mode. Dan Corliss, the EUV Development Program Manager for IBM, called it a “watershed moment.”

Critics, most notably analyst Robert Maire of Semiconductor Advisors, said it was “not that much of a real increase in power and certainly no breakthrough, just incremental improvement.” He adds: “We still don’t have the reticle “ecosystem,” the resist and many other components to make for viable, commercial EUV production. We are still a very long way away and this does not change the view that EUV will not be implemented at 10nm.” The 10nm node is slated to go into production in late 2015/early 2016.

Yet EUV proponents remain optimistic. Kevin Cummings, the director of lithography at SEMATECH, said “It is good news indeed to hear that IBM in conjunction with ASML has met/exceeded their projected productivity. It is clear to this industry that the EUV LPP source was not meeting the desired schedule and the source improvements timelines were over promised. However this announcement give us some confidence that we are making progress against that schedule. In addition, this milestone is significant in that it allows the wafer throughput needed to continue EUVL HVM development. With the throughputs obtained on the scanner and the recent successes from SEMATECH on zero defect mask blanks and low-dose high-resolution resists now is an excellent time to take advantage of the Albany NY based capability to develop the materials and processes that will be needed for EUVL manufacturing.”

Luc Van den hove, president and CEO of imec, described EUV as a cost-effective lithography approach that is “absolutely needed.” In terms of imaging performance, imec has been characterizing some of the latest hardware together with ASML and have showed very good resolution performance of 13nm half pitch and 22nm contact holes. “With double patterning, we have even demonstrated 9nm half pitch,” Van den hove said. “Who would have thought a couple of years ago that this would be realizable with lithography?”

An Steegen, senior vice president of process technology at imec, said the ideal entry point for EUV is the 10nm node (or N10 using imec’s terminology). “If you look at the cost calculation, the best entry point for EUV is actually at N10 because you can replace triple patterning layers in immersion with a single patterning layer in EUV,” Steegen said. Since that will come relatively soon with early production occurring toward the end of 2015 and in early 2016, that means that likely the whole development phase will have already been built on immersion and multi-patterning. “Likely you will see on the most difficult levels, a swap, an introduction of EUV at the most critical levels later on in manufacturing for N10,” Steegen said.

Interestingly, industry-leader Intel has said that it will not use EUV for 14nm, and even sees a path to 10nm without EUV. At the Intel Developer’s Forum in 2012, Mark Bohr, director of Intel’s technology and manufacturing group said 10nm “would require quadruple patterning for some mask layers but it’s still economical.”

FIGURE 1. Multi-patterning can achieve sub-10nm dimensions. Source: Applied Materials.

FIGURE 2. Multi-patterning adds many process steps, and cost. Source: ASML.

FIGURE 1 shows that the use of spacers can enable sub-10nm dimensions without EUV. FIGURE 2 shows multi-patterning adds to process cost and complexity.

Earlier this year, at the SEMI Northeast Forum held in North Reading, MA, Patrick Martin, Senior Technology Director at Applied Materials, talked about scaling and the rising cost and complexity of patterning. “There’s a lot of talk in the industry about how scaling is dead,” he said. I think a lot of the discussions are if we look at the current architectures entitlements – finFET related technologies that scale to 7nm and 5nm, and the complexity associated with litho, driving those types of cost models, I would have to agree. But the argument is really going to be on architecture entitlement. How the devices are going to adapt to these pattern complexity limited challenges.”

Terry Lee, the chief marketing officer for the DSM business unit at Applied Materials says continued scaling will not be driven as much by lithography, but by 3D. “Scaling used to be enabled by lithography,” he said in a presentation at this year’s Semicon West. “What we’re seeing is the move to enable scaling using both materials and 3D device architectures.” 3D devices include FinFETs, 3D NAND DRAMs with buried word lines and bit lines. These devices represent “the drive to further scale on a third dimension versus scaling using lithography on a horizontal plane,” Lee said. Appled Materials recently introduced a several new products aimed at the 3D device market, including the Producer XP Precision CVD system.

“We’re really in a dilemma when it comes to semi-related production capability,” Martin said. The device features are much smaller than the wavelength that we’re using. We’re into these complex processing related technologies that require double patterning, triple patterning, multiple patterning. The great equalizer here is EUV. If we can ever get to EUV-related manufacturing capability, it gets us to a regime where the devices are relatively the same size as the wavelength of light. The problem is that it’s been delayed. The challenge is if it doesn’t hit 10nm, we’re looking at 7nm. If we start looking at the insertion opportunity for EUV at 7nm and 5nm, we’re now below wavelength. 13.5 nm is the wavelength of EUV. The complexities associated with double patterning come back into play,” Martin added.

The EUV mask challenge

The next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. According to Veeco’s Tim Pratt, Senior Director, Marketing, the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV. “Based on the yield today, the mask blank manufacturing capacity can’t produce enough mask blanks to support the ASML scanners that they’re planning to ship,” Pratt said. “ASML is going to be delivering some light source upgrades in the field and when those start happening, the effective total wafer throughput of EUV scanners in the field is going to multiply and there’s just not the supply of usable mask blanks to be able to support those.”

The requirement for 2015 is to have zero blank defects larger than 62nm. SEMATECH in 2012 reported work showing eight defects larger than 50nm. “A lot of progress being made but the elusive zero defects has not yet been hit,” Pratt said. Veeco, which is the sole supplier of EUV multilayer deposition tools, has plans to upgrade the existing Odyssey tool and launch a new platform in the 2017/2018 timeframe.

FIGURE 3. EUV masks are considerably more complicated than conventional photomasks. Source: Veeco.

FIGURE 3 shows an EUV mask, which is considerably more complicated than conventional photomasks.

What could derail the EUV ramp, according to Pratt, is a supply of defect-free mask blanks. “EUV is, despite many years and many dollars of investment, not yet in production. The two main gaps are the EUV light sources and the defects on the mask. As they start to make progress, people start to look more seriously at the list of things to worry about for EUV going to production.

The e-beam alternative

There are only a few alternatives to EUV and complex (and costly) mutli-patterning approaches: multi-e-beam (MEB), nanoimprint and directed self-assembly. Electron beam lithography with a single beam has been used for many years for mask writing and device prototyping, and tools available from a number of companies, such as Advantest, IMS, JEOL and Vistec.

Single-beam writing has never been able to compete with massively parallel optical systems in throughput and cost. Now, TSMC’s Burn Lin says that the time for e-beam lithography has arrived. Why? Digital electronics can affordably provide a gigabit per second data rate in a manageable space, enabling very high wafer throughput. Microelectrical mechanical systems and packaging techniques have advanced sufficiently to support a several order of magnitude increase in beam number and high-speed beam writing. And e-beam techniques generally offer higher resolution than optical systems. [1] Last year, TSMC and KLA-Tencor presented a reflective e-beam lithography (REBL) system that can potentially enable multiple-e-beam direct-write for high-volume manufacturing.

Multiple beam systems are also being developed by Multibeam Corp. (the well known David Lam is CEO), IMS and MAPPER. MAPPER was founded in 2000 by Professor Pieter Kruit and two of his recent graduates Marco Wieland and Bert Jan Kampherbeek.

What’s intriguing about e-beam direct write is that it could be used in conjunction with more conventional immersion lithography. Yan Borodovsky, Intel Corporation Sr. Fellow and Director of Advanced Lithography, calls it “complementary lithography.” He says that EBDW could be used instead of EUV to break the continuity of the grating made using 193i with pitch division. In addition to again maintaining the benefits of mature 193i on the critical layer, this solution has lower mask costs (no mask required for grating cutting and vias), and the escalating cost of the mask-making infrastructure is avoided.

He reported that EBDW could also be used instead of EUV for the complementary solution to break the continuity of the grating made using 193i with pitch division. In addition to again maintaining the benefits of mature 193i on the critical layer, this solution has lower mask costs (no mask required for grating cutting and vias), and the escalating cost of the mask-making infrastructure is avoided.

An organization that is focused on developing e-beam technology for mask writing and direct write is the E-beam Initiative (www.ebeam.org).

Nanoimprint

Step and Flash Imprint Lithography (SFIL), a form of ultraviolet nanoimprint lithography (UV-NIL), is recognized for its resolution and patterning abilities. It is one of the few next generation lithography techniques capable of meeting the resolution requirements of future semiconductor devices. Austin-based Molecular Imprints, now a wholly owned subsidiary of Canon, has successfully commercialized the technology. Molecular Imprints invested $165 million over the last decade on platforms, materials, templates and applications.

In 2004, Canon began conducting research into nanoimprint technology to realize sub-20nm high-resolution processes began carrying out joint development with Molecular Imprints and a major semiconductor manufacturer in 2009. Canon says NIL offers such benefits as high-resolution performance, exceptional alignment accuracy and low cost. However, others report that many integration issues such as defectivity, throughput, and overlay must be resolved before SFIL can be used for leading-edge semiconductor high volume manufacturing.

DSA is very promising

Imec’s Van den hove described direct self-assembly (DSA) as “very promising” and Steegen said work there has largely focused on reducing defectivity. In DSA, resists that contain block copolymers are deposited on top of guiding structures. The self-directed nature of the process results in very regular patterns with very high resolution.

The trick with DSA is that it requires a double exposure to take away the random patterns at the edge of the device, and the resolution needed for this “cut mask” is also very high. “We’re convinced that it’s not a replacement for EUV or any high resolution lithography technique. We are very convinced it will be used in conjunction with EUV,” Van den hove said. “It certainly keeps the pressure on EUV very high.”

Steegen described DSA as a complimentary litho technique that is having quite some momentum. The process starts with a “relaxed” guiding pattern on your wafer.  Then, depending on the polymer length in the block copolymer, the space in between the guiding structure is replicated into multiple lines and spaces. “The defectivity of these materials are going to be key to bring the defects down. Our year end target is 60 defects/cm2 and this needs to go down even further next year,” she said.

Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” Steegen said. Imec is already looking at where DSA levels could be inserted into the logic N7 flow, with fins and spacers being primary targets. Steegen said the Metal1 level would be a challenge due to its irregular pattern. “That makes it not easy to be replaced with DSA, but we’re looking into techniques to do that,” she said.

Here’s how imec summed up DSA readiness:

• Good progress in material selection and integration flow optimization for line-multiplication down to 14nm, pattern transfer into bulk Si demonstrated.

• First templated DSA process available using SOG/SOC hard mask stack.

• Focus on defectivity reduction & understanding, currently at 350 defects/cm2, YE13 target 60 def/cm2

• Alignment and overlay strategy needs to be worked out

• First N7 implementation levels identified: Finfet (replace SADP EUV or SAQP 193i) and Via (replace EUV SP/DP or 193i LE3).

Conclusion

Hopes remain high for EUV, but long delays has caused attention to shift to possible alternatives. Multi-level patterning is costly but it works; Intel, for example, says it will soon have 14nm devices in production without using EUV. Mutli-ebeam work continue apace, and we could see a role in direct write e-beam in a complementary approach with conventional lithography. Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. Some new device structures, such as vertical NAND and FinFETs, take the pressure off of lithography, but create challenges in other process areas, such as deposition and etch.

Blog review August 18, 2014

Monday, August 18th, 2014

Vivek Bakshi provides a deeper look at the ASML/IBM announcement on EUV progress. ASML and IBM reconfirmed the benchmarking in press and via social media. In short, 637 wafers per day throughput stands, resulting from the successful upgrade of source power by 100%, to its targeted level of ~43 W.

Dick James of Chipworks finally has his hands on Samsung’s V-NAND vertical flash. The vertical flash was first released in an enterprise solid-state drive (SSD) last year, in 960 GB and 480 GB versions. Then in May this year they announced a second-generation V-NAND SSD, with a stack of 32 cell layers.

Phil Garrou provides an overview of controlling warpage in packaging as discussed at ECTC by Hitachi Chemical, Amkor, Qualcomm, and imec.

Anand Sundaram, Senior Associate for PwC’s PRTM Management Consulting writes that software that controls and powers embedded devices is playing a key role in making possible the highly integrated, multi-functional ‘smart’ devices we take for granted in our daily lives – from the ubiquitous smart phones/tablet to ‘smart’ home appliances and wearable electronics.

Pete Singer posted an IoT infographic, courtesy of Jabil. The global IoT market is poised for explosive growth. By 2020, the market is expected to soar to $7.1 trillion. This infographic, courtesy of Jabil, gives an good overview of what will be connected (even garbage bins!).

Bob Smith, Senior Vice President of Marketing and Business Development, Uniquify blogs that these days, chip design may seem like an intricately connected jigsaw puzzle, including small, oddly shaped interlocking pieces.

Solid State Watch: July 31-August 7, 2014

Friday, August 8th, 2014
YouTube Preview Image

Blog review August 4, 2014

Monday, August 4th, 2014

Innovation is alive and well in the semiconductor industry. That was a key takeaway from the strategic investor panel at the second annual Silicon Innovation Forum at SEMICON West, and one I can’t reinforce enough within the venture capital (VC) community. Eileen Tanghal of Applied Materials reports.

At SEMICON West this year in Thursday morning’s Yield Breakfast sponsored by Entegris, top executives from Qualcomm, GlobalFoundries, and Applied Materials discussed the challenges to achieving profitable fab yield for atomic-scale devices. In his blog, Ed Korzynski reports on what was discussed.

Phil Garrou blogs that Apple has acquired 24 tech companies in the last 18 months. Recently, Apple acquired LuxVue, a start-up focused on low power micro-LED displays. Although Apple has not disclosed any details of the acquisition, not even the purchase price, one can easily envision where micro LED displays could play a big part in Apples thrust into wearable electronics such as the i-watch, Phil says.

Adele Hars continued a report on the SOI papers at the VLSI Symposia in this Part 2 installment. The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry.

Vivek Bakshi created a EUV stir, blogging about IBM’s NXE3300B scanner, at the EUV Center of Excellence in Albany, which recently completed a “40W” EUV light source upgrade.  The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.

The Week in Review: August 1, 2014

Friday, August 1st, 2014

Semiconductors providing wireless connectivity in health and fitness devices are set for solid double-digit growth in 2014 and beyond, especially as a clutch of wireless technologies make their way into a growing number of wearable devices, according to a new report from IHS Technology.

This week, IBM reported that its NXE3300B scanner, at the EUV Center of Excellence in Albany, recently completed a 40 Watt EUV light source upgrade.  The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.  In the first 24 hours of operation after the upgrade six hundred thirty seven wafer exposures were completed in normal production lot mode. Vivek Bakshi of EUV Litho, Inc. said that this is a watershed moment for EUV as it establishes the benchmark capability of the EUV source and scanner to support semiconductor technology node development.

Cambridge Nanotherm, a producer of semiconductor heatsink technology, this week announced that it has appointed semiconductor industry veteran Ralph Weir as its CEO. This follows just a few months after news of the initiation of its first production line, allowing the company to roll out its advanced nano-ceramic heat dissipation technology at high volumes to meet the growing needs of LED makers. Cambridge Nanotherm also announces the appointment of a new Business Development Director, Andrew Duncan, as well as ISO 9000 accreditation of its production line.

IHS Technology also reported that the number of smart cities worldwide will quadruple within a 12-year period that started last year, proliferating as local governments work with the private sector to cope with a multitude of challenges confronting urban centers. There will be at least 88 smart cities all over the world by 2025, up from 21 in 2013. While the combined Europe-Middle East-Africa region represented the largest number of smart cities last year, Asia-Pacific will take over the lead in 2025. In all, Asia-Pacific will account for 32 smart cities of the total in nine years’ time, Europe will have 31, and the Americas will contribute 25.

TriQuint Semiconductor, Inc., a RF solutions supplier and technology innovator, announced that it is the first gallium nitride (GaN) RF chip manufacturer to achieve Manufacturing Readiness Level (MRL) 9. This achievement means TriQuint’s GaN manufacturing processes have met full performance, cost and capacity goals, and that the company has the capability in place to support full rate production.

Blog review July 21, 2014

Monday, July 21st, 2014

Matthew Hogan, a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, blogs that SoC Reliability Verification Doesn’t Just Happen, You Know. He says the best way to verify multi-IP, multiple power domain SoCs, is with the Unified Power Format (UPF), which enables a repeatable, comprehensive, and efficient design verification methodology, using industry standards, at the transistor level.

Dick James, Senior Technology Analyst, Chipworks, has a TSMC-fabbed 20-nm part in-house, and is looking forward to the analysis results. Wondering what changes TSMC has made from the 28-nm process, Dick says he expects mostly a shrink of the latter process, with no change to the materials of the high-k stack, though maybe to the sequence.

Ed Korczynski continues his theme of “Moore’s Law is Dead” with a third installment that looks at when that might happen. He says that at ~4nm pitch we run out of room “at the bottom,” after patterning costs explode at 45nm pitch.

Vivek Bakshi, EUV Litho, Inc. blogs about The 2014 EUVL Workshop which was held late last month amid some positive highlights and lots of R&D updates. The keynote talks this year were from Intel, Gigaphoton and Toshiba.

In his 201st Insights from The Leading Edge (IFTLE) blog post, Phil Garrou takes a look at some of the presentations at this year’s ConFab. Subramani Kengeri, Vice President, Advanced Technology Architecture for GlobalFoundries discussed the techno-economics of the semiconductor industry. Gary Patton, VP of IBM Semiconductor Research & Development Center addressed “Semiconductor Technology: Trends, Challenges, & Opportunities.” Adrian Maynes, 450C program manager, discussed the “450mm Transition Toward Sustainability: Facility & Infrastructure Requirements.”

Zvi Or-Bach, President and CEO of MonolithIC 3D Inc., blogs that over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.

Blog review July 14, 2014

Monday, July 14th, 2014

Ed Korzynski blogs that Moore’s Law is dead – including what and when in the first two parts of a four part series that reference an interview with Gordon Moore and the “so-called” Moore’s Law (by Moore himself).

Pete Singer also blogs on continued scaling, as discussed by IBM’s Gary Patton at The ConFab in June. Patton said scaling will continue but the industry needs to address costs in addition to continued technology innovation.

Many of the developments in the semiconductor industry have stemmed from the continued progress in lithography. However, with the persistent uncertainty of extreme ultraviolet EUV for future-generation patterning, the industry has developed techniques such as self-alignment double patterning (SADP) to extend optical lithography. In a video produced by SPIETV, Chris Bencher of Applied Materials Office of the Chief Technology Officer, reviews the evolution of SADP and looks to its future.

The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu. Adele Hars reports.

The 5th annual Suss Technology Forum was recently held at SEMICON West focused on trends in 3DIC and WLP. Phil Garrou reports in his latest blog.

Next Page »