Posts Tagged ‘CVD’
The Semiconductor Industry Association announced that worldwide sales of semiconductors reached $25.87 billion for the month of February 2014, an increase of 11.4 percent from February 2013 when sales were $23.23 billion.
Nanoengineering researchers at Rice University and Nanyang Technological University in Singapore have unveiled a potentially scalable method for making one-atom-thick layers of molybdenum diselenide.
SEMI releases fourth quarter 2013 worldwide photovoltaic equipent market statistics report. Bookings levels improved some in the quarter to reach the highest value since the first quarter of 2012.
Using a laser to place individual rubidium atoms near the surface of a lattice of light, scientists at MIT and Harvard University have developed a new method for connecting particles.
Researchers at Johannes Gutenberg University Mainz (JGU) have achieved a major breakthrough in the development of methods of information processing in nanomagnets.
The Global Semiconductor Alliance (GSA) is celebrating 20 years of industry collaboration this year.
After the successful premier of a program to connect early-stage companies with strategic investors and venture capitalists (VCs) in the U.S., SEMI is expanding the program to Europe as part of SEMICON Europa 2014 in Grenoble, France (October 7-9).
By Pete Singer, Editor-in-Chief, Solid State Technology
Applied Materials introduced three new tools for the display market aimed at metal oxide thin film transistors. The tools, one of which is CVD and the other two PVD, employ new hardware designs and process technology that enable better film uniformity with fewer defects, and are designed for use with next generation IGZO-based thin film transistors (TFTs). The display industry is quickly switching to metal oxide TFTs and IGZO (indium gallium zinc oxide) is the material of choice.
Higher resolution LCD displays, greater than 300 dpi, require a switch from amorphous silicon designs to either metal oxide transistors or low-temperature polysilicon (LTPS), which offer higher-mobility in a smaller area (Figure 1). They also operate at lower power levels, which is important in mobile devices. Another problem with larger transistors is that they block too much of the light in the display.
LG has already begun shipping 55-inch OLED TVs using metal oxide backplanes and by 2014, all major LCD and LED display makers will have begun the switch over to metal oxide TFTs.
The advantage of metal oxide transistors over LTPS transistors is that they consume less power and are more easily scaled.
The layers in an IGZO transistor are deposited by both PVD and CVD, according to Max McDaniel, Applied Materials’ director and chief marketing officer for its display business. Figure 2 shows a cross-section of the device. “You use PVD to deposit the metal gate material (on the glass substrate), then you have an insulator over the top of the gate (GI = gate insulator in the figure). That’s deposited by PECVD. On top of that, you’ve got the active layer, which is the IGZO. This is deposited by PVD. Then you’ve an etch stop layer (ESTL in the figure) and that’s a PVD layer. Then you’ve got the source/drain, which is a metal deposited by CVD. Finally, you’ve got the passivation on the top which is a CVD layer,” McDaniel said. He noted that these interfaces between the CVD layers and the IGZO are critical. “We want to reduce the hydrogen as much as we can, so that’s what our technology helps the customer to do,” he said, adding that Applied Materials has the capability to build transistors in house and test them. “We’re able to solve some of these integration challenges before we deliver it to the customer.”
This time last year, Applied Materials introduced two new products. One offers a new design for depositing IGZO films for TFTs; the other handles bigger substrates of low temperature polysilicon (LTPS) films to help lower manufacturing costs.
The three new products now being introduced are the Applied AKT-PiVot 55K DT PVD, Applied AKT-PiVot 25K DT PVD and Applied AKT 55KS PECVD. The 55k nomenclature is a reference to the Gen 8.5 size panesl the system can handle, which are 2.2m x 2.5 m, or 55,000 cm2. DT stands for “dual track” which is new.
One of the key changes in the 55KS PECVD system include is related to how process gas is distributed the substrate surface. “The hundreds of thousands of holes that the gas is distributed out of – you have to customize them across the whole area of the chamber to compensate for the shape of the plasma,” McDaniel said. “It’s not just the diameter of the holes, it’s the depth of them.” A new gas deflector pre-distributes the gas before it goes into the diffuser, and support structures were added to achieve a higher degree of flatness over the 2.5 wide area.
On the PVD side, the new systems are designed specifically for IGZO. “Unlike our prior Pivot PVD system, where you want to have lots of chambers and be able to run multiple materials in different chambers, customers really want a system that just deposited the IGZO,” McDanield said. “It gets the substrates in and out quickly, so this is a compact, efficient platform that’s designed for depositing the IGZO.” The 25K system is targets displays for mobile applications. “We’re entering a whole new segment,” McDanield added.
The Pivot employs a set of rotary cathodes and targets, which act quite differently than conventional planar targets. Planar targets don’t get consumed uniformly and there can be redeposition of the material back onto the target. This redeposited material can spall off as particles. “Our technology is different,” McDaniel said. “The target is an array of rotating targets/cathodes. As they are being bombarded and consumed, you’re actually rotating the tubes in a circle and consuming them evenly throughout the deposition. The other benefit is this is a reactive process so you also have to introduce oxygen gas into the reaction. With the planar cathode, you have to introduce the gas from around the sides of the planar target. It’s hard to get it evenly over the substrate. With this array of tubes, you can introduce the process gas in between the tubes and get it uniformly distributed over the substrate,” he said. The rotary cathode employ magnets inside the tubes for uniformity enhancement.
McDaniel added that presently everyone who is doing metal oxide IGZO use the etch stop (ES) structure (Figure, right), but would like to eliminate the etch stop and use a back channel etch (BCD) directly (Figure, left). “The IGZO material is very sensitive to hydrogen. What you’re trying to do is not expose it to the etching chemistry,” he said. “You put an etch stop layer on top of the IGZO, which is a CVD SiO2 process, and that protects it while you’re etching the source and drain. That adds an extra mask and extra process step. The panel makers would like to get rid of that etch stop layer and go to a back channel etch (BCE). This is where you etch the source drain directly down all the way to the IGZO and it’s unprotected. We’re not there yet, but the industry would like to see that structure developed. That’s on the roadmap for the industry.”
Looking forward, the holy grail for the display industry might just be the flexible display. McDaniel said flex displays will not likely be based on LCDs, but OLEDs. “For flexible OLED, you want to deposit on a flexible, non-glass substrate and then you need to encapsulate the OLEDs with something other than rigid glass.” This could require numerous thin films, which is good news for a supplier of tool deposition systems. He added that they would probably require an alternative to ITO (a commonly used transparent conductor). “There are a number of ITO replacement materials that are being looked at now, so as metal mesh, nanowires and even carbon nanotubes,” he said.
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.