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Air-gaps in Copper Interconnects for Logic

Friday, October 31st, 2014


By Ed Korczynski, Sr. Technical Editor, SST/SemiMD

The good people at ChipWorks have released some of the first public data on Intel’s new 14nm-node process, and the results indicate that materials limitations in on-chip electrical interconnects are adding costs. Additional levels of metal have been added, and complex “air-gap” structures have been added to the dielectric stack. Flash memory chips have already used air-gaps, and IBM has already used a subtractive variant of air-gaps with >10 levels of metal for microprocessor manufacturing, but this is the first known use of additive air-gaps for logic after Intel announced that a fully-integrated process was ready for 22nm-node chips.

Mark Bohr of Intel famously published data in 1995 (DOI:  10.1109/IEDM.1995.499187) on the inherent circuit speed limitations of interconnects, showing proportionality to the resistance (R) of the metal lines multiplied by the capacitance (C) of the dielectric insulation around the metal (Fig.1). The RC product thus should be minimized for maximum circuit speed, but the materials used for both the metal and the dielectric insulation around metal lines are at limits of affordability in manufacturing.

There are no materials that super-conduct electricity at room temperature, and only expensive and room-sized supercomputers and telecommunications base-stations can afford to use the liquid-nitrogen cooling that is needed for known superconductors to function. Carbon Nano-Tubes (CNT) and 2D atomic-layers of carbon in the form of graphene can conduct ballistically, but integration costs and electrical contact resistances limit use. Copper metal remains as the best electrical conductor for on-chip interconnects, yet as horizontal lines and vertical vias continue to shrink in cross-sectional area the current density has reached the limit of reliability. The result is the increase in the number of metal layers to 13 for 14nm-node Intel microprocessors, while IBM used 15 layers for 22nm-node Power8 chips.

Low-k Dielectrics and Pore Sizes

The dielectric constant (“k”) of silicon oxide is ~4, and ~3.5 with the addition of fluorine to the oxide (SiOF). Carbon-Doped Oxide (CDO or SiOC or SiOC:H) with k~3.0 has been integrated well into interconnect stacks. Some polymers can provide k values in the 2.0-2.7, but they cannot be integrated into most interconnects due to lack of mechanical strength, chemical resistance, and overall stability. Air has k=1, and there have been specialized chips made using metal wires floating in air, but lack of physical structure results in poor manufacturing yield and weak reliability.

A clever compromise is to use both SiOC with k~3 and air with k~1 in a stack, which results in an integrated k value weighted by the percent of the volume taken up by each phase. Porous Low-k (PLK) with 10% porosity allows for an integrated k of ~2.7 for modest improvement, but increasing porosity to just 20% for k~2.4 results in connected random pores that reduce reliability. To reliably integrate 20-30% air into SiOC, the pores cannot be random but must be engineered as discrete gaps in the structure.

In 2007, IBM announced that it would engineer air-gaps in microprocessors, but the company claimed to be using an extremely complex process for integration involving a self-assembled thin-film mask to anisotropically etch out holes between lines and then further isotropic etching to form elongated pores. Though relatively complex and expensive, this process allows for the use of any 2D layout for lines in a given metal layer.

Additive Air-gap Process-Design Integration

For fab lines that are still working with aluminum metal and additive dielectrics, air-gaps are a defect that occurs with imperfect dielectric fill. When not planned as part of the design, air-gaps formed in a lower-layer can be exposed to etchants during subsequent processing resulting in metal shorts or opens. However, Figure 2 shows that it is possible to engineer air-gaps by Chemical-Vapor Deposition (CVD) of dielectric material into line-space structures with proper process control and design layout restrictions. Twenty years ago, this editor worked for an OEM on CVD processes for dielectric fill, and the process can be tuned to be highly repeatable and relatively low-cost if a critical masking step can be avoided. In 1998, Shieh et al. from Stanford (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) showed proof-of-concept for this approach to lower k values.

Figure 2: CVD can be easily tuned to initially coat sidewalls (top), then pinch-off (middle), and finally form a closed pore (bottom) during one step. (Source: Ed Korczynski)

Four years ago at IEDM 2010, Intel presented details of how to engineer air-gaps using CVD. As this editor wrote at that time in an extensive analysis:

The lithographic masking step is needed for two reliability reasons. First, by excluding air-gap formation in areas near next-layer vias, alignment between layers can be more easily done. Second, wide spaces are excluded where the final non-conformal CVD step wouldnt automatically pinch-off to close the gaps; leaving full SiOC(H) in wider spaces also helps with mechanical strength. The next layer is patterned with a conventional dual-damascene flow, with the option to add air-gaps.

Now we know that Intel kept air-gaps on the metaphorical shelf by skipping use at the 22nm-node. The 2014 IEDM paper from Intel will discuss details of 14nm-node air-gaps:   two levels at 80nm and 160nm minimum pitches, yielding a 17% reduction in capacitance delays.

This process requires regularly spaced 1D line arrays as a design constraint, which may also be part of the reason for additional metal layers to allow for 2D connections through vias. Due to lithography resolution advantages with 1D “gridded” layouts, other logic fabs may soon run 1D designs at which point additive air-gaps like that used by Intel will provide a relatively easy boost to IC speeds.

The Week in Review: October 17, 2014

Friday, October 17th, 2014

Driven by rising demand for fitness and health monitoring features as well as by improved user interfaces, shipments of sensors used in wearable electronic devices will rise by a factor of seven from 2013 through 2019, according to IHS Technology.

Intermolecular, Inc. announced this week that Dr. Bruce McWilliams has been appointed president and chief executive officer. David Lazovsky has resigned as president and chief executive officer and from the Board of Directors to pursue other interests.

Qualcomm announced that it has reached agreement with CSR regarding the terms of a recommended cash acquisition of CSR will be acquired by Qualcomm Global Trading Pte. Ltd.

Texas Instruments this week announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial.

Element Six this week announced the development of a new thermal grade of diamond grown by chemical vapor deposition (CVD), DIAFILM TM130.

Wrap-up: SEMI’s Strategic Materials Conference

Tuesday, October 7th, 2014

SEMI’s Strategic Materials Conference was held September 30-October 1, 2014, in Santa Clara, CA at the Biltmore hotel.

By Karey Holland, Techcet Group

The 2014 Strategic Materials Conference was very well attended.  There were people from several of the leading IC makers as well as suppliers of equipment and materials to the fabs.  Unfortunately, the audio and video systems were not stellar, so we had to endure some ear shattering system noise, and any light image was not visible on the screens.  Otherwise, the venue was good.  Throughout the conference, several themes were repeated.

Focus on the stability we hope for in post 2013 times, but concern about volatility and uncertainty of the world economics, esp. the recession-like growth numbers in Europe and Japan expected for the next few years. While forecasters (Gartner, IC Insights, VLSI Research, Linx, Techcet Group and others) anticipate IC wafer starts growing at ≥6% CAGR over the next 5 years, there is concern that any number of geo political world problems could throw us back into a global recession.  Attendees had a greater concern than the presenters over the possibility of a future recession, and that the impact would be greater to IC industry now due to the entrenchment of mobile platforms.

Focus on cost of lithography as a driver for increased cost of leading edge MCUs/MPUs … with current nodes, multi-patterning requires many more expose/develop/dep/etch steps than EUV, but EUV has not yet met the requirements for manufacturing implementation.  It is likely that EUV will first be used for only a few critical layers.  DSA (directed self-assembly) may be used also for a few selected critical layers, but issues of defects will likely keep it from use in many layers.

Focus on the expected (and currently numerous options) for advanced devices and implications for materials.  This includes advanced packaging technologies.

450mm wafers may continue to slip, if the other large IC makers (e.g. TSMC, Samsung, GlobalFoundries) don’t agree with Intel on first implementation date/node. Collaboration across the entire ecosystem was stressed for 450mm to become a reality.

Below are things I found particularly interesting in the presentations and/or at the end of day panel discussions.

The key note presentation, “Materials Innovation for the Digital 6th Sense Era,” was by Matt Nowak of Qualcomm.  He discussed both the vision of the Internet of Things (IoT), the required IC devices (including analog & sensors) and implications to materials (and cost to manufacture) from these new IC devices; a perfect start to SMC 2014.  Qualcomm defines the Digital 6th Sense Era is “the augmentation of human ability”, or as Sue Davis put it “intelligent data based extension of our 5 senses ==>to a 6th“. Essentially this is where the ability of the IoT/IoE data feedback can act as our 6th sense by capturing data about one & one’s environment which results in  prediction/information being shared based on data collection and/or user selections regarding the environment around us (or about us, e.g., tele-health).”  Because the smartphone is the “most pervasive platform ever” (US Android users average 106 Apps launched/day), it can serve as a remote connection to the IoT world … be that monitoring our health, schedules, honey-do lists, and improving our understanding and enjoyment of the world around us.  For advanced logic one might expect, lithography for advanced ICs (quad patterning vs EUV) were discussed as key cost drivers.  Other required/expected advanced materials include high mobility channel materials and thin barrier metals (likely Co). Beyond CMOS, new structures and materials may be required to support sensors (bio, chemical, fluidic), nano batteries, piezo, thermal, and solar harvesters.

Mark Thirsk, Linx-Consulting, reviewed IC growth and lack thereof for past years, and observed that 2014 will be “first good year in 8 years” (since 2006), and forecast 6-8% CAGR for the next few years – strongly dependent on the success of the IoT.  IC market growth since 2010 correlates strongly to GDP since 2010, and thus regional GDP differences (e.g. the current European recession) are reflected in IC demand.  Technology challenges & opportunities in for the next 5+ years include advanced logic (3D NAND, and new memory method after 2018), numerous AL (atomic layer) processes, 3D / advanced packaging, patterning efficiency, and complexity.  The electronic materials landscape is changing: the supply chain is merging, and there are new entrants (esp. from Korea, Taiwan & China) in advanced materials such as photoresists. Interestingly, China appears to be focusing more on investing in fabless than fabs.

Duncan Meldrum, Hilltop Economics, said that the current subdued market growth (3% 2013-16) is due to more fiscal responsible people. China & Asia are growing 4 to 7.7%, US & Latin America about 2.1 to 3.1, Euro <2%, and Japan ~1.5%.  The tax increase in Japan is having a very negative impact. He expects the US to see a 5% year over year improvement (very good news) with our investments finally growing in 2nd half of 2014.  He anticipates healthy, but not stellar consumer spending through 2016.

Patrick Ho, Stifel Nicolas, initially discussed that for companies that follow Moore’s Law, that it is increasingly Fab capital intensity (Capex) with addition of FinFETs, new materials (e.g. High k), 3D NAND, and Multi-Patterning (from delayed EUV).  One can assume this will continue to be the case as CMOS devices moves from Si channel to replacement channel filled with SiGe, Ge, or III-V and memories move to new technologies such as ReRAM, STTRAM, etc.  His observation is that only Intel is pulling for 450mm, and if TSMC & Samsung don’t exert more pull, 450mm may not happen (esp. in light of the negative impact to equipment revenue per square inch of silicon).  The top 4 OEMs (ASML, KLA-T, Lam, AMAT) are large enough to push back on the top 3 IC makers, and that consolidation is continuing.  Patrick noted that all 4 top OEMs have dividends, and he anticipates that they will eventually get better valuations.  He showed a nice list of companies he thinks are acquisition candidates (CMC, Nanometrics, Nikon, Nova, Axcelis, Rudolph, Veeco, FormFactor, and Ultratech).  Other comments:  Moore’s law lives, but is under stress.  Innovation w/ or w/o EUV will bring industry back to Moore’s Law.  Changing landscape will help economics of leading players.

Ross Kozarsky, who leads Lux Research’s advanced materials team, discussed the longer range materials he investigates such as graphene, 3D printing, and Meta-materials. Graphene film sheets are of interest for transparent conductive materials (e.g. touchscreens), possibly moving to FETs & sensors.  3D printing has been around 30 yrs; today it’s used mostly for prototyping, but manufacturing use makes sense and could really increase total growth.  Multifunctional and multi-materials printers will be needed.  Autonomous cars are now a big growth opportunity, opening great opportunity for chemical and material companies to innovate.

Geraud Duboix, IBM Almaden, develops porous low k materials for interconnect passivation and their integration (esp. plasma damage).  In the 0.65 to 0.1um timeframe, interconnect RC delay was slowing devices even though the transistors were getting faster, and thus began the drive for lower k insulators.  The ITRS has been showing the need for lower k since its inception, but it also has pushed out the date of the more aggressive low ks.  Initially to achieve lower k, C and F were added to SiO2 to break-up network structure.  Today, they are driving low k down by adding porosity.  Once a big concern, Geraud said that ULK mechanical properties are now no longer a concern with UV treatment, the lowest k being integrated is 2.3-2.4, and new low k materials are emerging. Geraud is working on porous low k materials, to achieve lower k, and larger pores deliver lower k.  He discussed the various pore-sizes in evaluation, the importance of porogens (material in the low k deposition that is later removed to create pores) and methods being used to seal the created pores (especially before conformal barrier metal deposition).  Interestingly, he commented that creating and sealing the larger pores is somewhat easier, although he’s being asked to work on the smaller pores for now.  During the panel discussion Mansour Moinpour (Intel) asked why Geraud was working on smaller pores that are more difficult to fill. Geraud responded that for the designers insulators with 2.0 or 1.8 k would be too big a change and they want 2.4 and 2.2 first.

Todd Younkin, from Intel’s central research (components) novel materials group, discussed that the industry will continue CMOS Scaling through 7nm. As stated by others, lithography is a challenge and using several methods to accomplish patterning, while productivity and pattern placement (alignment) are concerns.  Intel is working on devices with channels of higher mobility materials that Si (III-V or MoS2) as well as beyond CMOS (e.g., GAA) devices.  Todd said that early in device research development, Intel works to make sure manufacturing should be capable of meeting cost expectations. These include the cost of multi-patterning versus EUV, ultra-low k interconnect materials, etc.

Angela Franklin, of TriQuint (recently renamed Qorvo) discussed the challenges of supply management (and unlike others, she projects well when talking, so we could avoid the audio system problems … thanks Angela!).  Angela educated the audience about Qorvo devices (some look more like MEMS with permanent epoxy “cavity” structures that resonate w/ the RF) which are significantly different from the leading edge logic and non-volatile most of us follow.  Unlike the device manufactures that use Si, Qorvo uses smaller substrates of III-V and GaN.  Many films are already on the substrates when purchased.  The fab process is very solvent intensive, and only 1/3 aqueous.  Unlike others, Qorvo uses significant eBeam lithography with up to 28 different resists and many negative resists, as well as metal lift-off (my first job at IBM >30 yrs ago).

Prof. Philip Wong of Stanford gave his typical dynamic and mind-stretching presentation. His discussion was focused on the single digit nodes, and the possible new channel materials for logic (III-V or 2D MoS2, MoSe2, WSe2, WTe2 or ??) and possible new devices, including carbon nanotube FET (CNFET), STTRAM, CBRAM, ReRAM (using HfOx, TaOx, TiOx).  He said that memory chips will hold 32Tbits.  He then smiled and said “none of this before the next 10 years”.  He showed some exciting interleaved memory and logic ideas using a base of 2D or 3D FETs, topped by STTRAM, then 2D or 3D FETs, and then 3D RRAM.  Because the interconnects of the bottom device are present, all processing for the others must be at low temperature (<400C).

Discussion Panel.  When asked about collaboration with materials suppliers, Intel and IBM research had significantly different responses.  Intel invests dollars and works with graduate students on advanced projects and hopefully a “lucky accident” brings advances.  IBM research mentioned that legal issues often get in the way of collaboration with suppliers.

Notes for SMC Day 2 2014 Blog

Tim Hendry, from Intel’s supply management team started off day 2.  A large concern he brought up was what he described as the widening connections between fab, material suppliers, and sub-suppliers.  He then discussed the concerns and possible ways to improve connections, as well as the importance of metrology and verification of chemical quality.  Unfortunately, some of the sub-suppliers are very big chemical companies that have difficulty getting excited about the low volume materials used to make ICs.  He finished up by saying that Intel is focused on controlling the costs of manufacturing that require close partnerships with materials suppliers. Intel is driving for unprecedented collaboration among the materials and sub tier suppliers to achieve cost, performance and defect targets.  The cost of packaging and shipping materials globally is driving investigation into new operating models to cut costs.

Dennis Hausmann of LamRC/NVLS discussed ALD/CVD in more details than others.  For Each CVD/ALD step, an average of $2-$3/wafer is added to manufacturing cost, while only about $1/wafer of this is for chemistry+power+exhaust management.  He reviewed at least 4 versions of ALD tools (furnaces to single wafer) and said that there is a “right ALD tool” for the right deposition job.  He said that single wafer tools with proper development can meet same throughput as batch furnaces.  However, if you look at the development cost, single wafer tools are much better in cost.  For depositions that improve with plasma ALD, single wafer tools also make sense.  An important observation by Dennis was that for ALD, sometimes it is the unknown contaminant that “makes it go”.  This is something that has been observed in the past of copper plating chemistries, as well as some CMP slurries.

James ONeil, CTO Entegris had an interesting title, which should fit most suppliers “Accelerating yield in a disruptive environment”.  James emphasized that suppliers need meaningful process discussions, insights & collaboration with their customers.

Adrienne Pierce of Edwards introduced SCIS collaboration to most of us.  This is a supply chain collaboration working group.  Some topics are tracing defects origins and BKMs for specific process (e.g. ALD).

There were then two parallel sessions; one on advanced memories and the other on 3D packaging.  In the memory session, Norma Sosa of IBM talked about PCRAM (phase change memory, which Micron has been shipping for a few years now), Mark Raynor, Matheson, discussed RRAM for Non-Volatile, and Suresh Upa, SanDisk, discussed packaging implications.

After the breakout, we had presentations from four materials supplier companies.  The four same very similar things.  Dave Bern of Dow Chemical discussed using the “right tool” for collaboration and the importance of making sure suppliers agree to work in areas that fit their “core competencies”.  Wayne Mitchel of Air Products noted that ICs are only 2% of GDP.  He agreed with Dave Bern that suppliers should only agree to work (partner) with customer on areas within expertise, otherwise it takes too much time and money to execute successfully. Jean Marc Girard, Air Liquide discussed the numerous risks of supply chain, from the sub-supplier, the environment (e.g. earthquakes), and materials stability (or lack thereof). Kevin O’Shea of SAFC Hitech emphasized that taking materials from a catalog of low volume and ramping to IC manufacturing needs is not trivial, and may also not be consistent with the materials manufacturer (the sub-supplier, or company that is “primary” in the materials).

The day 2 Panel discussion had more audience participation.  Some discussions I found particularly interesting are discussed below.

Tim (Intel) said the gap is getting wider between Intel, suppliers, sub-suppliers (esp. customs for IC industry). The large sub-supplier that doesn’t have an interest in moving forward – there is no motivation to increase metrology, metrics, etc.  The shrinking sub-supplier base isn’t good for our industry – reduction in cost per bit comes from shrinks and reuse of capital, not only lower cost materials..

Kurt Carlson said that sub suppliers don’t think IC fabrication is the best industry – the IC industry wants more and more, yet wants to pay less and less.  It’s not worth it to us (good sub-suppliers leave because it’s too costly for the small volumes).

Jean Marc said they don’t want to duplicate development costs, if they don’t need to; they would rather use universities and share on things like toxicology.

Dave said it costs millions of dollars to test materials, like EUV.

Mansour Moinpour asked about collaboration on liquid particle, GCMS, and similar – can we have joint & consistent measurements across the industry?  James Entegris responded that end user need to be drivers.  Jean Marc suggested that maybe SEMI standards could drive a standard of industrial analytics.

The value of roadmaps was very different to the various participants, however the idea of regulatory alignment and a roadmap related to this was generally thought to be useful.

The question of cost and logistics … there are some materials that require shipping a lot of water, which adds cost.  Intel said that they are getting into more cost sensitive mobile market and they may be driven to this rather than exact materials copy in near future.  Tim said the Intel CEO is “hell bent” that Intel will make money in the mobile market.  “Intel will pull it off.”

Solid State Watch: May 9-15, 2014

Friday, May 16th, 2014
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The Week in Review: April 11, 2014

Friday, April 11th, 2014

The Semiconductor Industry Association announced that worldwide sales of semiconductors reached $25.87 billion for the month of February 2014, an increase of 11.4 percent from February 2013 when sales were $23.23 billion.

Nanoengineering researchers at Rice University and Nanyang Technological University in Singapore have unveiled a potentially scalable method for making one-atom-thick layers of molybdenum diselenide.

SEMI releases fourth quarter 2013 worldwide photovoltaic equipent market statistics report. Bookings levels improved some in the quarter to reach the highest value since the first quarter of 2012.

Using a laser to place individual rubidium atoms near the surface of a lattice of light, scientists at MIT and Harvard University have developed a new method for connecting particles.

Researchers at Johannes Gutenberg University Mainz (JGU) have achieved a major breakthrough in the development of methods of information processing in nanomagnets.

The Global Semiconductor Alliance (GSA) is celebrating 20 years of industry collaboration this year.

After the successful premier of a program to connect early-stage companies with strategic investors and venture capitalists (VCs) in the U.S., SEMI is expanding the program to Europe as part of SEMICON Europa 2014 in Grenoble, France (October 7-9).

Solid State Watch: April 4-10, 2014

Friday, April 11th, 2014
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Applied Materials rolls out new CVD and PVD systems for IGZO-based displays

Thursday, October 17th, 2013

By Pete Singer, Editor-in-Chief, Solid State Technology

Applied Materials introduced three new tools for the display market aimed at metal oxide thin film transistors. The tools, one of which is CVD and the other two PVD, employ new hardware designs and process technology that enable better film uniformity with fewer defects, and are designed for use with next generation IGZO-based thin film transistors (TFTs). The display industry is quickly switching to metal oxide TFTs and IGZO (indium gallium zinc oxide) is the material of choice.

Higher resolution LCD displays, greater than 300 dpi, require a switch from amorphous silicon designs to either metal oxide transistors or low-temperature polysilicon (LTPS), which offer higher-mobility in a smaller area (Figure 1). They also operate at lower power levels, which is important in mobile devices. Another problem with larger transistors is that they block too much of the light in the display.

LG has already begun shipping 55-inch OLED TVs using metal oxide backplanes and by 2014, all major LCD and LED display makers will have begun the switch over to metal oxide TFTs.

The advantage of metal oxide transistors over LTPS transistors is that they consume less power and are more easily scaled.

The layers in an IGZO transistor are deposited by both PVD and CVD, according to Max McDaniel, Applied Materials’ director and chief marketing officer for its display business. Figure 2 shows a cross-section of the device. “You use PVD to deposit the metal gate material (on the glass substrate), then you have an insulator over the top of the gate (GI = gate insulator in the figure). That’s deposited by PECVD. On top of that, you’ve got the active layer, which is the IGZO. This is deposited by PVD. Then you’ve an etch stop layer (ESTL in the figure) and that’s a PVD layer. Then you’ve got the source/drain, which is a metal deposited by CVD. Finally, you’ve got the passivation on the top which is a CVD layer,” McDaniel said. He noted that these interfaces between the CVD layers and the IGZO are critical. “We want to reduce the hydrogen as much as we can, so that’s what our technology helps the customer to do,” he said, adding that Applied Materials has the capability to build transistors in house and test them. “We’re able to solve some of these integration challenges before we deliver it to the customer.”

This time last year, Applied Materials introduced two new products. One offers a new design for depositing IGZO films for TFTs; the other handles bigger substrates of low temperature polysilicon (LTPS) films to help lower manufacturing costs.

The three new products now being introduced are the Applied AKT-PiVot 55K DT PVD, Applied AKT-PiVot 25K DT PVD and Applied AKT 55KS PECVD. The 55k nomenclature is a reference to the Gen 8.5 size panesl the system can handle, which are 2.2m x 2.5 m, or 55,000 cm2. DT stands for “dual track” which is new.

The AKT-55KS

The AKT-PiVot DT PVD system.

One of the key changes in the 55KS PECVD system include is related to how process gas is distributed the substrate surface. “The hundreds of thousands of holes that the gas is distributed out of – you have to customize them across the whole area of the chamber to compensate for the shape of the plasma,” McDaniel said. “It’s not just the diameter of the holes, it’s the depth of them.” A new gas deflector pre-distributes the gas before it goes into the diffuser, and support structures were added to achieve a higher degree of flatness over the 2.5 wide area.

New hardware provide better gas distribution and better uniformity.

On the PVD side, the new systems are designed specifically for IGZO. “Unlike our prior Pivot PVD system, where you want to have lots of chambers and be able to run multiple materials in different chambers, customers really want a system that just deposited the IGZO,” McDanield said. “It gets the substrates in and out quickly, so this is a compact, efficient platform that’s designed for depositing the IGZO.” The 25K system is targets displays for mobile applications. “We’re entering a whole new segment,” McDanield added.

The Pivot employs a set of rotary cathodes and targets, which act quite differently than conventional planar targets. Planar targets don’t get consumed uniformly and there can be redeposition of the material back onto the target. This redeposited material can spall off as particles. “Our technology is different,” McDaniel said. “The target is an array of rotating targets/cathodes. As they are being bombarded and consumed, you’re actually rotating the tubes in a circle and consuming them evenly throughout the deposition. The other benefit is this is a reactive process so you also have to introduce oxygen gas into the reaction. With the planar cathode, you have to introduce the gas from around the sides of the planar target. It’s hard to get it evenly over the substrate. With this array of tubes, you can introduce the process gas in between the tubes and get it uniformly distributed over the substrate,” he said. The rotary cathode employ magnets inside the tubes for uniformity enhancement.

Old-style planar (left) vs new-style rotary (right).

Material can redeposit onto planar cathodes (left) but that doesn't happen on rotray cathodes (right).

McDaniel added that presently everyone who is doing metal oxide IGZO use the etch stop (ES) structure (Figure, right), but would like to eliminate the etch stop and use a back channel etch (BCD) directly (Figure, left). “The IGZO material is very sensitive to hydrogen. What you’re trying to do is not expose it to the etching chemistry,” he said. “You put an etch stop layer on top of the IGZO, which is a CVD SiO2 process, and that protects it while you’re etching the source and drain. That adds an extra mask and extra process step. The panel makers would like to get rid of that etch stop layer and go to a back channel etch (BCE). This is where you etch the source drain directly down all the way to the IGZO and it’s unprotected. We’re not there yet, but the industry would like to see that structure developed. That’s on the roadmap for the industry.”

The display industry hopes to use a back channel etch (left), but presently uses an etch stop layer (right), which adds an extra mask and process step.

Looking forward, the holy grail for the display industry might just be the flexible display. McDaniel said flex displays will not likely be based on LCDs, but OLEDs. “For flexible OLED, you want to deposit on a flexible, non-glass substrate and then you need to encapsulate the OLEDs with something other than rigid glass.” This could require numerous thin films, which is good news for a supplier of tool deposition systems. He added that they would probably require an alternative to ITO (a commonly used transparent conductor). “There are a number of ITO replacement materials that are being looked at now, so as metal mesh, nanowires and even carbon nanotubes,” he said.