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Has SOI’s Turn Come Around Again?

Monday, October 10th, 2016

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By David Lammers, Contributing Editor

When analyst Linley Gwennap is asked about the chances that fully-depleted silicon-on-insulator (FD-SOI) technology will make it in the marketplace, he gives a short history lesson.

First, he makes clear that the discussion is not about “the older SOI,” – the partially depleted SOI that required designers to deal with the so-called “kink effect.” The FD-SOI being offered by STMicroelectronics and Samsung at 28nm design rules, and by GlobalFoundries at 22nm and 12nm, is a different animal: a fully depleted channel, new IP libraries, and no kink effect.

Bulk planar CMOS transistor scaling came to an end at 28nm, and leading-edge companies such as Intel, TSMC, Samsung, and GlobalFoundries moved into the finFET realm for performance-driven products, said Gwennap, founder of The Linley Group (Mountain View, Calif.) and publisher of The Microprocessor Report, said,

While FD-SOI at the 28nm node was offered by STMicrelectronics, with Samsung coming in as a second source, Gwennap said 28nm FD-SOI was not differentiated enough from 28nm bulk CMOS to justify the extra design and wafer costs. “When STMicro came out with 28 FD, it was more expensive than bulk CMOS, so the value proposition was not that great.”

NXP uses 28nm FD-SOI for its iMX 7 and iMX 8 processors, but relatively few other companies did 28nm FD-SOI designs. That may change as 22nm FD-SOI offers a boost in transistor density, and a roadmap to tighter design rules.

“For planar CMOS, Moore’s Law came to a dead end at 28nm. Some companies have looked at finFETs and decided that the cost barrier is just too high. They don’t have anywhere to go; for a few years now those companies have been at 28nm, they can’t justify the move on to finFETs, and they need to figure out how they can offer something new to their customers. For those companies, taking a risk on FD-SOI is starting to look like a good idea,” he said.

A cautious view

Joanne Itow, foundry analyst at Semico Research (Phoenix), also has been observing the ups and downs of SOI technology over the last two decades. The end of the early heyday, marked by PD-SOI-based products from IBM, Advanced Micro Devices, Freescale Semiconductor, and several game system vendors, has led Itow to take a cautious, Show-Me attitude.

“The SOI proponents always said, ‘this is the breakout node,’ but then it didn’t happen. Now, they are saying the Fmax has better results than finFETs, and while we do see some promising results, I’m not sure everybody knows what to do with it. And there may be bottlenecks,” such as the design tools and IP cores.

Itow said she has talked to more companies that are looking at FD-SOI, and some of them have teams designing products. “So we are seeing more serious activity than before,” Itow said. “I don’t see it being the main Qualcomm process for high-volume products like the applications processors in smartphones. But I do see it being looked at for IoT applications that will come on line in a couple of years. And these things always seem to take longer than you think,” she said.

Sony Corp. has publicly discussed a GPS IC based on 28nm FD-SOI that is being deployed in a smartwatch sold by Huami, a Chinese brand, which is touting the long battery life of the watch when the GPS function is turned on.

GlobalFoundries claims it has more than 50 companies in various stages of development on its 22FDX process, which enters risk production early next year, and the company plans a 12nm FDX offering in several years.

IP libraries put together

The availability of design libraries – both foundation IP and complex cores – is an issue facing FD-SOI. Gwennap said GlobalFoundries has worked with EDA partners, and invested in an IP development company, Invecas, to develop an IP library for its FDX technology. “Even though GlobalFoundries is basically starting from scratch in terms of putting together an IP library, it doesn’t take that long to put together the basic IP, such as the interface cells, that their customers need.

“There is definitely going to be an unusual thing that probably will not be in the existing library, something that either GlobalFoundries or the customers will have to put together. Over time, I believe that the IP portfolio will get built out,” Gwennap said.

The salaries paid to design engineers in Asia tend to be less than half of what U.S.-based designers are paid, he noted. That may open up companies “with a lower cost engineering team” in India, China, Taiwan, and elsewhere to “go off in a different direction” and experiment with FD-SOI, Gwennap said.

Philippe Flatresses, a design architect at STMicro, said with the existing FDSOI ecosystem it is possible to design a complete SoC, including processor cores from ARM Ltd., high speed interfaces, USB, MIPI, memory controllers, and other IP from third-party providers including Synopsys and Cadence. Looking at the FD-SOI roadmap, several technology derivatives are under development to address the RF, ultra-low voltage, and other markets. Flatresses said there is a need to extend the IP ecosystem in those areas.

Wafer costs not a big factor

There was a time when the approximately $500 cost for an SOI wafer from Soitec (Grenoble, France) tipped the scales away from SOI technology for some cost-sensitive applications. Gwennap said when a fully processed 28nm planar CMOS wafer cost about $3,000 from a major foundry, that $500 SOI wafer cost presented a stumbling block to some companies considering FD-SOI.

Now, however, a fully-processed finFET wafer costs $7,000 or more from the major foundries, Gwennap said, and the cost of the SOI wafer is a much smaller fraction of the total cost equation. When companies compare planar FD-SOI to finFETs, that $500 wafer cost, Gwennap said, “just isn’t as important as it used to be. And some of the other advantages in terms of cost savings or power savings are pretty attractive in markets where cost is important, such as consumer and IoT products. They present a good chance to get some key design wins.”

Soitec claims it can ramp up to 1.5 million FD-SOI wafers a year with its existing facility in 18 months, and has the ability to expand to 3 million wafers if market demand expands.

Jamie Schaeffer, the FDX program manager at GlobalFoundries, acknowledges that the SOI wafers are three to four times more expensive than bulk silicon wafers. Schaeffer said a more important cost factor is in the mask set. A 22FDX chip with eight metal layers can be constructed with “just 39 mask layers, compared with 60 for a finFET design at comparable performance levels.” And no double patterning is required for the 22FDX transistors.

Technology advantages claimed

Soitec senior fellow Bich-Yen Nguyen, who spent much of her career at Freescale Semiconductor in technology development, claims several technical advantages for FD-SOI.

FD-SOI has a high transconductance-to-drain current ratio, is superior in terms of the short channel effect, and has a lower fringing and effective capacitance and lower gate resistance, due partly to a gate-first process approach to the high-k/metal gate steps, Nguyen said.

Back and forward biasing is another unique feature of FD-SOI. “When you apply body-bias, the fT and fmax curves shift to a lower Vt.  This is an additional benefit allowing the RF designer to achieve higher fT and fmax at much lower gate voltage (Vg) over a wider Vg range.  That is a huge benefit for the RF designer,” she said. Figure 1 illustrates the unique benefit of back-bias.

Figure 1. The unique benefit of back-bias is illustrated. Source: GlobalFoundries.

“To get the full benefit of body bias for power savings or performance improvement, the design teams must consider this feature from the very beginning of product development,” she said. While biasing does not require specific EDA tools, and can be achieve with an extended library characterization, design architects must define the best corners for body bias in order to gain in performance and power. And design teams must implement “the right set of IPs to manage body biasing,” such as a BB generator, BB monitors, and during testing, a trimming methodology.

Nguyen acknowledged that finFETs have drive-current advantages. But compared with bulk CMOS, FD-SOI has superior electrostatics, which enables scaling of analog/RF devices while maintaining a high transistor gain. And drive current increases as gate length is scaled, she said.

For 14/16 nm finFETs, Nguyen said the gate length is in the 25-30 nm range. The 22FDX transistors have a gate length in the 20nm range. “The very short gate length results in a small gate capacitance, and total lower gate resistance,” she said.

For fringing capacitance, the most conservative number is that 22nm FD-SOI is 30 percent lower than leading finFETs, though she said “finFETs have made a lot of progress in this area.”

Analog advantages

It is in the analog and RF areas that FD-SOI offers the most significant advantages, Nguyen said. The fT and fMAX of 350 and 300 GHz, respectively, have been demonstrated by GlobalFoundries for its 22nm FD-SOI technology. For analog devices, she claimed that FD-SOI offers better transistor mismatch, high intrinsic device gain (Gm/Gds ratio), low noise, and flexibility in Vt tuning. Figure 2 shows how 22FDX outperforms finFETs for fT/fMax.

Figure 2. 22FDX outperforms finFETs for fT/fMax. Source: GlobalFoundries.

“FDSOI is the only device architecture that meets all those requirements. Bulk planar CMOS suffers from large transistor mismatch due to random dopant fluctuation and low device gain due to poor electrostatics. FinFET technology improves on electrostatics but it lacks the back bias capability.”

The undoped channel takes away the random doping effect of a partially depleted (doped) channel, reducing variation by 50-60 percent.

Analog designers using FD-SOI, she said, have “the ability to tune the Vt by back-bias to compensate for process mismatch or drift, and to offer virtually any Vt desired. Near-zero Vt can also be achieved in FD-SOI, which enables low voltage analog design for low power consumption applications.”

“If you believe the future is about mobility, about more communications and low power consumption and cost sensitive IoT chips where analog and RF is about 50 percent of the chip, then FD-SOI has a good future.

“No single solution can fit all. The key is to build up the ecosystem, and with time, we are pushing that,” she said.

CMOS-Photonics Technology Challenges

Friday, July 8th, 2016

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By Ed Korczynski, Sr. Technical Editor

Fig 1

While it is very easy to talk about the potential advantages of CMOS-photonic integration, the design and manufacturing of commercially competitive products has been extraordinarily difficult. It has been well-known that the cost efficiencies of silicon wafers and CMOS fab processes could theoretically be leveraged to create low-cost photonic circuitry. However, the physics of optics is quite different from the physics of electronics, and so there have been unexpected challenges in moving R&D experiments to HVM products. During the Imec Technology Forum in Brussels held this May, Joris Van Campenhout, imec program director for Optical I/O (Fig. 1) sat down with Solid State Technology to discuss recent progress and future plans.

Data centers—also known as “The Cloud”—continue to grow along with associated power-consumptions, so there are strong motivations to find cost-effective ways to replace more of the electrical switches with lower-power optical circuits. Optical connections in modern data centers do not all have the same specifications, with a clear hierarchy based on the 3D grid-like layout of rows of rack-mounted Printed Circuit Boards (PCB). The table shows the basic differences in physical scale and switching speeds required at different levels within the hierarchy.

Data centers—also known as “The Cloud”—continue to grow along with associated power-consumptions, so there are strong motivations to find cost-effective ways to replace more of the electrical switches with lower-power optical circuits. Optical connections in modern data centers do not all have the same specifications, with a clear hierarchy based on the 3D grid-like layout of rows of rack-mounted Printed Circuit Boards (PCB). The table shows the basic differences in physical scale and switching speeds required at different levels within the hierarchy.

ESTIMATED DATA CENTER REQUIREMENTS FOR OPTICAL I/O  (Source: imec)
OPTICAL CONNECTION RACK BACKPLANE PCB CHIP
DISTANCE 5-500m 0.5-3m 5-50cm 1-50mm
RELATIVE COST $$$$ $$$ $$ $
POWER/Gbps 5mW 1mW 0.5mW 0.1mW

Rack fiberoptic lines connecting the rows of rack-mounted printed-circuit boards (PCB) in data centers represent a major portion of the total investments for capital equipment, so there is a roadmap to keep the same fibers in place while upgrading the speeds of photonic transmit and receive components over time:

40GHz was standard through 2015,

100GHz upgrades in 2016,

400GHz planned by 2019, and

1THz estimated by 2022.

Some companies have tried to develop multi-mode fiber solutions, but imec is working on single-mode. The telecommunications standard for single-mode optical fiber diameter is 9 microns, while multimode today can be up to 50 microns diameter. “Fundamentally single-mode will be the most integrate-able way to try to get that fiber on to a chip,” explained Van Campenhout. “It is difficult enough to get nine micron diameter fibers to couple to sub-micron waveguides on chip.”

Backplane is the PCB-to-PCB connection within one rack, that today uses copper connections running at up to 50 GHz. Imec sees backplane applications as a possible insertion point for CMOS-Photonics, because there are approximately 10X the number of connections compared to rack applications and because the relative cost target calls for new technologies. Imec’s approach uses 56G silicon ring-modulators to shift wavelengths by 0.1% at very low power, knowingly taking on control issues with non-linearity, and high temperature sensitivity. “We’re confident that it can be done,” stated Van Campenhout, “but the question remains if the overhead can be reduced so that the costs are competitive.” The overhead includes the possible need for on-chip thin-film heaters/coolers to be able to control the temperature.

PCB level connections are being pushed by the Consortium for On-Board Optics (COBO), an industry group working to develop a series of specifications to permit the use of board-mounted optical modules in the manufacturing of networked equipment (i.e. switches, servers, etc.). The organization plans to reference industry specifications where possible and develop specifications where required with attention to electrical interfaces, pin-outs, connectors, thermals, etc. for the development of interchangeable and interoperable optical modules that can be mounted onto motherboards and daughtercards.

Luxtera is the commercial market leader for CMOS-Photonic chips used at the Rack level today, and uses ‘active alignment’ meaning that the fiber has to be lit with the laser and then aligning to the waveguides during test and during assembly. Luxtera is fabless and uses Freescale as foundry to build the chip in an established CMOS SOI process flow originally established for high performance microprocessors. The company produces 10G chips today for advanced Ethernet connections, and through a partnership with Molex ships 40G Active Optical Cables.

Chip level optical connections require breakthrough technologies such as indium-phosphide epitaxy on silicon to be able to grow the most efficient electrically-controlled optical switches, instead of having to pick-and-place discrete components aligned with waveguides. Alignment of components is a huge issue for manufacturing and test that adds inherent costs. “The main issue is getting the coupling from the chip to the fiber with low losses, since sub-micron alignment is needed to avoid a 1 dB loss,” summarized Van Campenhout.

Figure 2 shows a simplified functional schematic of a high-capacity optical communications links employing Dense Wavelength Division Multiplexing (DWDM) to combine modulated laser beams of different colors on a single-mode fiber. Luxtera is working on DWDM for increased bandwidth as is imec.

FIGURE 2: Dense Wavelength Division Multiplexing (DWDM) scheme allows multiplication of the total single-mode fiber (SMF) bandwidth by the number of laser colors used. (Source: imec)

Difficult Design

“If you have just a 1 nm variation in the waveguide width, that device’s spectral response will be proportional as a rule of thumb,” explained Van Campenhout. “We can tune for that with a heating element, but then we lose the low-power advantage.” This results in a need for different design-for-manufacturing approaches.

“When we do photonics design we have to have round features or the light will scatter. So when we do mask making we have to use different rules, and we need to educate all of our partners that we are doing photonics,” reminded Van Campenhout. “However there are EDA companies that are becoming aware of these aspect, so things are developing nicely to create a whole ecosystem to be able to build these. We have the first version of a PDK that we use for multi-product-wafer runs, so we can deliver custom chips to partners.”

Mentor Graphics is an imec partner, and the company’s Tom Daspit, marketing manager for Pyxis Design Tools, spoke with Solid State Technology about the special challenges of EDA for photonics. “You’ve now jumped off the cliff of the orthogonal design environment. Light doesn’t bend at 45° let alone 90°. On an IC it’s all orthogonal, while if it’s photonic we have to modify the interconnect so that the final design is a nice curved one.” To produce a smooth curve the EDA tools must fracture it into a small grid for the photomask, so a seemingly simple set of curves can require gigabytes in a final GDSII file.

It was about 4 years ago that some customers began asking Mentor to modify tools to be able to support photonics, and today there are customers large and small, and some are in full volume production for communications applications. “Remember when they building the old Cray supercomputers and they had to account for all wire lengths to handle signal delays, well now with photonics we need to account for waveguide lengths,” commented Daspit.

In full volume products today are likely communications chips. Customers do not typically share product plans, so not sure of applications spaces. Everybody wants to get rid of the Cu in the backpane to eliminate power consumption, but:

“The big application is photonics for sensor integration, with universities leading the way. Medical is a huge new market,” explained Daspit. “The CMOS die could be 130- down to 65nm or maybe 28nm-nm for some digital.” So there are a wide variety of future applications for CMOS-Photonics, and despite the known manufacturing challenges there are already commercial applications in communications.

—E.K.

79 GHz CMOS RADAR Chips for Cars from Imec and Infineon

Tuesday, May 24th, 2016

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By Ed Korczynski, Sr. Technical Editor

As unveiled at the annual Imec Technology Forum in Brussels (itf2016.be), Infineon Technologies AG (infineon.com) and imec (imec.be) are working on highly integrated CMOS-based 79 GHz sensor chips for automotive radar applications. Imec provides expertise in high-frequency system, circuit, and antenna design for radar applications, complementing Infineon’s knowledge from the many learnings that go along with holding the world’s top market share in commercial radar sensor chips. Infineon and imec expect functional CMOS sensor chip samples in the third quarter of 2016. A complete radar system demonstrator is scheduled for the beginning of 2017.

Whether or not fully automated cars and trucks will be traveling on roads soon, today’s drivers want more sensors to be able to safely avoid accidents in conditions of limited visibility. Typically, there are up to three radar systems in today’s vehicle equipped with driver assistance functions. In a future with fully automated cars, up to ten radar systems and ten more sensor systems using cameras or lidar (https://en.wikipedia.org/wiki/Lidar) could be needed. Short-range radar (SRR) would look for side objects, medium-range radar (MRR) would scan widely for objects up to 50m in front and in back, and long-range radar (LRR) would focus up to 250m in front and in back for high-speed collision avoidance.

“Infineon enables the radar-based safety cocoon of the partly and fully automated car,” said Ralf Bornefeld, Vice President & General Manager, Sense & Control, Infineon Technologies AG. “In the future, we will manufacture radar sensor chips as a single-chip solution in a classic CMOS process for applications like automated parking. Infineon will continue to set industry standards in radar technology and quality.”

The Figure shows the evolution of radar technology over the last decades, leading to the current miniaturization using solid-state silicon CMOS. Key to the successful development of this 79 GHz demonstrator was choosing to use 28 nm CMOS technology. Imec has been refining this technology as shown at ISSCC (isscc.org) for many years, first showing a 28nm transmitter chip in 2013, then showing a 28nm transmit and receive (a.k.a. “transceiver”) chip in 2014, and finally showing a single-chip with a transceiver and analog-digital converters (ADC) and phase-lock loops (PLL) and digital components in 2015. Long-term supply of eventual commercial chips should be ensured by using 28nm technology, which is known as a “long lived” node.

“We are excited to work with Infineon as a valuable partner in our R&D program on advanced CMOS-based 77 GHz and 79 GHz radar technology,” stated Wim Van Thillo, program director perceptive systems at imec. “Compared to the mainstream 24 GHz band, the 77 GHz and 79 GHz bands enable a finer range, Doppler and angular resolution. With these advantages, we aim to realize radar prototypes with integrated multiple-input, multiple-output (MIMO) antennas that not only detect large objects, but also pedestrians and bikers and thus contribute to a safer environment for all.”

Since the aesthetics are always important for buyers, automobile companies have been challenged to integrate all of the desired sensors into vehicles in an invisible manner. “The designers hate what they call the ‘warts’ on car bumpers that are the small holes needed for the ultrasonic sensors currently used,” explained Van Thillo in a press conference during ITF2016.

In an ITF2016 presentation, CEO Reinhard Ploss, discussed how Infineon works with industrial partners to create competitive commercial products. “When we first developed RADAR, there was a collaboration between the Tier-1 car companies and ourselves,” explained Ploss. “The key lies in the algorithms needed to process the data, since the raw data stream is essentially useless. The next generation of differentiation for semiconductors will be how to integrate algorithms. In effect, how do you translate ‘pixels’ into ‘optics’ without an expensive microprocessor?”

Evolution of radar technology over time has reached the miniaturization of 79 GHz using 28nm silicon CMOS technology. Imec is now also working on 140 GHz radar chips. (Source: imec)

—E.K.

Leti’s CoolCube 3D Transistor Stacking Improves with Qualcomm Help

Wednesday, April 27th, 2016

By Ed Korczynski, Sr. Technical Editor

As previously covered by Solid State Technology CEA-Leti in France has been developing monolithic transistor stacking based on laser re-crystallization of active silicon in upper layers called “CoolCube” (TM). Leading mobile chip supplier Qualcomm has been working with Leti on CoolCube R&D since late 2013, and based on preliminary results have opted to continue collaborating with the goal of building a complete ecosystem that takes the technology from design to fabrication.

“The Qualcomm Technologies and Leti teams have demonstrated the potential of this technology for designing and fabricating high-density and high-performance chips for mobile devices,” said Karim Arabi, vice president of engineering, Qualcomm Technologies, Inc. “We are optimistic that this technology could address some of the technology scaling issues and this is why we are extending our collaboration with Leti.” As part of the collaboration, Qualcomm Technologies and Leti are sharing the technology through flexible, multi-party collaboration programs to accelerate adoption.

Olivier Faynot, micro-electronic component section manager of CEA-Leti, in an exclusive interview with Solid State Technology and SemiMD explained, “Today we have a strong focus on CMOS over CMOS integration, and this is the primary integration that we are pushing. What we see today is the integration of NMOS over PMOS is interesting and suitable for new material incorporation such as III-V and germanium.”

Table: Critical thermal budget steps summary in a planar FDSOI integration and CoolCube process for top FET in 3DVLSI. (Source: VLSI Symposium 2015)

The Table shows that CMOS over CMOS integration has met transistor performance goals with low-temperature processes, such that the top transistors have at least 90% of the performance compared to the bottom. Faynot says that recent results for transistors are meeting specification, while there is still work to be done on inter-tier metal connections. For advanced ICs there is a lot of interconnect routing congestion around the contacts and the metal-1 level, so inter-tier connection (formerly termed the more generic “local interconnect”) levels are needed to route some gates at the bottom level for connection to the top level.

“The main focus now is on the thermal budget for the integration of the inter-tier level,” explained Faynot. “To do this, we are not just working on the processing but also working closely with the designers. For example, depending on the material chosen for the metal inter-tier there will be different limits on the metal link lengths.” Tungsten is relatively more stable than copper, but with higher electrical resistance for inherently lower limits on line lengths. Additional details on such process-design co-dependencies will be disclosed during the 2016 VLSI Technology Symposium, chaired by Raj Jammy.

When the industry decides to integrate III-V and Ge alternate-channel materials in CMOS, the different processing conditions for each should make NMOS over PMOS CoolCube a relatively easy performance extension. “Three-fives and germanium are basically materials with low thermal budgets, so they would be most compatible with CoolCube processing,” reminded Faynot. “To me, this kind of technology would be very interesting for mobile applications, because it would achieve a circuit where the length of the wires would be shortened. We would expect to save in area, and have less of a trade-off between power-consumption and speed.”

“This is a new wave that CoolCube is creating and it has been possible thanks to the interest and support of Qualcomm Technologies, which is pushing the technological development in a good direction and sending a strong signal to the microelectronics community,” said Leti CEO Marie Semeria. “Together, we aim to build a complete ecosystem with foundries, equipment suppliers, and EDA and design houses to assemble all the pieces of the puzzle and move the technology into the product-qualification phase.”

—E.K.

New MEMS Design Contest Encourages Advances in MEMS Technology

Wednesday, March 16th, 2016

Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a new MEMS Design Contest is being launched at DATE 2016. The objective of this contest is to encourage greater ingenuity with regard to the integration of MEMS devices and mixed-signal CMOS blocks. To kick off the contest, an informative session will be held in the Exhibition Theatre on Thursday, March 17, 2016 from 14:00 to 17:30 and is open to all DATE attendees free of charge.

The contest seeks companies, entrepreneurs, researchers and students from around the globe. Design teams are encouraged to propose imaginative design concepts that combine MEMS and mixed-signal technologies. The organizers will provide free training workshops to familiarize the participating teams with the design tools, design methodologies and process technologies involved.

A panel of highly experienced industry professionals and respected academics will undertake appraisal of the submissions. Each submission will be judged on the degree of innovation demonstrated in hardware and methodology, the novelty of the application and the value the design provides. Awards for the top three submissions will be presented at Cadence’s annual user conference, CDNLive EMEA 2018, in Munich and the winning team’s solution will be manufactured at X-FAB’s wafer production facilities.

“Supporting innovation and advancement in electronic design is fundamental to what this contest is all about,” said Alexander Duesener, Corporate VP EMEA of Cadence Design Systems. “Creating mixed-signal logic and MEMS designs requires a new process flow and totally new thinking. By enabling the winning design team to turn their concepts into manufactured designs, we highlight the value of MEMS and mixed-signal designs in today’s products.”

“The MEMS Design Contest calls attention to the increasing integration of MEMS and mixed-signal technologies in phones, cars and Internet of Things (IoT) devices,” said Dr. Stephen Breit, Vice President of Engineering at Coventor. “By offering design teams state-of-the-art Cadence and Coventor tools in combination with X-FAB’s latest MEMS and CMOS design kits, we hope to inspire new applications of our combined solution for efficiently designing, integrating and manufacturing MEMS and mixed-signal CMOS technologies.”

“By enabling the winning design team to turn their ideas into manufactured designs, X-FAB is highlighting the value of proven MEMS process technology and design enablement through our design kits,” added Joerg Doblaski, Director Design Support at X-FAB. “We look forward to seeing innovative designs from around the world and helping bring the best of them to life.”

For complete information on the contest and how to enter visit: http://www.cadence.com/MEMS_Design_Contest_2018

Technologies for Advanced Systems Shown at IMEC Tech Forum USA

Tuesday, July 14th, 2015

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By Ed Korczynski, Sr. Technical Editor

Luc Van den hove, president and CEO, imec opened the Imec Technology Forum – USA in San Francisco on July 13 by reminding us of the grand vision and motivation behind the work of our industry to empower individuals with micro- and nano-technologies in his talk, “From the happy few to the happy many.” While the imec consortium continues to lead the world in pure materials engineering and device exploration, they now work on systems-integration complexities with over 100 applications partners from agriculture, energy, healthcare, and transportation industries.

We are now living in an era where new chip technologies require trade-offs between power, performance, and bandwidth, and such trade-offs must be carefully explored for different applications spaces such as cloud clusters or sensor nodes. An Steegen, senior vice president process technology, imec, discussed the details of new CMOS chip extensions as well as post-CMOS device possibilities for different applications spaces in her presentation on “Technology innovation: an IoT era.” EUV lithography technology continues to be developed, targeting a single-exposure using 0.33 Numerical Aperture (NA) reflective lenses to pattern features as small as 18nm half-pitch, which would meet the Metal1 density specifications for the industry’s so-called “7nm node.” Patterning below 12nm half-pitch would seem to need higher-NA which is not an automatic extension of current EUV technology.

So while there is now some clarity regarding the pre-competitive process-technologies that will be needed to fabricate next-generation device, there is less clarity regarding which new device structures will best serve the needs of different electronics applications. CMOS finFETs using strained silicon-doped-with-Germanium Si(Ge) will eventually be replaced by gate-all-around (GAA) nano-wires (NW) using alternate-channel materials (ACM) with higher mobilities such as Ge and indium-gallium-arsenide (InGaAs). While many measures of CMOS performance improve with scaling to smaller dimensions, eventually leakage current and parasitic capacitances will impede further progress.

Figure 1 shows a summary of energy-vs.-delay analyses by imec for all manner of devices which could be used as switches in logic arrays. Spin-wave devices such as spin-transfer-torque RAM (STT-RAM) can run at low power consumption but are inherently slower than CMOS devices. Tunnel-FET (TFET) devices can be as fast or faster than CMOS while running at lower operating power due to reduced electrostatics, leading to promising R&D work.

Fig.1: Energy vs. delay for various logic switches. (Source: imec)

In an exclusive interview, Steegen explained how the consortium balances the needs of all partners in R&D, “When you try to predict future roadmaps you prefer to start from the mainstream. Trying to find the mainstream, so that customers can build derivatives from that, is what imec does. We’re getting closer to systems, and systems are reaching down to technology,” said Steegen. “We reach out to each other, while we continue to be experts in our own domains. If I’m inserting future memory into servers, the system architecture needs to change so we need to talk to the systems people. It’s a natural trend that has evolved.”

Network effects from “the cloud” and from future smart IoT nets require high-bandwidth and so improved electrical and optical connections at multiple levels are being explored at imec. Joris Van Campenhout, program director optical I/O, imec, discussed “Scaling the cloud using silicon photonics.” The challenge is how to build a 100Gb/s bandwidth in the near term, and then scale to 400G and then 1.6T though parallelism of wavelength division multiplexing; the best results to date for a transmitter and receiver reach 50Gb/s. By leveraging the existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon photonics platform enables high integration density and reduced power consumption, as well as high yield and low manufacturing cost. Supported by EDA tools including those from Mentor Graphics, there have been 7 tape-outs of devices in the last year using a Process Design Kit (PDK). When combined with laser sources and a 40nm node foundry CMOS chip, a complete integrated solution exists. Arrays of 50Gb/s structures can allow for 400Gb/s solutions by next year, and optical backplanes for server farms in another few years. However, to bring photonics closer to the chip in an optical interposer will require radical new new approaches to reduce costs, including integration of more efficient laser arrays.

Alexander Mityashin, project manager thin film electronics, imec, explained why we need, “thin film electronics for smart applications.” There are billions of items in our world that could be made smarter with electronics, provided we can use additive thin-film processes to make ultra-low-cost thin-film transistors (TFT) that fit different market demands. Using amorphous indium-gallium-zinc-oxide (a-IGZO) deposited at low-temperature as the active layer on a plastic substrate, imec has been able to produce >10k TFTs/cm2 using just 4-5 lithography masks. Figure 2 shows these TFT integrated into a near-field communications (NFC) chip as first disclosed at ISSCC earlier this year in the paper, “IGZO thin-film transistor based flexible NFC tags powered by commercial USB reader device at 13.56MHz.” Working with Panasonic in 2013, imec showed a flexible organic light-emitting diode (OLED) display of just 0.15mm thickness that can be processed at 180°C. In collaboration with the Holst Center, they have worked on disposable flexible sensors that can adhere to human skin.

Fig.2: Thin-Film Transistors (TFT) fabricated on plastic using Flat Panel Display (FPD) manufacturing tools. (Source: imec/Holst Center)

Jim O’Neill, Chief Technology Officer of Entegris, expanded on the systems-level theme of the forum in his presentation on “Putting the pieces together – Materials innovation in a disruptive environment.” With so many additional materials being integrated into new device structures, there are inherently new yield-limiting defect mechanisms that will have to be controlled. With demand for chips now being driven primarily by high-volume consumer applications, the time between first commercial sample and HVM has compressed such that greater coordination is needed between device, equipment, and materials companies. For example, instead of developing a wet chemical formulation on a tool and then optimizing it with the right filter or dispense technology, the Process Engineer can start envisioning a “bottle-to-nozzle wetted surface solution.” By considering not just the intended reactions on the wafer but the unintended reactions that can occur up-steam and down-stream of the process chamber, full solutions to the semiconductor industry’s most challenging yield problems can be more quickly found.

—E.K.

Research Alert: March 10, 2015

Tuesday, March 10th, 2015

Graphene meets heat waves

In the race to miniaturize electronic components, researchers are challenged with a major problem: the smaller or the faster your device, the more challenging it is to cool it down. One solution to improve the cooling is to use materials with very high thermal conductivity, such as graphene, to quickly dissipate heat and thereby cool down the circuits.

At the moment, however, potential applications are facing a fundamental problem: how does heat propagate inside these sheets of materials that are no more than a few atoms thick?

In a study published in Nature Communications, a team of EPFL researchers has shed new light on the mechanisms of thermal conductivity in graphene and other two-dimensional materials. They have demonstrated that heat propagates in the form of a wave, just like sound in air. This was up to now a very obscure phenomenon observed in few cases at temperatures close to the absolute zero.Their simulations provide a valuable tool for researchers studying graphene, whether to cool down circuits at the nanoscale, or to replace silicon in tomorrow’s electronics.

Quasi-Lossless Propagation

If it has been difficult so far to understand the propagation of heat in two-dimensional materials, it is because these sheets behave in unexpected ways compared to their three-dimensional cousins. In fact, they are capable of transferring heat with extremely limited losses, even at room temperature.

Generally, heat propagates in a material through the vibration of atoms. These vibrations are are called “phonons”, and as heat propagates though a three-dimensional material,, these phonons keep colliding with each other, merging together, or splitting. All these processes can limit the conductivity of heat along the way. Only under extreme conditions, when temperature goes close to the absolute zero (-200 0C or lower), it is possible to observe quasi-lossless heat transfer.

A wave of quantum heat

The situation is very different in two dimensional materials, as shown by researchers at EPFL. Their work demonstrates that heat can propagate without significant losses in 2D even at room temperature, thanks to the phenomenon of wave-like diffusion, called “second sound”. In that case, all phonons march together in unison over very long distances. “Our simulations, based on first-principles physics, have shown that atomically thin sheets of materials behave, even at room temperature, in the same way as three-dimensional materials at extremely low temperatures” says Andrea Cepellotti, the first author of the study. “We can show that the thermal transport is described by waves, not only in graphene but also in other materials that have not been studied yet,” explains Cepellotti. “This is an extremely valuable information for engineers, who could exploit the design of future electronic components using some of these novel two-dimensional materials properties.”

UT Dallas technology could make night vision, thermal imaging affordable

Engineers at The University of Texas at Dallas have created semiconductor technology that could make night vision and thermal imaging affordable for everyday use.

Researchers in the Texas Analog Center of Excellence (TxACE) in the University’s Erik Jonsson School of Engineering and Computer Science created an electronic device in affordable technology that detects electromagnetic waves to create images at nearly 10 terahertz, which is the highest frequency for electronic devices. The device could make night vision and heat-based imaging affordable.

Presently, night vision and thermal imagers are costly, in part because they are made with specialty semiconductor devices or need isolation from the environment.

The UT Dallas device is created using Schottky diodes in Complementary Metal-Oxide Semiconductor (CMOS) technology. CMOS is used to make affordable consumer electronic devices such as personal computers, game consoles and high-definition TVs. In addition to being affordable, these devices could be more easily incorporated into smartphones.

“There are no existing electronic detection systems operating in CMOS that can reach above 5 terahertz,” said Zeshan Ahmad, lead author of the work, electrical engineering doctoral candidate and a research assistant in TxACE. “We designed our chip in such a way that it can be mass produced inexpensively, has a smaller pixel and operates at higher frequencies.”

Dr. Kenneth O, professor of electrical engineering in the Jonsson School and director of TxACE, noted the time it took for the field to reach this frequency in CMOS.

“This is a truly remarkable accomplishment,” said Dr. O, holder of the Texas Instruments Distinguished Chair.

“Twenty years ago, we were struggling to build CMOS circuits operating at 1 gigahertz. Now we are building circuits working at frequencies that are 10,000 times higher.”

The device could eventually be used for imaging animals near a road while driving at night; imaging intruders in darkness; providing light for night hiking; and estimating how many people are in a room to better control heating, air conditioning and light. It also could be used for other tasks such as finding pipes covered by concrete or walls.

“This technology could provide a very superior means to use the infrared portion of the spectrum,” said Dr. Robert Doering, research strategy manager at Texas Instruments.” Electronic control of generating infrared directly from CMOS integrated circuits will enable a wide variety of important new applications.”

The next step in the research is to realize CMOS devices that can reach even higher frequencies, up to 40 terahertz.

Breakthrough in OLED technology

Organic light emitting diodes (OLEDs), which are made from carbon-containing materials, have the potential to revolutionize future display technologies, making low-power displays so thin they’ll wrap or fold around other structures, for instance.

Conventional LCD displays must be backlit by either fluorescent light bulbs or conventional LEDs whereas OLEDs don’t require back lighting. An even greater technological breakthrough will be OLED-based laser diodes, and researchers have long dreamed of building organic lasers, but they have been hindered by the organic materials’ tendency to operate inefficiently at the high currents required for lasing.

Now a new study from a team of researchers in California and Japan shows that OLEDs made with finely patterned structures can produce bright, low-power light sources, a key step toward making organic lasers. The results are reported in a paper appearing this week on the cover of the journal Applied Physics Letters, from AIP Publishing.

The key finding, the researchers say, is to confine charge transport and recombination to nanoscale areas, which extends electroluminescent efficiency roll off the current density at which the efficiency of the OLEDs dramatically decreases — by almost two orders of magnitude. The new device structures do this by suppressing heating and preventing charge recombination.

“An important effect of suppressing roll-off is an increase in the efficiency of devices at high brightness,” said Chihaya Adachi of Kyushu University, who is a co-author of the paper. “This results in lower power to obtain the same brightness.”

“For years scientists working in organic semiconductors have dreamed of making electrically-driven organic lasers,” said Thuc-Quyen Nguyen of the University of California, Santa Barbara, another co-author. “Lasers operate in extreme conditions with electric currents that are significantly higher than those used in common displays and lighting. At these high currents, energy loss processes become stronger and make lasing difficult.

“We see this work, which reduces some loss processes, as one step on the road toward realizing organic lasers,” Nguyen added.

OLEDs operate through the interaction of electrons and holes. “As a simple visualization,” Adachi said, “one can think of an organic semiconductor as a subway train with someone sitting in every seat. The seats represent molecules and the people represent energetic particles, i.e., electrons. When people board the train from one end, they have extra energy and want to go to the relaxed state of sitting. As people board, some of the seated people rise and exit the train at the other end leaving empty seats, or ‘holes,’ for the standing people to fill. When a standing person sits, the person goes to a relaxed state and releases energy. In the case of OLEDs, the person releases the energy as light.”

Production of OLED-based lasers requires current densities of thousands of amperes per square centimeter (kA/cm2), but until now, current densities have been limited by heating. “At high current densities, brightness is limited by annihilation processes,” Adachi said. “Think of large numbers of people on the train colliding into each other and losing energy in ways other than by sitting and releasing light.”

In previous work, Adachi and colleagues showed OLED performance at current densities over 1 kA/cm2 but without the necessary efficiency required for lasers and bright lighting. In their current paper, they show that the efficiency problem can be solved by using electron-beam lithography to produce finely-patterned OLED structures. The small device area supports charge density injection of 2.8 kA/cm2 while maintaining 100 times higher luminescent efficiency than previously observed. “In our device structure, we have effectively confined the entrance and exit to the middle of the train. People diffuse to the two less crowded ends of the train and reduce collisions and annihilation.”

MicroWatt Chips shown at ISSCC

Thursday, March 5th, 2015

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By Ed Korczynski, Sr. Technical Editor

With much of future demand for silicon ICs forecasted to be for mobile devices that must conserve battery power, it was natural for much of the focus at the just concluded 2015 International Solid State Circuits Conference (ISSCC) in San Francisco to be on ultra-low-power circuits that run on mere microWatts (µW). From analog to digital logic to radio-frequency (RF) chips and extending to complete system-on-chip (SoC) prototypes, silicon IC functionality is being designed with evolutionary and even revolutionary reductions in the operational power needed.

The figure shows a multi-standard 2.4 GHz radio that was co-developed by imec, Holst Centre, and Renesas using a 40nm node CMOS process. This was detailed in session 13.2 when Y.H. Liu presented “A 3.7mW-RX 4.4mW-TX Fully Integrated Bluetooth Low-Energy/IEEE802.15.4/Proprietary SoC with an ADPLL-Based Fast Frequency Offset Compensation in 40nm CMOS.” It uses a digital-intensive RF architecture tightly integrated with the digital baseband (DBB) and a microcontroller (MCU), and the digital-intensive RF design reduces the analog core area to 1.3mm2, and the DBB/MCU/SRAM occupies an area of 1.1mm2. This is an evolution of a previous 90nm RF front-end design that results in a reduced supply voltage (20 percent), power consumption (25 percent), and chip area (35 percent).

Ultra-low-power multi-standard 2.4 GHz radio compliant with Bluetooth Low Energy and ZigBee, co-developed by imec, Holst Centre, and Renesas. (Source: Renesas)

“From healthcare to smart buildings, ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life,” said Harmke De Groot, Department Director at imec. “The radio consumes the majority of the power of the total system and is one of the most critical components to enable these emerging applications. Moreover, a low-cost area-efficient radio design is an important catalyst for developing small sensor applications, seamlessly integrated into the environment. Implementing an ultra-low power radio will increase the autonomy of the sensor device, increase its quality, functionality and performance and enable the reduction of the battery size, resulting in a smaller device, which in case of wearable systems, adds to user’s comfort.”

When most ICs were used in devices and systems that were powered by line current there was no advantage to minimizing power consumption, and so digital CMOS circuits could be designed with billions of transistors switching billions of times each second resulting in sufficient brute-force power to solve most problems. With power-consumption now a vital aspect of much of the demand for future chips, this year’s ISSCC offered the following tutorials on low-power chips:

  • “Ultra Low Power Wireless Systems” by Alison Burdett of Toumaz Group (UK),
  • “Low Power Near-threshold Design” by Dennis Sylvester of University of Michigan, and
  • “Analog Techniques for Low-Power Circuits” by Vadim Ivanov of Texas Instruments.

Then on Thursday the 26th, an entire short course was offered on “Circuit Design in Advanced CMOS Technologies:  How to Design with Lower Supply Voltages.” with lectures on the following:

  • “A Roadmap to Lower Supply Voltages – A System Perspective” by Jan M. Rabaey of UC Berkeley,
  • “Designing Ultra-Low-Voltage Analog and Mixed-Signal Circuits” by Peter Kinget of Columbia University,
  • “ACD Design in Scaled technologies” by Andrea Baschirotto of University of Milan-Bicocca, and
  • “Ultra-Low-Voltage RF Circuits and Transceivers” by Hyunchoi Shin of Kwangwoon University.

µW SoC Blocks

Session 5.10 covered “A 4.7MHz 53µW Fully Differential CMOS Reference Clock Oscillator with -22dB Worst-Case PSNR for Miniaturized SoCs” by J. Lee et al. of the Institute of Microelectronics (Singapore) along with researchers from KAIST and Daegu Gyeongbuk Institute of Science and Technology in Korea. While many SoCs for the IoT are intended for machine-to-machine networks, human interaction will still be needed for many applications so session 6.7 covered “A 2.3mW 11cm-Range Bootstrapped and Correlated-Double-Sampling (BCDS) 3D Touch Sensor for Mobile Devices” by L. Du et. al. from UCLA (California).

As indicated by the low MHz speed of the clock circuit referenced above, the only way that these ICs can consume 1/1000th of the power of mainstream chips is to operate at 1/1000th the speed. Also note that most of these chips will be made using 90nm- and 65nm-node fab processes, instead of today’s leading 22nm- and 14nm-node processes, as evidenced by session 8.3 covered “A 10.6µA/MHz at 16MHz Single-Cycle Non-Volatile Memory-Access Microcontroller with Full State Retention at 108nA in a 90nm Process” by V.K. Singhal et al. from the Kilby Labs of Texas Instruments (Bangalore, India). Session 18.3 covered “A 0.5V 54µW Ultra-Low-Power Recognition Processor with 93.5% Accuracy Geometric Vocabulary Tree and 47.5 Database Compression” by Y. Kim et al. of KAIST (Daejeon, Korea).

In the Low Power Digital sessions it was natural that ARM Cortex chips were the basis for two different presentations on ultra-low power functionality, since ARM cores power most of the world’s mobile processors, and since the RISC architecture of ARM was deliberately evolved for mobile applications. Session 8.1 covered “An 80nW Retention 11.7pJ/Cycle Active Subthreshold ARM Cortex-M0+ Subsystem in 65nm CMOS for WSN Applications” by J. Myers et al. of ARM (Cambridge, UK). In the immediately succeeding session 8.2, W. Lim et al. of the University of Michigan (Ann Arbor) presented on the possibilities for “Batteryless Sub-nW Cortex-M0+ Processor with Dynamic Leakage-Suppression Logic.”

nW Beyond Batteries

Session 5.4 covered “A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-Low Power Systems” by A. Shrivastava et al. of PsiKick (Charlottesville, VA). PsiKick’s silicon-proven ultra-low-power wireless sensing devices are based on over 10 years of development of Sub-Threshold (Sub-Vt) devices. They are claimed to operate at 1/100th to 1/1000th of the power budget of other low-power IC sensor platforms, allowing them to be powered without a battery from a variety of harvested energy sources. These SoCs include full sensor analog front-ends, programmable processing and memory, integrated power management, programmable hardware accelerators, and full RF (wireless) communication capabilities across multiple frequencies, all of which can be built with standard CMOS processes using standard EDA tools.

Extremely efficient energy harvesting was also shown by S. Stanzione et al. of Holst Centre/ imec/KU Leuven working with OMRON (Kizugawa, Japan) in session 20.8 “A 500nW Battery-less Integrated Electrostatic Energy Harvester Interface Based on a DC-DC Converter with 60V Maximum Input Voltage and Operating From 1μW Available Power, Including MPPT and Cold Start.” Such energy harvesting chips will power ubiquitous “smarts” embedded into the literal fabric of our lives. Smart clothes, smart cars, and smart houses will all augment our lives in the near future.

—E.K.

5nm Node Needs EUV for Economics

Thursday, January 29th, 2015

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By Ed Korczynski, Sr. Technical Editor

#mce_temp_url#

At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.

Fig. 1: Panelists discuss future IC manufacturing and design possibilities in San Francisco on December 16, 2014. (Source: Pete Singer)

Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:

  • Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
  • Michael Guillorn, Ph.D. – research staff member, IBM,
  • Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
  • Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
  • Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.

Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.

Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.

Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm:  gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.

Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.

Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:

  1. everything is an interface requiring precision materials engineering,
  2. film depositions are either atomic-layer or selective films or even lattice-matched,
  3. pattern definition using dry selective-removal and directed self-assembly, and
  4. architecture in 3D means high aspect-ratio processing and non-equilibrium processing.

An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.

Fig. 2: ElectroMigration (EM) lifetimes for on-chip interconnects made with either conventional Cu or Cu lined and capped with Co, showing 10 times improvement with the latter. (Source: Applied Materials)

“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.

There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.

However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”

Solid Doping for Bulk FinFETs

Monday, January 5th, 2015

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By Ed Korczynski, Sr. Technical Editor

In another example of the old one-liner that “all that is old is new again,” the old technique of solid-source doping is being used by Intel for a critical process step in so-called “14nm node” finFET manufacturing. In the 7th presentation in the 3rd session of this year’s IEDM, a late news paper written by 52 co-authors from Intel titled “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588m2 SRAM Cell Size” disclosed that solid source doping was used under the fins.

As reported by Dick James of Chipworks in his blog coverage of IEDM this year, the fins have a more vertical profile compared to the prior “22nm node” and are merely 8nm wide (Fig. 1). Since Intel is still using bulk silicon wafers instead of silicon-on-insulator (SOI), to prevent leakage through the substrate these 8nm fins required a new process to make punch-through stopper junctions, and the new sub-fin doping technique uses solid glass sources. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over the prior node, and Idlin by 30% for NMOS and 38% for PMOS.

FIGURE: Intel Corp’s “14nm node” finFETs show (in the left SEM) 8nm wide and 42nm high fins in cross-section, below which are located the punch-through stopper junctions. (Source: IEDM 2014, Late News 3.7)

Solid glass sources of boron (B) and phosphorous (P) dopants have been used for decades in the industry. In a typical application, a lithographically defined silicon-nitride hard-mask protects areas from a blanket deposition in a tube furnace of an amorphous layer containing the desired dopant. Additional annealing before stripping off the dopant layer allows for an additional degree of freedom in activating dopants and forming junctions.

In recent years, On Semiconductor published how solid-source doping on the sidewalls of Vertical DMOS transistors enable a highly phosphorous doped path for the drain current to be brought back to the silicon surface. The company shows that phosphorous-oxy-chloride (POCl) and phospho-silicate glass (PSG) sources can both be used to form heavily doped junctions 1-2 microns deep.

The challenge for solid-source doping of 8nm wide silicon fins is how to scale processes that were developed for 1-2 microns to be able to form repeatable junctions 1-2 nm in scale. Self-aligned lithographic techniques could be used to mask the tops of fins, and various glass sources could be used. It is likely that ultra-fast annealing is needed to form stable ultra-shallow junctions.

Intel is notoriously protective of process Intellectual Property (IP) and so has almost certainly ensured that any equipment and materials suppliers who work on the solid-source doping process sign Non-Disclosure Agreements (NDA) with amendments that forbid acknowledging signing the NDA itself, so it is pointless to directly ask for any further details at this point. However, slides from John Borland’s recent presentation at the NCCAVS Junction Technology Users Group meeting provide a great overview of the publicly available information on finFET junction formation, and include the following:

…higher dopant activation can be realized at low temperatures if the junction is amorphous and recrystalized by using SPE (solid phase epitaxy) recrystalization of the junction as also shown in the data by Intel.

Also seen at IEDM this year in the 7th presentation of the Advanced Process Modules section, Taiwanese researchers—National Nano Device Laboratories, National Chiao Tung University, and National Cheng Kung University—joined with Californian consultants—Current Scientific, Evans Analytical Group—to show “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing.” They claim an ideal subthreshold swing (~60 mV/dec) at a high doping level. Poly-Si n & p JLFinFETs (W/L=10/20 nm) with SDP experimentally exhibit superior gate control (Ion/Ioff >10E6) and improved device variation.

—E.K.

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