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Posts Tagged ‘ChipWorks’

Solid Doping for Bulk FinFETs

Monday, January 5th, 2015

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By Ed Korczynski, Sr. Technical Editor

In another example of the old one-liner that “all that is old is new again,” the old technique of solid-source doping is being used by Intel for a critical process step in so-called “14nm node” finFET manufacturing. In the 7th presentation in the 3rd session of this year’s IEDM, a late news paper written by 52 co-authors from Intel titled “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588m2 SRAM Cell Size” disclosed that solid source doping was used under the fins.

As reported by Dick James of Chipworks in his blog coverage of IEDM this year, the fins have a more vertical profile compared to the prior “22nm node” and are merely 8nm wide (Fig. 1). Since Intel is still using bulk silicon wafers instead of silicon-on-insulator (SOI), to prevent leakage through the substrate these 8nm fins required a new process to make punch-through stopper junctions, and the new sub-fin doping technique uses solid glass sources. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over the prior node, and Idlin by 30% for NMOS and 38% for PMOS.

FIGURE: Intel Corp’s “14nm node” finFETs show (in the left SEM) 8nm wide and 42nm high fins in cross-section, below which are located the punch-through stopper junctions. (Source: IEDM 2014, Late News 3.7)

Solid glass sources of boron (B) and phosphorous (P) dopants have been used for decades in the industry. In a typical application, a lithographically defined silicon-nitride hard-mask protects areas from a blanket deposition in a tube furnace of an amorphous layer containing the desired dopant. Additional annealing before stripping off the dopant layer allows for an additional degree of freedom in activating dopants and forming junctions.

In recent years, On Semiconductor published how solid-source doping on the sidewalls of Vertical DMOS transistors enable a highly phosphorous doped path for the drain current to be brought back to the silicon surface. The company shows that phosphorous-oxy-chloride (POCl) and phospho-silicate glass (PSG) sources can both be used to form heavily doped junctions 1-2 microns deep.

The challenge for solid-source doping of 8nm wide silicon fins is how to scale processes that were developed for 1-2 microns to be able to form repeatable junctions 1-2 nm in scale. Self-aligned lithographic techniques could be used to mask the tops of fins, and various glass sources could be used. It is likely that ultra-fast annealing is needed to form stable ultra-shallow junctions.

Intel is notoriously protective of process Intellectual Property (IP) and so has almost certainly ensured that any equipment and materials suppliers who work on the solid-source doping process sign Non-Disclosure Agreements (NDA) with amendments that forbid acknowledging signing the NDA itself, so it is pointless to directly ask for any further details at this point. However, slides from John Borland’s recent presentation at the NCCAVS Junction Technology Users Group meeting provide a great overview of the publicly available information on finFET junction formation, and include the following:

…higher dopant activation can be realized at low temperatures if the junction is amorphous and recrystalized by using SPE (solid phase epitaxy) recrystalization of the junction as also shown in the data by Intel.

Also seen at IEDM this year in the 7th presentation of the Advanced Process Modules section, Taiwanese researchers—National Nano Device Laboratories, National Chiao Tung University, and National Cheng Kung University—joined with Californian consultants—Current Scientific, Evans Analytical Group—to show “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing.” They claim an ideal subthreshold swing (~60 mV/dec) at a high doping level. Poly-Si n & p JLFinFETs (W/L=10/20 nm) with SDP experimentally exhibit superior gate control (Ion/Ioff >10E6) and improved device variation.

—E.K.

Blog review December 16, 2014

Tuesday, December 16th, 2014

Maybe, just maybe, ASML Holding N.V. (ASML) has made the near-impossible a reality by creating a cost-effective Extreme Ultra-Violet (EUV @ ~13.5nm wavelength) all-reflective lithographic tool. The company has announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has ordered two NXE:3350B EUV systems for delivery in 2015 with the intention to use those systems in production. In addition, two NXE:3300B systems already delivered to TSMC will be upgraded to NXE:3350B performance. While costs and throughputs are conspicuously not-mentioned, this is still an important step for the industry.

The good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2014 IEEE International Electron Devices Meeting. Dick James of Chipworks writes that it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

The 4th Annual Global Interposer Technology Workshop at GaTech gathered 200 attendees from 11 countries to discuss the status of interposer technology. It has become the one meeting where you can find all the key interposer layers including those representing glass, laminate and silicon, blogs Phil Garrou.

Sharon C. Glotzer and Nicholas A. Kotov are both researchers at the University of Michigan who were just awarded a MRS Medal at the Materials Research Society (MRS) Fall Meeting in San Francisco for their work on “Integration of Computation and Experiment for Discovery and Design of Nanoparticle Self-Assembly.”

In order to keep pace with Moore’s Law, semiconductor market leaders have had to adopt increasingly challenging technology roadmaps, which are leading to new demands on electronic materials (EM) product quality for leading-edge chip manufacturing. Dr. Atul Athalye, Head of Technology, Linde Electronics, discusses the challenges.

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. Adele Hars reports.

Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.

At the recent IMAPS conference, Samsung electro-mechanics compared their Plated Mold Via Technology (PMV) to the well known Amkor Through Mold Via  (TMV) technology. The two process flows are compared. Phil Garrou reports.

Air-gaps in Copper Interconnects for Logic

Friday, October 31st, 2014

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By Ed Korczynski, Sr. Technical Editor, SST/SemiMD

The good people at ChipWorks have released some of the first public data on Intel’s new 14nm-node process, and the results indicate that materials limitations in on-chip electrical interconnects are adding costs. Additional levels of metal have been added, and complex “air-gap” structures have been added to the dielectric stack. Flash memory chips have already used air-gaps, and IBM has already used a subtractive variant of air-gaps with >10 levels of metal for microprocessor manufacturing, but this is the first known use of additive air-gaps for logic after Intel announced that a fully-integrated process was ready for 22nm-node chips.

Mark Bohr of Intel famously published data in 1995 (DOI:  10.1109/IEDM.1995.499187) on the inherent circuit speed limitations of interconnects, showing proportionality to the resistance (R) of the metal lines multiplied by the capacitance (C) of the dielectric insulation around the metal (Fig.1). The RC product thus should be minimized for maximum circuit speed, but the materials used for both the metal and the dielectric insulation around metal lines are at limits of affordability in manufacturing.

There are no materials that super-conduct electricity at room temperature, and only expensive and room-sized supercomputers and telecommunications base-stations can afford to use the liquid-nitrogen cooling that is needed for known superconductors to function. Carbon Nano-Tubes (CNT) and 2D atomic-layers of carbon in the form of graphene can conduct ballistically, but integration costs and electrical contact resistances limit use. Copper metal remains as the best electrical conductor for on-chip interconnects, yet as horizontal lines and vertical vias continue to shrink in cross-sectional area the current density has reached the limit of reliability. The result is the increase in the number of metal layers to 13 for 14nm-node Intel microprocessors, while IBM used 15 layers for 22nm-node Power8 chips.

Low-k Dielectrics and Pore Sizes

The dielectric constant (“k”) of silicon oxide is ~4, and ~3.5 with the addition of fluorine to the oxide (SiOF). Carbon-Doped Oxide (CDO or SiOC or SiOC:H) with k~3.0 has been integrated well into interconnect stacks. Some polymers can provide k values in the 2.0-2.7, but they cannot be integrated into most interconnects due to lack of mechanical strength, chemical resistance, and overall stability. Air has k=1, and there have been specialized chips made using metal wires floating in air, but lack of physical structure results in poor manufacturing yield and weak reliability.

A clever compromise is to use both SiOC with k~3 and air with k~1 in a stack, which results in an integrated k value weighted by the percent of the volume taken up by each phase. Porous Low-k (PLK) with 10% porosity allows for an integrated k of ~2.7 for modest improvement, but increasing porosity to just 20% for k~2.4 results in connected random pores that reduce reliability. To reliably integrate 20-30% air into SiOC, the pores cannot be random but must be engineered as discrete gaps in the structure.

In 2007, IBM announced that it would engineer air-gaps in microprocessors, but the company claimed to be using an extremely complex process for integration involving a self-assembled thin-film mask to anisotropically etch out holes between lines and then further isotropic etching to form elongated pores. Though relatively complex and expensive, this process allows for the use of any 2D layout for lines in a given metal layer.

Additive Air-gap Process-Design Integration

For fab lines that are still working with aluminum metal and additive dielectrics, air-gaps are a defect that occurs with imperfect dielectric fill. When not planned as part of the design, air-gaps formed in a lower-layer can be exposed to etchants during subsequent processing resulting in metal shorts or opens. However, Figure 2 shows that it is possible to engineer air-gaps by Chemical-Vapor Deposition (CVD) of dielectric material into line-space structures with proper process control and design layout restrictions. Twenty years ago, this editor worked for an OEM on CVD processes for dielectric fill, and the process can be tuned to be highly repeatable and relatively low-cost if a critical masking step can be avoided. In 1998, Shieh et al. from Stanford (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) showed proof-of-concept for this approach to lower k values.

Figure 2: CVD can be easily tuned to initially coat sidewalls (top), then pinch-off (middle), and finally form a closed pore (bottom) during one step. (Source: Ed Korczynski)

Four years ago at IEDM 2010, Intel presented details of how to engineer air-gaps using CVD. As this editor wrote at that time in an extensive analysis:

The lithographic masking step is needed for two reliability reasons. First, by excluding air-gap formation in areas near next-layer vias, alignment between layers can be more easily done. Second, wide spaces are excluded where the final non-conformal CVD step wouldnt automatically pinch-off to close the gaps; leaving full SiOC(H) in wider spaces also helps with mechanical strength. The next layer is patterned with a conventional dual-damascene flow, with the option to add air-gaps.

Now we know that Intel kept air-gaps on the metaphorical shelf by skipping use at the 22nm-node. The 2014 IEDM paper from Intel will discuss details of 14nm-node air-gaps:   two levels at 80nm and 160nm minimum pitches, yielding a 17% reduction in capacitance delays.

This process requires regularly spaced 1D line arrays as a design constraint, which may also be part of the reason for additional metal layers to allow for 2D connections through vias. Due to lithography resolution advantages with 1D “gridded” layouts, other logic fabs may soon run 1D designs at which point additive air-gaps like that used by Intel will provide a relatively easy boost to IC speeds.

Blog review August 18, 2014

Monday, August 18th, 2014

Vivek Bakshi provides a deeper look at the ASML/IBM announcement on EUV progress. ASML and IBM reconfirmed the benchmarking in press and via social media. In short, 637 wafers per day throughput stands, resulting from the successful upgrade of source power by 100%, to its targeted level of ~43 W.

Dick James of Chipworks finally has his hands on Samsung’s V-NAND vertical flash. The vertical flash was first released in an enterprise solid-state drive (SSD) last year, in 960 GB and 480 GB versions. Then in May this year they announced a second-generation V-NAND SSD, with a stack of 32 cell layers.

Phil Garrou provides an overview of controlling warpage in packaging as discussed at ECTC by Hitachi Chemical, Amkor, Qualcomm, and imec.

Anand Sundaram, Senior Associate for PwC’s PRTM Management Consulting writes that software that controls and powers embedded devices is playing a key role in making possible the highly integrated, multi-functional ‘smart’ devices we take for granted in our daily lives – from the ubiquitous smart phones/tablet to ‘smart’ home appliances and wearable electronics.

Pete Singer posted an IoT infographic, courtesy of Jabil. The global IoT market is poised for explosive growth. By 2020, the market is expected to soar to $7.1 trillion. This infographic, courtesy of Jabil, gives an good overview of what will be connected (even garbage bins!).

Bob Smith, Senior Vice President of Marketing and Business Development, Uniquify blogs that these days, chip design may seem like an intricately connected jigsaw puzzle, including small, oddly shaped interlocking pieces.


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