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Posts Tagged ‘Cadence Design Systems’

Amkor and Cadence to Develop Packaging Assembly Design Kits for Amkor’s SLIM and SWIFT Packaging Technologies

Thursday, May 5th, 2016

Amkor Technology, Inc., a outsourced semiconductor packaging and test service provider, today announced the expansion of its collaboration with Cadence Design Systems, Inc. to streamline semiconductor package verification with the joint development of a package assembly design kit (PADK) for Amkor’s SLIM and SWIFT advanced fan-out package technologies. As a leader in electronic design automation, Cadence will provide Amkor with PADK development support based on the Cadence Physical Verification System (PVS) software tool. This integrated solution allows Amkor’s customers to shorten the SLIM and SWIFT design and verification cycles.

“We’re at a critical juncture in the semiconductor industry with increased dependence on packaging solutions for delivery of next-generation products,” said Ron Huemoeller, Amkor’s corporate vice president, research and development. “The development of these PADKs, the latest outcome of our lengthy collaboration with Cadence, addresses a critical gap forming between foundry and back-end-of-line, as fan-out packaging solutions blur the lines between these processes. Based on our vast experience with advanced package design methodologies, Amkor is well positioned to lead the industry with our unique fan-out packaging technologies.”

By jointly developing Cadence PVS-based PADKs for SLIM and SWIFT technologies, Amkor and Cadence are filling the gap between semiconductor die design and package design, while refining design methodologies for advanced IC packaging fan-out technologies. Amkor’s PADKs will enable designers to meet the design requirements needed to ensure complete package-level sign-off verification for SLIM and SWIFT technologies and provide more seamless collaboration with their customers.

“To keep up with the industry’s faster-performing, lower-power and smaller form-factor device requirements, fan-out processing is now an essential part of advanced IC packaging,” said Steve Durrill, senior product engineering group director of the PCB Group at Cadence Design Systems. “Our partnership with Amkor fills a void when it comes to complete sign-off verification for this advanced IC packaging technology, helping to accelerate the adoption of SLIM and SWIFT technologies in this fast growing market segment.”

Cadence to Acquire Rocketick

Monday, April 11th, 2016

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced that it has entered into a definitive agreement to acquire Rocketick Technologies Ltd., an Israel based pioneer and leading provider of multicore parallel simulation. Rocketick’s technology accelerates Cadence Incisive® Enterprise Simulator to provide up to 6X speed-up for register-transfer-level (RTL), up to 10X speed-up for gate-level functional and up to 30X speed-up for gate-level DFT simulations using standard x86-based servers. The Rocketick solution is proven and is in use today by numerous marquee systems and semiconductor companies in the mobile, server, and graphics domains. The integration of Rocketick’s technology will serve to strengthen Cadence’s System Design Enablement strategy by delivering ultra-high-performance simulation to accelerate the development of complete systems with the consumer end-product in mind.

“Ensuring that SoC verification is completed on time within ever shrinking project schedules is driving the strong need to speed up the underlying logic simulation technology,” said Dr. Anirudh Devgan, senior vice president and general manager of the System & Verification Group and the Digital & Signoff Group at Cadence. “Rocketick is the leading, established provider of parallel simulation technology. I look forward to welcoming the Rocketick team to Cadence as we accelerate our innovation in functional verification to solve our customers’ most difficult challenges.”

Rocketick’s market-leading technology achieves linear speed-up by parallelizing simulation on standard x86-based multicore servers, providing automated partitioning across designs and testbenches, and the flexibility to direct simulations to server farm resources ranging from one to 64 cores. It also provides a significant accuracy advantage and enhanced visibility with four-state logic simulation, and reduces host memory footprint by 2-3X for gate-level designs. Rocketick’s technology works seamlessly with the Cadence Incisive Enterprise Simulator without the need to modify designs or testbenches, eliminating ramp-up time while providing accurate results at significantly accelerated speeds.

“Rocketick and Cadence serve market-leading customers whose exploding verification challenges are testing the limits of conventional simulators,” said Tomer Ben-David, CEO of Rocketick. “Rocketick’s technology has been proven to deliver as much as 30X faster simulation on very challenging designs at top tier system and semiconductor companies. We are very excited to join the Cadence team and look forward to providing even more benefit to customers through the tight integration of Rocketick’s core engines with Cadence’s overall verification solution.”

The acquisition is expected to close in the second quarter of fiscal 2016, and is not expected to have a material impact on Cadence’s fiscal 2016 results of operations. Terms of the transaction were not disclosed. Rocketick is backed by investments from Intel Capital and other strategic and financial investors. Needham & Company advised Rocketick on the transaction.

Functional Safety, Security for IoT Stressed at Cadence Event

Thursday, April 7th, 2016

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By Jeff Dorsch, Contributing Editor

Lip-Bu Tan, President and CEO, Cadence Design Systems

The “big trends” in the electronics industry are social, mobility, the Internet of Things, and security, Lip-Bu Tan, the president and chief executive officer of Cadence Design Systems, said Tuesday (April 5) in his keynote address at the CDNLive Cadence User Conference in Santa Clara, Calif.

He later touched on 5G wireless communications, Big Data, deep learning, and ultra-low-power devices, leading up to the concept of System Design Enablement, or SDE. “We have been changing the entire system design flow,” Tan told a capacity audience in the Santa Clara Convention Center’s Elizabeth A. Hangs Theatre.

The Cadence CEO described new products that have been introduced in the past year.

(The system design theme is also exemplified by the Electronic Design Automation Consortium renaming itself last month as the Electronic System Design Alliance.)

Tan was followed by Qualcomm CEO Steve Mollenkopf, who took “The Evolution of Connected Devices” as his theme.

“There’s tremendous innovation in front of us…providing technology at scale,” Mollenkopf said. Mobility and low-power technology are “disrupting multiple industries,” he added.

While growth in the smartphone market is slowing down, wider adoption of Long-Term Evolution communications and the introduction of augmented reality and virtual reality on handsets promise to buoy the smartphone business for years to come, according to Mollenkopf.

The description of automotive vehicles as “a phone on wheels” is not unjustified, the Qualcomm CEO observed. While the unit volume of the auto business is lower than smartphones and many electronics products, the process of adding connectivity and Internet service to cars is “just beginning,” he said.

While the IoT is “not the next savior for the [semiconductor] industry,” Mollenkopf said, the industrial IoT promises to generate valuable data for manufacturers. “We’re moving from discrete to integrated platforms,” he added.

Qualcomm CEO Steve Mollenkopf

Mollenkopf also addressed drone aircraft, 5G, and autonomous vehicles in his keynote.

Congratulating Cadence on its collaborations with Qualcomm, Mollenkopf concluded, “We need people to make it easy for us to use silicon.”

GlobalFoundries CEO Sanjay Jha was up next. He identified mobile computing, the IoT, and mission-critical/automotive applications as important considerations for the near future.

The IoT market could generate a low estimate of $3.9 trillion in the next decade, with high estimates topping out at $11.5 trillion, Jha said, citing IHS Technology, iSuppli, and other sources. The semiconductor industry could realize $50 billion to $75 billion in value from IoT-related products, “from chips to mini-systems,” he added.

GlobalFoundries, which last year acquired IBM Microlectronics, has identified several key technologies for its operations and foundry services: fully-depleted silicon-on-insulator, magnetic random-access memory, radio-frequency SOI and silicon germanium, system-in-package and other advanced packaging, FinFETs, and application-specific integrated circuits.

“Power consumption is the big differentiator,” Jha commented.

GlobalFoundries CEO Sanjay Jha

The 5-nanometer process node “will be a very expensive technology,” he said. Jha compared an extreme-ultraviolet lithography scanner (EUV technology is now expected to be production-ready for 5nm chips) to “a small Hadron Collider.”

The CDNLive Silicon Valley event was the first of 2016 for the EDA company. Similar conferences are scheduled this year for Germany, Korea, Japan, India, China, Taiwan, the eastern US (Boston), and Israel.

Cadence and University of Oxford Foster the Advancement of Formal Verification Innovation

Thursday, April 7th, 2016

Cadence Design Systems, Inc. (NASDAQ:  CDNS) and the University of Oxford today announced a move to foster the advancement of formal verification innovation with the appointment of Dr. Ziyad Hanna, Cadence vice president of R&D, as a visiting professor in Oxford’s Department of Computer Science for the next three years. Through Dr. Hanna’s appointment at Oxford, a globally distinguished university, Cadence further expands its Cadence® Academic Network footprint.

Dr. Ziyad Hanna, vice president of R&D at Cadence

Dr. Hanna brings more than 25 years of industry experience to Oxford. He currently leads the R&D team for the Cadence JasperGold® formal verification platform, having joined from Jasper Design Automation, which was acquired by Cadence in 2014. Before joining Jasper, Dr. Hanna was also a senior principal engineer and a group leader at Intel, working on formal property verification and equivalence checking. A senior IEEE member, he has mentored dozens of research projects, delivered many visionary talks for the industry and academia, and served in more than 50 program committees to advance academic research. Dr. Hanna has co-authored over 30 articles and holds 15 U.S. patents, and he earned both his B.Sc. and M.S. degrees in mathematics and computer science at Tel Aviv University and his D.Phil. from the University of Oxford.

Oxford’s Automated Verification Group, based in the Department of Computer Science, is one of the largest and strongest academic research groups in the field worldwide, and Cadence has one of the largest corporate investments in formal verification and formal equivalence research and development. Through this appointment, Dr. Hanna is using his real-world experience to enhance Oxford’s automated formal verification research program, while also gaining exposure to the university’s practical and industrially oriented research, which is what the Cadence Academic Network works to foster.

“The University of Oxford appoints visiting professorships to highly distinguished individuals who are regarded as world leaders in their field and can further enhance our research excellence,” said Thomas Melham, Professor of Computer Science at the University of Oxford. “The appointment of Dr. Hanna to Oxford highlights the commitment of Cadence to further the research and development of innovative technology, including formal verification. His visiting professorship provides Cadence with early insight into new academic research directions for addressing the hardest verification challenges that many chip design and system companies encounter.”

“Oxford’s work in verification spans a wide range of research, from fundamental investigations into model checking to practical, machine-assisted methods applicable to real-world design and verification problems in software and hardware systems,” said Dr. Hanna. “It’s an honor to be working with Oxford’s renowned Department of Computer Science. This appointment enables me to collaborate closely with Oxford’s leading verification researchers to tap into the university’s research, which can drive formal verification innovation and bring talented Oxford graduates to Cadence.”

Cadence Adds New Tools for Analog Design, Enhances Layout

Wednesday, April 6th, 2016

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By Jeff Dorsch, Contributing Editor

Cadence Design Systems today is introducing new tools within its Virtuoso Analog Design Environment (ADE), along with enhancements to the Virtuoso Layout Suite.

New to Virtuoso ADE are the Virtuoso ADE Explorer, Virtuoso ADE Assembler, and Virtuoso ADE Verifier.

“The new Virtuoso ADE Verifier technology and the Virtuoso ADE Assembler technology run plan capability make our design teams more productive,” said Yanqiu Diao, deputy general manager of the Turing Processor business unit at HiSilicon Technologies Co., Ltd. “Through our early use of the new Cadence Virtuoso ADE product suite, we’ve found that we can improve analog IP verification productivity by approximately 30 percent and reduce verification issues by one-half. Our smartphone and network chip projects should benefit from these latest capabilities.”

Steve Lewis, product marketing director for Cadence’s Custom IC & PCB Group, said the electronic design automation company’s Virtuoso ADE L, XL, and GXL tools “will be kept, will be maintained, and taking that technology to the next level.”

Virtuoso ADE Verifier is “the brand-new kid on the block,” Lewis said in an interview. The tool advances analog verification technology, according to Cadence, and offers an integrated dashboard for engineers to employ.

Under international standards for automotive vehicles, medical equipment, military/aerospace systems, and other products, suppliers “have to trace every aspect of your design,” he noted. “All has to be documented.”

The digital side of chip design addressed those issues about a decade ago, according to Lewis. Such recordkeeping and documentation are “far less common on the analog,” he said. “It’s no longer okay to say the analog takes care of itself.”

Changes in analog design projects were typically tracked in spreadsheet programs, which don’t connect to the Virtuoso suite, Lewis noted, adding, “Now, I know who’s working on what.”

The new analog design tools “add a little bit more granularity” with real-number models, Lewis said. “It’s not quite SPICE,” he admitted.

Regarding Virtuoso ADE Assembler, “we made it look like ADE XL,” Lewis said, so users should have a shorter learning curve with the new tool. Virtuoso ADE Explorer provides what Cadence calls a complete corners and Monte Carlo environment for finding and correcting variation problems.

Cadence is also offering a Virtuoso Variation Option, providing fast Monte Carlo analysis for FinFET chips with 16-nanometer or smaller dimensions.

The enhancements in Virtuoso Layout Suite are a 10x to 100x improvement in graphics rendering performance, real-time customization of Module Generators with a simpler and more visual approach; and new structured device-level routing capabilities that are said to enhance routing productivity by up to 50 percent.

“We actually made significant changes in layout for L, XL,” addressing “current techniques, current designs,” Lewis commented.

Cadence Virtuoso Analog Design Environment (ADE): Reimagining analog design with emphasis on usability, performance, and innovation

Goodbye, EDAC; Hello, ESD Alliance

Friday, April 1st, 2016

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By Jeff Dorsch, Contributing Editor

The Electronic Design Automation Consortium (EDAC) is no more. The industry organization, founded in 1989, is changing its name to the Electronic System Design Alliance, or ESD Alliance.

The name change is being accompanied by an expansion of the organization’s charter. Having taken on semiconductor intellectual property several years ago, the ESD Alliance will also address advanced packaging and embedded software, according to Robert Smith, who took over last year as executive director of EDAC. The ESD Alliance will also welcome service companies that offer design know-how and resources.

The alliance’s launch was marked by an evening event on Wednesday (March 30) at the SEMI headquarters in San Jose, Calif., where the ESD Alliance has its offices. In attendance at the social gathering were several EDAC directors, including Simon Segars, chief executive officer of ARM Holdings; Wally Rhines, chairman and CEO of Mentor Graphics; Lip-Bu Tan, president and CEO of Cadence Design Systems; and Aart de Geus, chairman and co-CEO of Synopsys.

“We’re part of this large ecosystem,” Bob Smith said Wednesday evening, adding, “Semiconductors – they need design.” He recognized by name many of the people involved in EDAC and now the ESD Alliance.

A slide presentation at the event began with “Kingdom of Rain,” by The The, segueing to “Love Shack” by the B-52’s – two songs dating to 1989, the year EDAC was formed. That also was the year Taylor Swift was born, one slide noted.

In 2016, marked musically by Mark Ronson’s “Uptown Funk” in the slide show, the ESD Alliance is taking the place of the EDA Consortium.

TSMC Readies 7nm Chip Ecosystem, Infrastructure for 2017

Wednesday, March 16th, 2016

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By Jeff Dorsch, Contributing Editor

Taiwan Semiconductor Manufacturing Company came to Silicon Valley on Tuesday for a day of presentations on its latest chip technology. The TSMC Technology Symposium for North America drew more than 1,000 attendees at the San Jose Convention Center.

The world’s largest silicon foundry led off the day with a pair of announcements: ARM Holdings and TSMC said they would collaborate on 7-nanometer FinFET process technology for ultra-low-power high-performance computing (HPC) system-on-a-chip devices, building on their previous experience with 16nm and 10nm FinFET process technology, while MediaTek and TSMC extended their partnership to develop Internet of Things and wearable electronics products, using the IC design house’s MT2523 chipset for fitness smartwatches, introduced in January and fabricated with TSMC’s 55nm ULP process.

TSMC’s work with ARM on the 16nm and 10nm nodes employed ARM’s Artisan foundation physical intellectual property, as will their 7nm efforts.

On Tuesday afternoon, the hundreds of attendees heard first from BJ Woo, TSMC’s vice president of business development, on the company’s advanced technology, including its moves toward supporting radio-frequency IC (RFIC) designs for smartphone chips and other areas of wireless communications.

“Cellular RF and WLAN are RF technology drivers,” she said. Looking toward 4G LTE Carrier Aggregation, TSMC began offering its 28HPC RF process to customers in late 2015 and will roll out the 28HPC+ RF process in the second quarter of this year, Woo added.

TSMC has won 75 percent of the business for RFIC applications, she asserted.

The foundry will start making 10nm FinFET chips for flagship smartphones and “phablets” this year, with 7nm FinFET devices for those products in 2017, according to Woo.

The business development executive also touted the company’s “mature 28-nanometer processes,” the 28HPC and 28HPC+, saying they are “rising in both volume and customer tape-outs.”

TSMC has been shipping automotive chips meeting industry standards since 2014, Woo noted, primarily for advanced driver assistance systems (ADAS) and infotainment electronics. The foundry is now working on vehicle control technology, employing microcontrollers.

The company’s 16FF+ process has been used in 50 customer tape-outs, Woo said. “Many have achieved first-silicon success,” she added. TSMC is putting its 16FFC process into volume production during this quarter.

“Automotive will be the [semiconductor] industry focus,” Woo predicted.

She also spoke about the company’s MD2 local interconnect technology, its 1D back-end-of-line process, and its spacer BEOL process.

Regarding 7nm chips, Woo said the company will offer two “tracks” of such chips, for high-performance computing and mobile applications. “Both will be available at the same time,” she said.

Most of the semiconductor production equipment being used for fabrication of 10nm chip will also be used for 7nm manufacturing, according to Woo. Those 7nm chips will be 10 to 15 percent faster than 10nm chips, while reducing power consumption by 35 to 40 percent, she said.

Risk production of 7nm chips will begin one year from now, in March of 2017, she said.

Suk Lee, senior director of TSMC’s Design Infrastructure Marketing Division, reported on development of electronic design automation (EDA) products for the 16nm node and beyond.

“Low-power solutions are ready,” he said of the foundry’s 16FFC process. IP is available to use with 16FFC for automotive, IoT, HPC, and mobile computing applications, he noted.

Lee reviewed what the company’s EDA partners – Mentor Graphics, Synopsys, Cadence Design Systems, ANSYS, and ATopTech – have available for 10nm chip design and verification.

Design and manufacturing of 7nm chips will involve cut-metal handling and multiple patterning, according to Lee. “We’ve used this technology on 16 nanometer and previous generations,” he said of cut-metal handling.

TSMC will support multiple SPICE simulators, having developed hybrid-format netlist support, Lee said. Pre-silicon design kits for 7nm chips will be available in the third quarter of 2016, he added.

The TSMC9000 Program for automotive/IoT products will be “up and running” in Q3 of this year, providing “automotive-grade qualification requirements in planning,” he said.

Lee also spoke about the foundry’s offerings in 3D chips, featuring “full integration of packaging and IC design” with TSMC’s InFO technology. The HBM2 CoWoS design kit will be out in the second quarter of 2016, he said. “We’re very excited about that,” Lee added.

George Liu, senior director of TSMC’s Sensor & Display Business Development, said, “The Internet of Things will drive the next semiconductor growth.” When it comes to the IoT and the Internet of Everything, “forecasts are all over the map,” he noted.

Taking diversification as his theme, Liu said TSMC’s specialty technology will help bridge the connection between the natural world and the computing cloud. First there is the “signal chain” of analog chips and sensors, leading to the “data chain” of connectivity, he said.

Liu reviewed a wide variety of relevant technologies, such as CMOS image sensors, microelectromechanical system (MEMS devices, embedded flash memories, biometrics, touch and display technology, and power management ICs.

At the all-day conference, which included an ecosystem exhibition by partner companies, TSMC emphasized its readiness to take on 28nm, 16nm, 10nm, and 7nm chip designs, along with the more mature process technologies. It’s game on for the foundry business.

Cadence Debuts Product for Reducing Test Time, Costs

Tuesday, February 2nd, 2016

By Jeff Dorsch, Contributing Editor

Cadence Design Systems is introducing the Modus Test Solution, a product that it touts as capable of reducing IC testing time and test costs, while improving profit margins for chips.

Modus shares a Tcl scripting and debugging environment with Cadence’s Genus Synthesis Solution, Innovus Implementation Solution, and Tempus Timing Signoff Solution, according to the company.

Its other capabilities include 2D compression, elastic compression, and embedded memory bus support. Modus incorporates automatic test pattern generation, built-in self-test, and design-for-test technologies.

“We’re pretty excited about it,” Paul Cunningham, vice president of research and development at Cadence, says of Modus. The automatic test equipment market is worth about $4 billion a year, yet test technology hasn’t yielded any significant breakthroughs in the 21st century, he asserts.

“Test has been stagnant for the last 15 to 20 years,” he says.

Cadence is trying to work around the challenges of test time and test costs by addressing “actual physical test” and “test logic itself,” Cunningham notes. Just as chip designers are constantly aware of power/performance/area in their projects, Cadence addressed test coverage and chip size in developing Modus, he adds.

ATPG, BIST, and DFT technologies have been around for a long time, and they are regaining substantial interest in the semiconductor industry as system-on-a-chip device designs grow more complex.

“Chip CAGRs are not what they used to be,” Cunningham observes. “Cost and profit are very, very critical. Power/performance/area are really, really critical.”

Chipmakers are constantly looking to “squeeze profit margins out,” and reducing test costs can contribute to that imperative, the Cadence executive says. “There is “real pressure on margins, real pressure on complexity,” he adds.

Cunningham also focuses on the “concept of a single user interface” for Modus and its related design tools. With a common UI, different steps in the chip design, manufacturing, and testing processes can be like “different apps on an iPhone,” he says.

Cadence collected testimonials for Modus from three chip companies.

“Minimizing the cost of test is crucial in high-volume, price-sensitive markets like embedded processing. The Modus Test Solution is showing a 1.7x reduction in digital test time on one of our largest and most complex embedded processor chips without any impact on design closure,” said Roger Peters of Texas Instruments, who is involved in microcontroller silicon development.

Sue Bentlage, director of ASIC design and methodology at GlobalFoundries, said, “The Modus Test Solution demonstrated a 3.6x reduction in test time on a customer networking chip without impacting design routability or fault coverage. This technology definitely reduces production test costs. The evolution of the Modus Test Solution, as well as the Innovus Implementation System, the Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution, provides a leading edge end-to-end design flow in 14nm and beyond for our worldwide design centers and for our ASIC customers.”

Chris Malkin, baseband IC manager at Sequans Communications, said of Modus, “Test time has a significant impact on semiconductor product costs and production capacity, so reducing test time is important. We have seen the Modus Test Solution achieve a 2x reduction in test time without impacting fault coverage or die size.”

“With the Modus Test Solution, we achieved an impressive 2.6X reduction in compression wirelength and a 2X reduction in scan time. The reduction in compression logic wirelength enabled us to address a key challenge for design closure as we push to smaller process nodes and scale design size,” said Alan Nakamoto, vice president, engineering services at Microsemi Corp.

IoT Will Enable ‘Living Services,’ Keynote Speaker Says

Monday, December 7th, 2015

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By Jeff Dorsch, Contributing Editor

“It’s not about the sensors,” Nandini (Nan) Nayak, managing director of design strategy at Fjord, said Thursday morning (December 3) in a keynote address at the Designers of Things conference in San Jose, Calif.

Rather than talk about the Internet of Things, the subject of this two-day conference, Nayak addressed what she termed “Living Services” – the product of all those IoT sensors and processors, data centers, and cloud-based services.

Living services are “responsive to individual needs, contextually aware, and react in real-time,” she said. They “learn and evolve…as if they are alive.”

The “digitization of everything” creates “liquid expectations” among consumers and other users, Nayak asserted. “People’s expectations transcend expected boundaries,” she added.

The IoT involves “a shift of focus from designing for users and things to designing for people’s activities,” Nayak elaborated. “Everything is beginning to connect with each other.”

She added, “Sensors are cheap; they are able to be placed in many places.”

User interfaces are changing, Nayak noted, moving from computer screen-based interfaces to haptics and “touch-based interaction.”

She laid out the key characteristics of living services – the automation of low-maintenance decisions and actions, long-term learning from what people do, powered by data and analytics, collected from sensor-rich objects and interactions of daily life. “Think about environments, not industries,” Nayak advised.

“The IoT or living services will affect all aspects of our lives,” she asserted. “The home will be a key battleground.”

Personal health and shopping will be other areas where living services will have dramatic impacts, Nayak said.

How can businesses address living services? Nayak said the key points are: Know your customer; flex your technology; design in order to know and flex; and design to delight.

“Think about the value of the experience,” she asserted. “People expect the richness of experience, fun.”

Nayak concluded, “Prepare to atomize. Make your brand feel alive.”

Fjord was acquired in 2013 by Accenture, the global management consulting and technical services firm.

Nayak’s keynote was followed with a panel session moderated by Lucio Lanza of Lanza techVentures, a veteran technology investor and one-time executive at Daisy Systems, an early leader in electronic design automation that was acquired by Intergraph in 1990 and later absorbed into Mentor Graphics.

While the Internet connected computers and networks around the world, smartphones and other mobile devices are connecting people, Lanza noted.

Rather than the Internet of things or objects, it’s more correct to speak of “a world of things,” Lanza asserted, adding, “There are a lot of opportunities making this thing happen.”

Jack Hughes, the chairman and founder of TopCoder who also serves as chairman of the Christopher & Dana Reeves Foundation, showed part of a foundation video showing the benefits of epidural stimulation for people with paralysis.

“It’s not a cure,” he said of the technology. “These are early days. But it is extremely promising. Every one of these injuries is individual.” The foundation has supported the work of device designers, turning out the electrodes that can help paralyzed people move their limbs for the first time in years.

While the technology could deliver groundbreaking rehabilitation, “how do we make these things secure?” Hughes asked.

Mark Templeton of Scientific Ventures LLC, the co-founder of Artisan Components (acquired by ARM Holdings in 2004) and now a tech investor, talked about the Learning Thermostat from Nest Labs (now a Google subsidiary) and the business model behind the device, which can deliver data on its use to electrical utility companies to guide how and when they supply power to customers.

He urged IoT startups to “think about the business model more than the device itself.” He added, “The device is just the starting point.”

Ted Vucurevich of Enconcert, who once was the chief technology officer of Cadence Design Systems, said the IoT is bringing about a “transformation” in electronics, semiconductors, computing, and related industries. “It’s not about winning a socket,” he said, but “how you’re going to monetize the things you sell.”

He added, “There is consolidation and exploration. How can we allow these ecosystems to move forward? There’s a complete transformation coming.”

Noting his background in software, Hughes said, “When I hear ‘Internet of Things,’ I think ‘community.’ It’s a community of things. This is sort of a watershed moment.”

The panel, left to right: Ted Vucurevich, Mark Templeton, Jack Hughes, Lucio Lanza.

Solid State Watch: June 19-25, 2015

Friday, June 26th, 2015
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