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Got MEMS? Get In Touch With memsstar For Production Equipment

Friday, July 17th, 2015

By Jeff Dorsch, Contributing Editor

As you might guess from the company’s name, memsstar is involved in microelectromechanical system (MEMS) devices. The company offers manufacturing equipment for “MEMS-specific production,” says CEO Tony McKie.

Based in Livingston, Scotland, memsstar wants to help in making “MEMS on top of silicon,” he adds.

“There are no such things as standard MEMS,” McKie notes. “MEMS are becoming more complicated.”

While most people are familiar with the MEMS devices in smartphones, like accelerometers and pressure sensors, the Internet of Things will call for different kinds of MEMS and other products, according to McKie. “You need hardware to do that,” he says of IoT. “The rest is filled by software.”

McKie estimates the worldwide market for MEMS production equipment is currently worth about $10 million to $15 million a year. “It’s a growing market,” he says. IoT and other new technologies call for “more and more things that are not CMOS-related,” he adds. Producing new types of MEMS will likely see the startup of more 200-millimeter wafer fabrication facilities, according to McKie.

The primary competitor of memsstar is the SPTS Technologies subsidiary of Orbotech, McKie says.

The company is also involved in refurbishing and remanufacturing deposition and etch equipment from such vendors as Applied Materials, Lam Research, and Novellus Systems (now part of Lam), while providing spare parts for those systems.

Founded in 2003 as Point 35 Microstructures, memsstar received an investment from Albion Ventures in 2007, and has since been a self-funded company, McKie says.

Applied Materials’ Olympia ALD Spins Powerful New Capabilities

Monday, July 13th, 2015

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By Ed Korczynski, Sr. Technical Editor

Applied Materials today unveiled the Applied Olympia ALD system, using thermal sequential-ALD technology for the high-volume manufacturing (HVM) of leading-edge 3D memory and logic chips. Strictly speaking this is a mini-batch tool, since four 300mm wafers are loaded onto a turn-table in the chamber that continuously rotates through four gas-isolated modular processing zones. Each zone can be configured to flow any arbitrary ALD precursor or to exposure the surface to Rapid-Thermal-Processing (RTP) illumination, so an extraordinary combination of ALD processes can be run in the tool. “What are the applications that will result from this? We don’t know yet because the world has never before had a tool which could provide these capabilities,” said David Chu, Strategic Marketing, Applied’s Dielectric Systems and Modules group.

Fig.1: The four zones within the Olympia sequential-ALD chamber can be configured to use any combination of precursors or treatments. (Source: Applied Materials)

Figure 1 shows that in addition to a high-throughput simple ALD process such that wafers would rotate through A-B-A-B precursors in sequence, or zones configured in an A-B-C-B sequence to produce a nano-laminate such as Zirconia-Alumina-Zirconia (ZAZ), almost any combination of pre- and post-treatments can be used. The gas-panel and chemical source sub-systems in the tool allow for the use up to 4 precursors. Consequently, Olympia opens the way to depositing the widest spectrum of next-generation atomic-scale conformal films including advanced patterning films, higher- and lower-k dielectrics, low-temperature films, and nano-laminates.

“The Olympia system overcomes fundamental limitations chipmakers are experiencing with conventional ALD technologies, such as reduced chemistry control of single-wafer solutions and long cycle times of furnaces,” Dr. Mukund Srinivasan, vice president and general manager of Applied’s Dielectric Systems and Modules group. “Because of this, we’re seeing strong market response, with Olympia systems installed at multiple customers to support their move to 10nm and beyond.” Future device structures will need more and more conformal ALD, as new materials will have to coat new 3D features.

When engineering even-smaller structures using ALD, thermal budgets inherently decrease to prevent atomic inter-diffusion. Compared to thermal ALD, Plasma-Enhanced ALD (PEALD) functions at reduced temperatures but tend to induce impurities in the film because of excess energy in the chamber. The ability of Olympia to do RTP for each sequentially deposited atomic-layer leads to final film properties that are inherently superior in defectivity levels to PEALD films at the same thermal budget:  alumina, silica, silicon-nitride, titania, and titanium-nitride depositions into high aspect-ratio structures have been shown.

Purging (from the tool) pump-purge

Fab engineers who have to deal with ALD technology—from process to facilities—should be very happy working with Olympia because the precursors flow through the chamber continuously instead of having to use the pump-purge sequences typical of single-wafer and mini-batch ALD tools used for IC fabrication. Pump-purge sequences in ALD tools result in the following wastes:

*   Wasted chemistry since tools generally shunt precursor-A past the chamber directly to the pump-line when precursor-B is flowing and vice-versa,

*   More wasted chemistry because the entire chamber gets coated along with the wafer,

*   Wasted cleaning chemistry during routine chamber and pump preventative-maintenance,

*   Wasted downtime to clean the chamber and pump, and

*   Wasted device yield because precursors flowing in the same space at different times can accidentally overlap and create defects.

“Today there are chemistries that are more or less compatible with tools,” reminded Chu. “When you try to use less-compatible chemistries, the purge times in single-wafer tools really begin to reduce the productivity of the process. There are chemistries out there today that would be desirable to use that are not pursued due to the limitations of pump-purge chambers.”

—E.K.

Solid State Watch: June 19-25, 2015

Friday, June 26th, 2015
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New Applied PVD system targets TiN hardmasks for 10nm, 7nm chips

Tuesday, May 19th, 2015

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By Jeff Dorsch, Contributing Editor

Applied Materials today introduces the Applied Endura Cirrus HTX PVD, a physical vapor deposition system for creating titanium nitride hardmask films that could be used in fabricating 10-nanometer and 7nm chips.

“Titanium nitride is the metal hardmask of choice,” harder than copper and nearly as hard as diamond, says Sree Kesapragada, Applied’s global product manager for Metal Deposition Products.

“Patterning plays key role in defining the interconnect,” Kesapragada says. “Perfect via alignment is critical for device yield. Hardmask ensures the perfect via alignment critical for yield.”

The hardmasks created with the Endura Cirrus HTX TiN system strike the required balance between neutral stress and film density hardness, he asserts. The TiN hardmask, meant to resist the erosion of etching, helps ensure that via etches land where they are supposed to, and not too close to neighboring vias, which can creates shorts.

Metal hardmask layer manages alignment errors.

Applied has worked with customers at multiple sites in developing the new PVD system over the past two to three years, according to Kesapragada. He emphasizes that the Cirrus HTX TiN system offers “precision control over TiN crystal growth,” as the process chamber is “designed for tensile high-density TiN films.” The new PVD system enables high density, tensile films thanks to a high level of ionization during deposition made possible by a high frequency source.

High film desnity is needed to prevent erosion, and a neutral-to-tensile stress is needed for pattern fidelity. CVD/ALD films have tensile stress, but are low density. Traditionally deposited TiN films have good density, but compressive stress.

The formation of “islands” of TiN crystals is almost like chemical vapor deposition, “layer by layer,” Kesapragada says, “in a PVD chamber.”

In the process chamber, the first of its kind, titanium atoms are reactively sputtered in a nitrogen-based plasma, allowing for tunable composition, according to Applied. This chamber can be used for high-volume manufacturing of semiconductors with 7nm features, covering two process-node generations, Kesapragada says.

There is also “very established integration” with chemical mechanical planarization equipment, he adds.

Applied is the market leader in TiN PVD systems, with more than 200 systems shipped, according to Kesapragada. Those PVD systems have more than 700 process chambers, he adds.

The Endura Cirrus HTX TiN PVD system is being formally introduced this week at the IEEE’s 2015 International Interconnect Technology Conference in Grenoble, France.

Solid State Watch: April 24-30, 2015

Monday, May 4th, 2015
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Solid State Watch: April 17-23, 2015

Friday, April 24th, 2015
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Solid State Watch: February 20-26, 2015

Monday, March 2nd, 2015
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Solid State Watch: February 6-12, 2015

Friday, February 13th, 2015
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5nm Node Needs EUV for Economics

Thursday, January 29th, 2015

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By Ed Korczynski, Sr. Technical Editor

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At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.

Fig. 1: Panelists discuss future IC manufacturing and design possibilities in San Francisco on December 16, 2014. (Source: Pete Singer)

Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:

  • Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
  • Michael Guillorn, Ph.D. – research staff member, IBM,
  • Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
  • Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
  • Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.

Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.

Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.

Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm:  gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.

Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.

Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:

  1. everything is an interface requiring precision materials engineering,
  2. film depositions are either atomic-layer or selective films or even lattice-matched,
  3. pattern definition using dry selective-removal and directed self-assembly, and
  4. architecture in 3D means high aspect-ratio processing and non-equilibrium processing.

An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.

Fig. 2: ElectroMigration (EM) lifetimes for on-chip interconnects made with either conventional Cu or Cu lined and capped with Co, showing 10 times improvement with the latter. (Source: Applied Materials)

“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.

There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.

However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”

Applied Materials Introduces New Hardmask Process, Saphira

Monday, November 24th, 2014

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A new hardmask material and process was introduced this month by Applied Materials. Designed for advanced logic and memories, including DRAM and vertical NAND, the hardmask is transparent, which simplifies processing. It also exhibits very high selectivity, low stress and good mechanical strength. It’s also ashable, so that it can be removed after etching is completed. Called Saphira, the process was developed in conjunction with Samsung and other customers. An Applied Materials-developed process for stripping the hardmask was licensed to Korea-based PSK.

Hardmasks are used for etching deep, high aspect ratio (HAR) features that conventional photoresists cannot withstand. Applied Materials first introduced an amorphous carbon hardmask in 2006, and now has a family of specialized films. The Advanced Patterning Films (APF) family now includes APFe, which enables deposition of thicker layers than APF (e.g., in capacitor formation and metal contacts for memory devices), and APFx, design to address patterning of metal lines and contacts at 5xnm and beyond.

The new Saphira APF process – which runs on the Applied Materials Producer XP Precision CVD chamber and works with PSK’s OMNIS Asher systems — introduces new film properties that include greater selectivity and transparency. The Saphira APF deposition and resolve major issues to improve patterning of more complex device structures at advanced technology nodes. “It’s a materials solutions,” said Terry Lee, vice president of strategy and marketing for the dielectrics systems and modules group at Applied Materials. “It’s delivered with the patterning film itself, Saphira, as well as the combination of technologies and processes, whether it’s in the CVD chamber or etch chamber, reducing process steps and simplifying process complexity.

Applied Materials isn’t saying exactly what the Saphira hardmask is composed of, but a recent patent filing describes it as boron-rich amorphous carbon layer. The patent notes that, compared to carbonaceous masking layers, boron-doped carbonaceous layers, which include between 1 wt. % and 40 wt. % boron provide even greater etch resistance.

Lee said the Saphira film “In general behaves very much like a ceramic. But unlike most ceramics, it’s ashable. It’s structurally hard like a ceramic, but it’s ashable like our standard carbon hard mask,” he said.

In general, the selectivity of Saphira is twice the conventional masking materials on the open market, Lee said.

The new process reduces process complexity and cost in a couple of different ways. Because it’s transparent, no extra step is needed to open the mask to find the alignment mark. And because the film has high selectivity, fewer masking steps are required. That all reduces the process complexity. Lee said that with conventional masks, in order to mask these high aspect ratio features, a thicker mask material is often needed. “When you have a thicker mask and you need to etch fine features, what you wind up with is a very narrow mask. In order to prevent the mask itself from collapsing or titling, you need very strong mechanical strength. With Saphira, we have that high mechanical strength and it resists the deformation,” he said.

Saphira can also reduce the need for multiple hardmasks. “Instead of having the hardmask, oxide and poly (see figure), it drops down to a one mask that’s thinner because the selectivity is higher,” Lee explained. “What we’re seeing is that we can reduce around 20 steps. When you reduce steps, you reduce cost. What we’re seeing based on our calculations is something like 35% reduction in cost of this one module. Across multiple modules, that adds up to a lot of money,” he added.

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