By Mark LaPedus

Taking another shot to displace ARM, Intel recently rolled out its new microarchitecture for its Atom processor line. In a research note, Will Strauss, president of Forward Concepts, said: “How many times have we heard Intel say that its next member of the Atom processor line would finally be competitive with low-power ARM implementations? Every other year, Intel carts out a new variant that will ‘finally’ do the trick.  The next (and fourth?) iteration of the family, code named Merrifield is said to be the ‘turning point’ for the company in mobile phones.  Although the 2012 launch of Medfield-based 3G phones came close, it didn’t put a dent in ARM’s market share. Merrifield will ship in 4Q13 and phones based on the SoC will be announced at MWC in February 2014. But, the application processor is only part of the solution for a successful smartphone chip offering.  Multimode LTE modems and LTE RF transceivers are also necessary.  Yes, the Infineon-heritage RF transceivers have been fielded in Motorola LTE smartphones, but we’re still waiting for Intel’s multimode LTE modem.  It’s our understanding that the Infineon-heritage multimode 2G/3G/HSPA+ (based on CEVA’s DSP cores) will be married to the Blue Wonder-heritage single-mode LTE (based on Tensilica’s DSP cores). Since the software between the two is not compatible, we expect that has led to integration problems and subsequent delays.”

Following a disappointing period in the first quarter of this year, IHS plans to lower its chip forecast to 4.8% for 2013, down from 5.6% in the previous forecast. In 2012, the IC market fell 2.2%, according to the research firm. Mike Splinter, chairman and CEO of Applied Materials, presents his forecast.

In its most recent quarter, Applied Materials generated orders of $2.27 billion, up 7%t from the prior period, with Silicon Systems Group orders up 14% from the first quarter and Display orders up 41% sequentially. Net sales were $1.97 billion, up 25% sequentially.

At SEMI’s recent Silicon Valley Lunch Forum, speakers from Applied Materials, ASML, and Intel discussed the critical challenges of 450mm and EUV.

The infrastructure in Saratoga, N.Y. can’t keep pace with the growth. One local government organization, the Saratoga County Industrial Development Agency, voted to consider issuing GlobalFoundries nearly $70 million in bonds to finance the infrastructure, according to The Saratogian.

Three companies announced RF switches based on SOI or a variant of the technology. Skyworks rolled out some new parts. Peregrine announced a product for harsh environments. And RDA’s RF switches are being used in Samsung’s smartphones.

Mentor Graphics announced that MagnaChip Semiconductor has adopted the Pyxis custom IC design platform and the Mentor process design kit (PDK) automation process.  Mentor Graphics also announced that CNH, a supplier of agricultural and construction equipment, has transitioned to the latest VeSys software platform.

Cadence Design Systems announced that it helped Yamaha reduce power consumption for its mobile consumer chips with characterization tools.

Is TranSwitch on the block? The communications chip maker has retained Needham & Co. as financial advisor to assist the board in evaluating various strategic alternatives available to the company.

Altera has signed a definitive merger agreement to acquire Enpirion, a provider of high-efficiency, integrated power conversion products known as power SoCs (power system-on-chips).

The use of Wi-Fi functionality in small-cell base stations will be a game changer for cellphone service providers, according to IHS.

Android and iOS, the number one and number two ranked smartphone operating systems (OS) worldwide, combined for 92.3% of all smartphone shipments during the first quarter of 2013 (1Q13) as Windows Phone crept past BlackBerry for 3rd place, according to IDC.

By Mark LaPedus

There are mixed signals in the semiconductor industry right now and it’s difficult to get a pulse on the market.

Chip demand is hot and then cold. Inventories seem to rise and fall. “We’re seeing positive signs and we’re seeing negative signs,” said Len Jelinek, an analyst for IHS. “In the U.S., one week is good. One week is bad.”

Following a disappointing period in the first quarter of this year, IHS plans to lower its chip forecast to 4.8% for 2013, down from 5.6% in the previous forecast, Jelinek said.  In 2012, the IC market fell 2.2%, according to the research firm.

“It’s a different story in the foundry market,” he said. The overall foundry market is expected to grow 20% in 2013, compared to 16.9% in 2012, according to the firm.

Another firm, VLSI Research, has recently lowered its chip forecast from 10.2% to 9.9% in 2013 over 2012. VLSI also lowered its semiconductor equipment forecast from -4.6% to -5.4% in 2013.

Earlier this year, Mike Splinter, chairman and CEO of Applied Materials, said the 2013 wafer fab equipment market would be flat to down 10% relative to 2012, reaching around $30 billion in terms of spending.

This week, Splinter maintained his forecast. “While there have been some shifts in customers’ investment plans towards mobility, we maintain our view that 2013 wafer fab equipment will be in the range of $27 billion to $30 billion,” he said on the Seeking Alpha Web site. Splinter’s comments were transcribed as Applied this week reported its results for the quarter.

Meanwhile, IHS originally thought that the first quarter would hit a seasonal lull and fall 2.4% in the period, compared to the fourth quarter of 2012. Instead, the first quarter of 2013 fell 4.4%. “It was a weaker quarter than anticipated,” Jelinek said during a keynote at the 2013 MagnaChip Semiconductor Foundry Technology Symposium in Santa Clara, Calif.

IHS also sees the chip market growing 2.3% in the second quarter and 8.3% in the third quarter, with flat growth in the fourth quarter. “2013 is driven by wireless products,” he said. “Consumer spending is second half loaded. PC and tablet sales, along with holiday spending, will drive industry revenue growth in Q3 and Q4.”

However, there are some concerns, especially with the overall economy. Europe and Japan remain in a slump. “Sequestering in the U.S. will slow economic growth in the second quarter before a modest improvement in the second half of this year,” he said. “Chinese economic growth in Q1 decelerated, but economic injections will drive overall growth to greater than 8%.”

On the semiconductor side of the equation, fab utilization will remain below optimal levels well into the second quarter. “Modest revenue growth projections with cautious increases in manufacturing should keep supply and demand in balance throughout 2013,” he said.

By Mark LaPedus
It’s the tale of two promising and separate 3D chip architectures. One technology is slowly taking root, while the other one is heating up.

3D stacked-die using through-silicon vias (TSVs) is on the slower path. Advanced chip-stacking has several challenges and is still a few years away from mass production. In contrast, 3D NAND is heating up, as Samsung and SK Hynix are accelerating their efforts in the arena.

Presently, NAND vendors are on the 2xnm or 1xnm nodes. The prevailing thought was that vendors would scale existing planar NAND at three distinct points down the 1xnm node. Typically, NAND vendors denote those points as 1x, 1y and 1z. Then, after the so-called 1z or 1znm node, planar NAND supposedly would hit the scaling wall, forcing vendors to migrate to 3D NAND.

In fact, 2D NAND will have difficulties scaling beyond 10nm. This is because the critical structure in NAND—the floating gate—is seeing an increase in the dreaded cell-to-cell interference in the word lines.

SanDisk still plans to scale NAND for two more generations until 2016, and then, it will debut 3D NAND. But in what appears to be a switch in strategy, Samsung and SK Hynix plan to develop 2D NAND at the 1x and 1y nodes. Then, “it appears that Samsung is bypassing 1z, similar to SK Hynix,” said Doug Freedman, an analyst with RBC Capital Markets.

Instead of going to 1z, Samsung and Hynix will move directly to 3D NAND. In fact, Samsung will begin sampling parts in the second half of 2013, with production slated for 2014, Freedman said.

“As there is maybe one more shrink left for planar NAND, some manufacturers are making the transition earlier to 3D NAND,” said Greg Wong, an analyst with Forward Insights. “Scaling of planar NAND is nearing its end, and 3D NAND is seen as the way to continue density increases and cost reductions for NAND flash memory.”

With 3D NAND, memory vendors also will move from a costly lithography-centric production environment to a less-expensive etch/deposition flow, said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “The overall cost of the tools will be cheaper with 3D NAND,” Lee said “This is mainly driven by the difference in the number of critical lithography and double-patterning steps.”

3D NAND contenders
Samsung will bring out 3D NAND first, followed in order by SK Hynix, Toshiba and Micron, Forward Insights’ Wong said. In 3D NAND, Samsung hopes to leapfrog the competition and grab the early profits with its so-called terabit cell array transistor (TCAT) architecture.

In TCAT, NAND layers are stacked using an oxide and nitride deposition process. Then, the nitride is removed by an etch process. Finally, the bit and word lines are created using a tungsten fill. TCAT and other 3D NAND architectures are different than 2.5D/3D stack-die technologies, where devices are stacked and connected using TSVs.

Another NAND vendor, SanDisk, has a different strategy. “SanDisk is planning to remain planar until 2016, while competitors begin to develop and produce 3D (NAND) into the market late this year and early next,” said RBC’s Freedman. “SanDisk’s (3D NAND) solutions are being judiciously developed to cater to the high-performance market. The high-performance side of the market will not be ready to qualify 3D for another two to three years.”

Using 193nm immersion lithography, the SanDisk-Toshiba duo is producing 19nm planar NAND with a 19- x 26-nm cell size. Then, at 1y, SanDisk’s goal is to devise planar NAND with a 19- x 19.5nm cell size, with production slated by the end of this year.

Then, unlike Samsung and SK Hynix, SanDisk will scale planar at 1z. “There is no need to rush into 3D” until it is cost effective, said Ritu Shrivastava, vice president of technology at SanDisk. In reality, 2D NAND will remain the mainstream technology for some time. Over time, 3D NAND will move into high-end applications, like solid-state storage.

By 2016, SanDisk hopes to debut the Bit Cost Scalable (BiCS) technology, a 3D NAND technology that was originally conceived by Toshiba. BiCS makes use of a “punch-and plug” structure. Toshiba has fabricated a prototype 32-Gbit BiCS test array, with a 16-layer memory cell based on 60nm design rules.

The advantage of 3D NAND is that it doesn’t require leading-edge lithography. Going to 3D NAND will present some challenges, namely the development of quality parts with good read/write performance with endurance. “3D NAND will require a different equipment set,” Shrivastava said. “The burden will shift from lithography to deposition and etch.”

3D NAND process challenges
It also will present NAND vendors with some difficult decisions. First, despite their public roadmaps, vendors may be forced to migrate to 3D NAND sooner than later. “Most leading-edge producers are doing 2D NAND manufacturing at the 20nm or 19nm node, which is the last generation of self-aligned double patterning technology,” Applied’s Lee said. “By using self-align double patterning, one can pattern about 19nm or 19.5nm half-pitch.”

But for some time, the problem with 2D NAND has been apparent—it is running out of steam. “With existing planar NAND, there is not much room to squeeze in the materials for the charge-trap flash or the floating-gate,” Lee said.

In theory, NAND hits the wall at 10nm. “In order to scale NAND manufacturing beyond that, the industry must adopt self-aligned quadruple patterning or self-aligned triple pattering,” he said. “That allows for 10nm half-pitch. But doing 10nm half-pitch patterning will be extremely difficult. It will add a lot more process steps, which will increase the cost of manufacturing.”

Clearly, 3D NAND is the future based on two factors: scaling and cost. “If you compare the cost between sub-20nm planar versus 3D NAND, I believe it will be a lot cheaper to build a 3D NAND fab,” he said. “Planar is driven by litho. In 3D NAND, the bit growth is enabled by increasing the number of vertical layers. This has nothing to do with litho.”

3D NAND can be produced using existing 193nm lithography. Other expensive steps, such as self-align double-patterning etch and low-temperature atomic layer-deposition (ALD), are also eliminated. All told, 3D NAND is largely dependent on two technologies: deposition and etch.

The big challenge is to enable high-aspect ratios using new etch techniques. “There are three distinctly new etch processes in 3D NAND,” Lee said. “This includes high-aspect ratio memory hole etch, which did not exist in planar NAND. There is also a high-aspect ratio trench-line etch, which also did not exist in planar. And then another one is a so-called staircase etch. This is a very long process, which has to provide the landing pads for the contacts.”

3D NAND also introduces alternating stack deposition, which defines the vertical stack. In a 32-layer NAND device, for example, the process could involve some 64 layers of deposition, plus some dummy layers. All told, the flow requires some 70 alternating deposition steps. “The existing tools cannot provide such high productivity,” Lee said. “So that involves a new type of chamber design and technology.”

Metrology is also a critical part of the equation. “Nanometrics believes that 3D NAND will use 20% to 25% more OCD tools relative to planar NAND,” said Weston Twigg, an analyst with Pacific Crest Securities.

“In planar NAND, the gate width is defined by lithography,” added Applied’s Lee. “Now, the gate width is defined by deposition. So, the uniformity of PECVD deposition of each layer, and the quality of the films, are very critical. When we deposit several layers, it’s not a big deal. But let’s say we deposit 40, 50 or 70 layers in-situ. That means we have to control the surface of the interface very smoothly from the beginning. Otherwise, we end up with a rough surface on the top, which will not work.”

So far, Micron, Samsung, SanDisk-Toshiba and SK Hynix have yet to discuss the exact specifications for their respective 3D NAND devices. It’s unclear how many layers the initial devices will have, prompting many to ask a simple question: How far will 3D NAND scale? “I see it going for several generations,” Lee said. “But after 3D NAND, the industry will require another breakthrough.”

By Mark LaPedus
Japan’s Ushio will discontinue its R&D for EUV light sources and will sell its EUV service business to ASML. That means the market has only two EUV source vendors—ASML’s Cymer unit and Gigaphoton. “Ushio’s subsidiary, Xtreme Technologies, competes with Cymer, which was recently acquired by ASML, thus symbolizing an endorsement of Cymer’s EUV technology. Ushio will gain cost savings in both fixed costs and variable costs as 30 staff in their German facility will be shifted under ASML’s umbrella. Although the termination of this business is disappointing, it does reduce future risk of high R&D costs as well as lowering current costs,” said analyst David Motozo Rubenstein in his blog called Chips and Dips.

Taking another shot to displace ARM in the mobile, tablet and other markets, Intel rolled out its new and long-awaited microarchitecture for its Atom processor line.

SEMI applauded the White House announcement that President Obama decided to visit Applied Materials’ facilities in Austin, Texas. This was part of his focus on manufacturing jobs, high-tech skills and technology that will drive long-term economic growth. The administration’s announcement cited Applied Materials’ contribution to innovation and job creation.

While faced with difficult technology and investment choices in R&D, there is now increased pressure on the component-level supply chain, according to Michael Lercel, director of nanodefectivity and metrology at Sematech, in SEMI’s newsletter.

Worldwide silicon wafer area shipments decreased during the first quarter 2013, when compared to fourth quarter 2012 area shipments according to the SEMI.

KC Ang, senior vice president and general manager of GlobalFoundries Singapore, has been appointed to serve SEMI Singapore Regional Advisory Board (RAB) as their new chairman.

Cadence announced its intent to acquire the IP business of Evatronix, adding to its rapidly expanding IP offering.

Cadence also introduced a new version of Incisive Enterprise Simulator, which improves low-power verification productivity of complex SoCs by 30%.

Mentor Graphics announced availability of the newest tool in the Capital software suite, Capital Harness TVM. This tool automatically generates detailed harness manufacturing process and cost data that is specific to each harness design, each factory and each company’s cost models.

SRC and NIST announced the second phase of the Nanoelectronics Research Initiative (NRI). For this phase, SRC and NIST will provide a combined $5 million in annual funding for three multi-university research centers tasked with demonstrating non-conventional, low-energy technologies that outperform current technologies on critical applications in 10 years and beyond.

On the outside, the U.S. and South Korean versions of Samsung Electronics’ Galaxy S4 smartphone look alike. But on the inside, there are differences in key components, according to IHS. Global shipments of solid state drives (SSD) in PCs are set to rise by a factor of seven by 2017, allowing them to claim more than one-third of the market for PC storage solutions by that time, according to an IHS.

The high-flying acceleration and sensor product category was brought back to earth in 2012 when price erosion pulled down annual sales growth to 7%—the lowest percentage increase for motion-sensing semiconductors since 2005, according to IC Insights.

After falling 15% in 2012, solar photovoltaic wafer production is forecast to grow 19% in 2013, passing 30 GW and recovering to the 2011 level, according to NPD Solarbuzz. However, industry utilization is expected to remain below 60%.

Natural gas vehicles (NGVs) on the road in the world’s seven largest automobile markets will reach only 7.5 million as the industry struggles to capitalize on cheap shale-driven natural gas, Lux Research said.

By Mark LaPedus
Enterprise-based bring your own device (BYOD) programs continue to become more commonplace. In fact, 38% of companies expect to stop providing devices to workers by 2016, according to a global survey of CIOs by Gartner.

What would happen if half of all global DRAM production, two-thirds of NAND flash manufacturing and 70% of the world’s tablet display supply suddenly disappeared from the market? For high-tech companies, this could be the outcome if current tensions escalate to the point of war on the Korean peninsula, resulting in the disruption of South Korea’s technology manufacturing base, says IHS iSuppli.

Intel telegraphed its future directions. The chip giant has named Brian Krzanich as its next chief executive, succeeding Paul Otellini. Krzanich, Intel’s chief operating officer since January 2012, will become the sixth CEO in Intel’s history. As announced, Otellini will step down as CEO. In a research note, Hans Mosesmann, an analyst with Raymond James, said: “We are not entirely shocked by the news but note that some investors preferred an external option on the belief that new blood was needed. Giving Krzanich’s manufacturing background we think the appointment is an indication that Intel will continue Paul Otellini’s strategy of building bigger/better fabs to attack the market. We also believe the move toward better manufacturing processes (like the 450mm transition) will remain front and center.” Added RBC Capital analyst Doug Freedman: “The move to appoint Renee James (as president) is likely in support of the vision of Krzanich’s and the board has laid out for the future of Intel. This appointment validates the increasing importance of on-going software development to Intel’s future, whether it be internally or in collaboration with partners.”

Microsemi has inked a foundry deal with Intel. Microsemi is currently engaged with customers and has started designs utilizing Intel’s 22nm tri-gate technology. Product delivery is anticipated to begin in late 2014 to early 2015.

Infineon and GlobalFoundries announced a joint technology development and production agreement for 40nm embedded flash (eFlash) process technology. The cooperation will focus on technology development based on Infineon’s eFlash cell design and manufacturing of automotive and security microcontrollers with 40nm process structures.

GlobalFoundries has collaborated with Cadence to provide pattern classification data for manufacturing processes of 20nm and 14nm. GlobalFoundries is using the Cadence Pattern Classification and Pattern Matching Solutions.

SEMI announced that Philip Yeo, chairman of Spring Singapore, and Lee Kok Choy, country manager of Micron Technology Singapore, have been voted by the SEMI Singapore Regional Advisory Board as recipients of two prestigious awards recognizing their contributions to the development and success of the Southeast Asian semiconductor industry. The awards will be presented during festivities held at Semicon Singapore 2013 on May 7.

Soitec has finalized a ZAR 1,000,000,000 (more than $100 million) solar financing bond issued by CPV Power Plant No.1 Bond SPV, an affiliate of Soitec Solar GmbH. The bonds will finance the construction of a 44 MWp utility-scale concentrator photovoltaic (CPV) solar power plant in Touwsrivier, South Africa.

Applied Materials and The Center for Science Teaching and Learning (CSTL) announced the San Francisco Bay Area grand-prize winning team and nine finalist teams in the 2013 Clean Tech Competition.

Rudolph has purchased selected assets related to 3D metrology from Tamar Technology.

Proteus Digital Health has completed a second closing of its Series F financing, raising $62.5 million in total. New corporate investor Oracle joins Otsuka, Novartis, Sino Portfolio and others in this funding round. Proteus is working to create a new category of products. Called Digital Medicines, these new pharmaceuticals will contain a tiny sensor that can communicate, via a digital health feedback system, vital information about an individual’s medication-taking behavior and how their body is responding.

Is Mindspeed Technologies on the block? The supplier of semiconductor solutions for communications has retained Morgan Stanley as a financial advisor to assist the board in evaluating various strategic alternatives available to the company.

Spansion has acquired the microcontroller and analog business of Fujitsu Semiconductor for approximately $110 million, plus approximately $65 million for inventory.

Amkor Technology announced that Stephen Kelley has been appointed to serve as president and CEO. He succeeds Ken Joyce, who previously announced his intention to retire.

ASE remained the world’s largest OSAT in 2012, according to the new rankings from Gartner.

By Mark LaPedus
Qualcomm has the highest market share for baseband solutions in handsets, resulting in a position far out in front of its competitors. ST-Ericsson has strong products on the market with competitive features. But one analyst at ABI Research questions why ST-Ericsson was broken up just as it finally came out with a highly competitive product, which was based on FD-SOI.

The worldwide semiconductor foundry market totaled $34.6 billion in 2012, a 16.2% increase from 2011, according to final results by Gartner. TSMC maintained the No. 1 spot in the rankings in 2012. Strong performance on 32nm yields and the availability of sub-45nm wafer capacity at the Dresden, Germany, fabs allowed GlobalFoundries to advance to the No. 2 position in 2012. UMC‘s market share decreased due to reduced wafer shipments. Driven by the wafers consumed by Apple, Samsung moved up four spots to the No. 5 position with 175.5% growth in 2012.

At this year’s Symposium on VLSI Technology, Intel will report technical details of its embedded DRAM with 22nm technology on bulk silicon wafers. Intel realized a 0.029mm2 DRAM cell capable of meeting >100us retention at 95 C. In the DC-DC converter session, Intel will present a switched capacitor step-down converter designed in a 22nm tri-gate CMOS technology. The VLSI Symposium is slated for June 11–14 in Kyoto, Japan.

At the VLSI event, STMicroelectronics and CEA-LETI will report six transistor SRAM (6T-SRAM) cells for high-density and low-voltage. The technology is fabricated at the 28nm node using FD-SOI technology for the first time.

At the VLSI Symposium, IBM and GlobalFoundries will report a SiGe channel tri-gate pFET with aggressively scaled fin width and gate length dimensions. It is fabricated using SiGe on an insulator substrate. Excellent electrostatic control down to Lg= 18nm and Wfin<18nm has been reported.

At the event, IMEC and GlobalFoundries will present the first demonstration of strained germanium channel pFETs fabricated on SiGe strain relaxed buffers, which is surrounded by STI region. Also, they introduced raised SiGe source/drain structures (Ge concentration= 75%) with an implant-free quantum well, replacement metal-gate process and germanide in contacts to solve void issues.

In addition, STMicrolectronics, Samsung, GlobalFoundries and IBM will report a 64nm pitch BEOL integration and material strategy. A self-aligned-via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask.

SEMI reported that for the quarter ending Dec. 31, 2012, the worldwide photovoltaic manufacturing equipment book-to-bill ratio remained well below parity, at 0.45, for the seventh consecutive quarter. Booking levels continue to be low as PV manufacturers grapple with oversupply across the supply chain.

Khaled Juffali Company (KJC), a Saudi Arabian investment company, and Soitec, signed a memorandum of understanding (MOU) to cooperate in driving solar industry growth in Saudi Arabia and the Middle East. Under the MOU, the two companies will create a joint venture to market and sell concentrator photovoltaic (CPV) systems in the Kingdom of Saudi Arabia.

Hwa Chong Institution emerged as the winner of the Applied Materials Clean Tech Competition in Singapore. The project focused on utilizing calcium carbonate found in clam shells to remove toxic metal ions from waste water.

The separate hardware and software teams in companies are notorious for not being on the same page, thereby putting product development times and cost at risk. Mentor Graphics CEO Walden Rhines outlined some new and practical solutions to the problem.

Mentor Graphics announced the release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon. The tool provides a tighter connection between hardware and software co-development, but allows software developers to use existing programming tools with extensions.

Cadence announced results for the first quarter of fiscal year 2013. Cadence also completed its previously announced acquisition of Tensilica.

Advantest will acquire W2BI, a provider of system level test automation software focusing on wireless communications.

Shipments of smart glasses may rise to as high 6.6 million units in 2016, up from just 50,000 in 2012, for a total of 9.4 million units for the five-year period, according to an upside forecast from IMS Research.

The worldwide mobile phone market grew 4% year over year in the seasonally slow first quarter of 2013 as smart phones out-shipped feature phones for the first time, according to IDC. Nokia, BlackBerry and HTC have dropped out of the top rankings.

By Mark LaPedus
The term carbon footprint seems to be “old hat” and yesterday’s measure of sustainability. “Sustainable development” is the new term. But what is it and can someone please define it? The recent European Coatings Show provided a clue, according to Lux.

For years, smart watches have failed to take off for one reason or another: they looked ugly, had weak functionality, or the battery life was lousy, according to ABI Research. However, a new collection of smart watches have emerged that could change consumers’ perceptions. Market intelligence firm ABI Research projects more than 1.2 million smart watches will be shipped in 2013.

Intel announced its results and cut its CapEx by $1 billion from $13 billion to $12 billion. Hans Mosesmann, an analyst with Raymond James, made the following observations: “With smartphones/tablets not contributing much for Intel in 2013 and the foundry growth vector still 2-3 years from being a real business, Intel is, in our view, quite vulnerable. The hope is for a datacenter recovery as an offset in 2H13 – we’ll see. Interestingly, Intel indicated in relation to its foundry strategy that it would not enable competitors that license ARM processor technology. Outside of programmable logic devices (PLDs), isn’t everybody of significance already using ARM?”

For total fab spending, GlobalFoundries plans to spend $4.4 billion this year to expand production as demand for smartphones and tablets jumps, according to Bloomberg. The spending compares with $3.8 billion last year.

TSMC raised its capital spending. Spending will be $9.5 billion to $10 billion, compared to an earlier forecast of $9 billion, according to Bloomberg. TSMC is accelerating its 20nm and finFET production.

In a blog, Applied Materials said it has recently completed the electrical characterization of through-silicon via (TSV) structures. This development is important because TSVs are the vertical interconnections that carry power and high-bandwidth speed signals between the stacked die of layered logic and memory devices.

Recently, more than 270 students from National Tsing Hua University in Hsinchu, Taiwan, crowded into the campus auditorium to hear Mike Splinter, chairman and CEO, of Applied Materials, to deliver a talk. The Applied Materials CEO told students to follow their passion.

Soitec’s solar unit has completed a debt financing plan for its Touwsrivier project in South Africa.

Soitec announced consolidated sales of 72.7 million euros for the fourth quarter, down 9.3% on a yearly basis. On a sequential basis, Q4 electronic sales were up by 19.1%.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 1.14 in March, up from 1.10 from April, according to SEMI. id=highlights

Mentor Graphics announced the opening of a new Mentor-sponsored electronics design laboratory at The University of Nottingham Ningbo China (UNNC), based in the Zhejiang province. Mentor has donated more than $10 million in EDA software and support to enable UNNC students to graduate with in-depth knowledge of leading-edge design methodologies.

ASML announced its results and said the contract of Eric Meurice, president and CEO, ends next year. As of July 1, ASML’s leadership will be comprised as follows: Peter Wennink, ASML’s CFO, will be president and CEO; Martin van den Brink, ASML’s executive vice president, will be president and chief technology officer. Meurice will be chairman of ASML and act as adviser to the new leadership and the supervisory board until the end of his contract on March 31, 2014.

Intermolecular has entered into a multi-year technology development and IP licensing agreement with Micron Technology, focused on technology development and related IP for advanced memory technologies. Intermolecular has been working on DRAM technology with Elpida, which is being acquired by Micron. Now, with Micron, Intermolecular is expanding into the nonvolatile memory front with the memory maker, said Dave Lazovsky, president and CEO of Intermolecular. “New materials and device architectures are increasingly needed to meet future embedded and mobile technology requirements, and partnering with Micron in this area is a significant milestone for Intermolecular,” he said.

Tessera has named Richard Hill as interim chief executive and executive chairman of the board. Hill replaces former president and CEO Robert Young, who has decided to step down amid pressure from an investment firm.

Altera has agreed to acquire TPACK, a subsidiary of Applied Micro Circuits Corp. TPACK delivers FPGA-based optical transport network products targeting packet and optical networking equipment suppliers.

”According to Dow Jones VentureWire and other news reports, Avago has reached a deal to acquire Javelin Semiconductor, a manufacturer of CMOS power amplifiers (PAs) which services the mobile market,” said Doug Freedman, an analyst with RBC Capital Markets.

Netronome has raised $19 million in series E and related financing from Sourcefire, Intel Capital and existing investors DFJ Esprit and the Raptor Group. The company is making a next-generation flow processor line, the NFP-6xxx, which is built using Intel’s 22nm tri-gate technology.

Smartphones are forecast to account for 26% of the $30.0 billion NAND flash memory market in 2013. The NAND flash market is forecast to grow 12% in 2013, from $26.8 billion in 2012, according to IC Insights.

By Mark LaPedus
Over the years, suppliers of metrology equipment have managed to meet the requirements for conventional planar chips. But tool vendors now find themselves behind in the emerging 3D chip era, prompting the urgent need for a new class of 3D metrology gear.

3D is a catch-all phrase that includes a range of new architectures, such as finFET transistors, 3D NAND and stacked-die using through-silicon vias (TSVs). Although a few 3D-like devices have appeared in the market, many chipmakers are still developing these technologies and face several process control challenges.

“In our industry, a lot of segments are metrology-limited,” said Christopher Bencher, a member of the technical staff at Applied Materials. “Overlay metrology is the number one area where we are limited. There is also a challenge with 3D devices like finFETs and 3D NAND. You have to be able to characterize them in 3D.”

As with many fab tool markets, there is a disconnect between the rhetoric from chipmakers and equipment vendors. Process control tool vendors insist they are ready for the 3D era. In contrast, chipmakers say many of the existing metrology solutions are running out of steam.

For example, some 50% of the process steps in a fab are devoted to inspection and metrology alone. About 10% of those steps use the workhorse metrology tool in the fab—the critical-dimension scanning electron microscope (CD-SEM). With finFETs, the CD-SEM is being stretched to its limits. “Three quarters of the steps can be handled by a conventional CD-SEM,” said Eric Solecky, senior manufacturing engineer at IBM. “This percentage is growing. It’s that fraction for 3D information that we don’t have a solution today for an image-based tool.”

Near term, there are other challenges in process control. “The main gaps in general are next-generation defect inspection, next-generation charge particle imaging, and next-generation scatterometry profile metrology,” said Benjamin Bunday, senior technical staff member at Sematech. Longer term, the industry also lacks a process control solution for graphene, carbon nanotubes and directed self-assembly (DSA).

Metrology madness
Several tool types—AFM, CD-SEM and OCD—can handle most requirements for today’s planar chips. Atomic force microscopy (AFM) uses a tiny probe to enable measurements. The CD-SEM is used for top-down measurements. And used for CD and overlay, optical scatterometry (OCD) measures the changes in the intensity of light.

But the process control world changed in 2011, when Intel rolled out the industry’s first finFETs. Using a transmission electron microscope (TEM), Chipworks recently discovered that the traditional one-to-one ratio between structures and transistors doesn’t apply with Intel’s tri-gate technology. In fact, one transistor can have multiple fins—six or more—while one fin can have multiple transistors, according to Chipworks.

So for finFETs, a given metrology tool must measure and characterize the separate pieces in the structure, such as the gate, fin height, sidewall angle and others. Each of those parts also requires one or more separate measurements.

The question is which single metrology tool can handle all requirements for structures such as finFETs and 3D NAND? The answer: None of them. There is no silver bullet. “We are already in a deluge of data,” said Jason Osborne, senior systems design engineer at Bruker. “We’ve got many systems making multiple measurements on the same structures and not getting the entire answer off any one system.”

In one possible finFET metrology flow, the fin is measured by the CD-SEM or AFM, and then, the results are feed to the OCD tool. Another possible metrology flow involves the CD-SEM, OCD and a TEM. The TEM, a system that shoots a beam of electrons through a tiny specimen, is used to validate the OCD model. “What you are trying to do is make your scatterometry model more robust,” said John Allgair, senior member of the technical staff and Fab 8 patterning metrology manager at GlobalFoundries.

Intel, meanwhile, uses a combination of undisclosed tool technologies within its finFET process control flow. “We need all solutions,” said Adam Schafer, area manager of metrology and inspection at Intel. “We need to combine them.”

In process control, the biggest challenges for Intel can be summarized in three words—cost, noise and throughput. “Noise is one of our top problems. And it is really distinguishing the signal from the noise in any one of our techniques,” Schafer said.

Each tool type has its own set of issues. “If you are talking about CD-SEM, my CD measurement is traditionally top down. That’s not enough. I cannot control my processes with those CDs,” said Alok Vaid, senior member of the technical staff at GlobalFoundries. “Regarding OCD, it’s a solution, but it’s too complicated. So if you look at 14nm, 10nm and beyond, I don’t think the small dimensions are an issue for OCD. In fact, it can work in your favor. The problem is correlations.”

For AFM, the challenge is to measure finFETs in 10nm to 20nm spaces and characterize the profiles and shapes, he said. “We can’t leave optical tools such as ellipsometry out of the picture. Since everything is going 3D, now you want to measure those thicknesses and compositions on actual 3D structures,” he said.

The solutions
For some time, GlobalFoundries and others have been talking about the solution to the 3D problem—hybrid metrology. In this approach, separate tool technologies are used in a flow. The challenge is to put rival tool vendors in the same flow and tell the competitors to collaborate and share proprietary data with each other. “Let’s take an example. You have a CD-SEM supplier. You have an OCD supplier. And let’s say you want to overlap them and get my results. You can’t do that unless you get those guys to draw an algorithm together and get them to collaborate,” Vaid said.

While hybrid metrology is perhaps the wave of the future, tool vendors are also improving their respective technologies. For example, using Applied Materials’ CD-SEM, IBM conducted measurements in a theoretical gate-all-around finFET with silicon nanowires. In this experiment, “you see nice defined edges, even when you are beyond the resolution image,” said Ofer Adan, managing technology and marketing manager at Applied Materials. “So can we go beyond 14nm? What this work tells me is that a CD-SEM can go down to 6nm on a gate-all-around device.”

This is not to say the CD-SEM can handle all finFET requirements. “It cannot see whether or not there is an undercut. We need to work together with the OCD guys,” Adan said.

Overlay is another challenge and OCD is being stretched to the limits. KLA-Tencor recently unveiled a dimensional metrology system, which includes a new OCD technology based on a laser-driven source. “We think this is an inflection point for scatterometry,” said Andrei Shchegrov, director of advanced development at KLA-Tencor. “Our signal-to-noise gets a huge boost across a very wide range of wavelengths. We found the increased sensitivity due to the light source allows us to see things we couldn’t see before. It allows us to measure deep structures like high-aspect ratio 3D NAND flash.”

Despite the breakthroughs, the industry is still searching for new and better 3D metrology solutions. There are some promising candidates on the table. For example, a possible successor to the CD-SEM is helium-ion imaging. And X-ray scattering (CD-SAXS) could succeed OCD.

“The CD-SEM today, for the most demanding applications, cannot resolve 3D information,” said IBM’s Solecky. “So the question is, ‘Do you need 3D information on the smallest features?’ The answer is yes. Potentially, helium ion is the solution.”

Helium ion enables 3D images, but the technology also can damage a device. The industry is looking for ways to tweak the helium ion microscope, which would make it somewhat comparable to the CD-SEM. “Technically, this involves a lot of challenges to make (helium ion into) a CD-SEM kind of tool. Those are not unsolvable problems, but it requires a lot of investments,” said Bipin Singh, product manager for Zeiss, a supplier of helium ion scopes and other fab tools.

As a replacement for OCD, the industry is looking at CD-SAXS, an X-ray scattering technology based on a synchrotron radiation source. “If you want 3D structures, you can certainly do it with CD-SAXS,” said Joseph Kline, a materials engineer at NIST. “The main limiter for CD-SAXS is throughput. Most of the measurements with CD-SAXS are done with a synchrotron source. Clearly, we are not going to have something like this in the fab. We are trying to figure out how to get a new source and make it work.”

There are other major gaps in metrology. For example, the current buzz in lithography centers on DSA, but it’s unclear if the industry has a metrology solution. “Metrology needed for DSA is really not different than the metrology needed for the rest of the industry,” said Applied’s Bencher. “You need to measure the registration of the holes. Now, when you are defining all of your holes by a mask, things tend to shift systematically, at least within the mobile region of the wafer. So how do you obtain an overlay measurement when things on the local level are shifted randomly? That’s not clear. It requires a different way of thinking.”

By Jeff Chappell
There may have been a time when AMD founder Jerry Sanders famous quote: “real men (i.e., real companies) have their own fabs” rang true, but in today’s business climate it seems quaint at best.

Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues by offering foundry services—Intel and Samsung among them. Then there is the fact that the third-largest chipmaker in 2012, in terms of revenue, was a pure-play foundry.

As the 28nm node capacity ramp continues in the foundry market in 2013, following unexpected demand and capacity bottlenecks in 2012, today’s foundry market is the end result of market trends and forces with old roots. But those trends and forces have been compounded in modern times by extreme financial and market necessities, not to mention technology.

In one sense, however, at its core, the foundry market hasn’t changed since Taiwan Semiconductor Manufacturing Co. (TSMC) launched as the industry’s first pure-play foundry in 1987: Chip companies look to foundries, either as a customer or as a provider, to maximize productivity and thereby minimize costs. That part of the game hasn’t changed, whether it involves a component supplier designing power modules with 0.18-micron design rules for manufacturing on 200mm wafers, or one of the two GPU giants producing their next-generation graphics processors based on the latest technology.

The trend for years now has been fabless or fab-lite; even Sanders’ own AMD spun out its manufacturing arm several years ago to create one of the world’s largest pure-play foundries, GlobalFoundries. This has naturally in turn spawned the growth of the pure-play foundry market from its birth some 26 years ago.

Indeed, last year the overall foundry market enjoyed revenues of $29.6 billion, managing year-over-year growth of 12%, which is three times that of the chip industry over all in 2012. That growth caught everyone by surprise including the foundries themselves; 28nm capacity was tight for much of the year, even as yields improved dramatically—so much so that it reportedly impacted some capital equipment purchases, in spite of tight foundry capacity.

But that illustrates the biggest and most obvious change in the foundry industry in modern times: The foundries themselves are involved directly with developing leading-edge semiconductor technology. In fact, with the industry looking at the end of planar CMOS at the leading edge for some devices with the advent of 3D transistor architectures and the high-k materials they require, leading foundries no longer can rely on a mix of conventional scaling, publicly available data and equipment and process technology suppliers to get their jobs done. Research and development now must be within their purview, at least for those playing at the leading edge.

“Historically foundries don’t do R&D, their clients do it,” noted Dean Freeman, a research vice president at Gartner Research. That’s not so, today.

Nothing illustrates that fact better than TSMC’s R&D budget. In 2012 the company spent 33.8 billion NT, or about $1.13 billion, on R&D—a quarter of its revenue. This year the company plans to spend 40.4 billion NT, or about $1.35 billion, which includes adding some 500 people to its employee headcount, bolstering its R&D staff from 3,400 people to 3,900.

Indeed, leading foundries have joined the leading IDMs and technology consortia as purveyors of—not just manufacturers of—advanced technology.

While TSMC and its foundry brethren in the first tier of the pure-play market—Globalfoundries and United Microelectronics Corp. (UMC)—continue to build out 28nm capacity, they are also hard at work on the 20nm node and the subsequent hybrid 14/16nm finFET based on a 20nm back-end of line process. In fact, TSMC just announced first tapeouts of an ARM A-57 processor, based on the 64-bit ARMv8 processor series and built with 16nm transistor technology, including finFETs. This followed their rival’s announcement of a few months earlier. In February, GlobalFoundries announced a “first implementation” of a dual-core ARM A9 processor using the company’s 14nm-XM FinFET transistor architecture.

Follow the money
Being on the very leading edge of technology is driving growth among the first-tier foundries.

Like many others in the industry, TSMC and its chairman and CEO, Morris Chang, are quite bullish on the continued demand for 28nm technology as well as the development of 20nm technology. In general, 28nm designs, with their combination of lower power consumption and speedier transistors, have consequently proven cost-effective for a chip industry currently driven by mobile devices—smartphones, tablets and ultra lightweight notebooks. During TSMC’s review of its 2012 results earlier this year, Chang said the company will continue to aggressively grow its 28nm capacity and output; 2013 capacity and output will triple that of 2012, he said.

“It’s all about lower power with functionality and no sacrifice on the power requirements,” observed Kathryn Ta, managing director of strategic marketing for Applied Materials’ Silicon Systems Group. The equipment and process technology supplier’s foundry customers are seeing a need to move to 3D transistor architectures with minimal leakage, she said, because of those power requirements.

Development will continue at 20nm and 16nm as well at TSMC and its rivals. This year, 88% of the 9 billion NT that TSMC will spend on capital expenditures will go to 28nm, 20nm and 16nm capacity; an additional 5% will be spent on additional R&D equipment. Chang predicted that by Q3 of this year high-k metal gate production will surpass that of standard oxynitride gates, a gap that naturally will widen in Q4 and beyond.

“Enough discussions have taken place with enough customers … to lead us to believe that in both its first and second year of production (2014 and 2015, respectively) the volume of 20nm SoCs will be larger than that of 28nm in its first and second years of production (2012 and 2013),” Chang said.

He further noted that this represented the state of the art, and not just for the foundry industry, but for the industry as whole. This may indeed prove to be true in a few years as those 20nm and 16nm/14nm SoC devices move into production. It’s a far cry from the days when foundries were traditionally technological also-rans.

But then the first-tier foundries at the leading edge are still playing catch-up in the meantime with those IDMs at the leading edge, namely Intel. The world’s biggest chipmaker has kept Moore’s Law on track on the CPU side of the ITRS roadmap, last year having brought its Ivy Bridge processors to market. These feature 22nm transistors replete with finFETs; Intel’s own roadmap calls for 14nm designs to be in production in 2014; in terms of mobile SoCs like those the foundries are talking about, the company has promised its 22nm Atom SoCs will be in production in 2015.

“Intel seems to be able to continue to shrink because they spend a fortune on R&D,” said Gartner’s Freeman. “The foundries are pushing hard to catch up,” He noted that while both GlobalFoundries and TSMC have 16nm/14nm chips featuring finFETs in development, they are taking a shortcut, so to speak, by employing 20nm metal interconnects. “It’s close to what Intel is doing. Intel’s design may be more sophisticated, but the lithography is the same.”

Plenty of room, and business, at the trailing end
But not everybody in the foundry market is playing at the leading edge. The same market and industry forces that have induced the bigger pure-play foundries to move beyond their historical roles also have created a two-tiered pure-play foundry market. In the first tier are those that have the deep pockets to play in this space: TSMC, Globalfoundries, UMC, and to a lesser extent China’s Semiconductor Manufacturing International Corp. (SMIC).

Then there are the second-tier companies, those that are still fulfilling a traditional foundry role—at trailing edge processes, but nevertheless needed or even essential semiconductor manufacturing technology and capacity. Indeed, many second-tier foundries do quite well with their particular market niches and technologies. In the world of mobile consumer gadgets, including but not limited to smartphones and tablets, there are still many components fabricated on established, trailing-edge technology, such as sensors, microcontrollers and power components.

Even in 2013, where CPUs with 22nm transistors and mobile SoCs with 28nm transistors represent the current state of the art, some 40% of all silicon used to manufacture chips goes into mature devices fabricated on 200mm wafers. That’s typically 0.18-micron designs or larger. And much, if not most, of that is coming from pure-play foundries.

At the top of that second-tier foundry market, Israel’s TowerJazz, for example, has found a relatively comfortable niche making high-speed devices for a broad range consumer applications utilizing 0.13-micron designs and larger. It also makes CMOS image sensors with 0.16- and 0.11-micron design rules. In terms of financials, this has translated to record revenues: last year TowerJazz posted revenues of $638.8 million, an increase of 5% over the previous year.

Freeman suggested there are plenty of opportunities for these second-tier foundries. The so-called “Internet of Things,” for example, is a major driver behind sensor applications, as it is for the controllers needed to coordinate the data these sensors produce—data that can be managed via mobile Internet devices. These supplemental and complementary applications typically don’t need cutting-edge technology.

As has always been the case in the foundry industry, as leading-edge technology becomes trailing-edge, there will be new opportunities for second-tier foundries, as well. Some of the larger second-tier foundries eventually may have the opportunity to compete with first-tier companies head-to-head with 28nm capacity if they have deep-enough pockets to invest.

In the bifurcated smartphone market, for example, low-end smartphones that originally utilized chips manufactured with 40nm technology soon will migrate to chips with 28nm technology, as capacity ramps and it becomes even more cost effective, said Applied’s Ta. Even as the leading-edge players are driven beyond the 28nm node and the adoption of 3D gate architectures, the industry could very well see an extended 28nm node, driven by this market for lower-end smartphones and other mobile devices, she said.

But What About …
Things rarely ever prove to be so clearly defined in the chip industry. With players such as Samsung, Intel and IBM among others flirting with the foundry business, and some of the larger first-tier foundries suffering the same financial headaches that have plagued the IDMs in the past—problems that drove some of them to a fabless model in the fist place—there are some significant unknowns.

While 3D, high-k metal gate architectures, i.e, finFETs and the like, seem to be the wave of the near future, there are still those in the industry that tout the efficacy of fully depleted silicon-on-insulator (FD-SOI) as either an alternative to complement to 3D gate technology, for example.

IBM and its technology alliance partners have considered FD-SOI as a possible outcome of the semiconductor technology roadmap in the near future, Ta noted. “We see most of the effort on the finFET/Intel approach, but some of our customers are still talking about SOI,” perhaps used in some combination with finFETs, she added.

Gartner’s Freeman noted that Intel’s finFET devices are already fully depleted devices, although SOI could conceivably provide a bit less leakage; as such it may be an option at future nodes. Given the transistor speed and power usage achieved by its 22nm Atom processors, which are manufactured on top of bulk silicon technology, that seems unlikely though for Intel and those choosing to follow its lead. Freeman further observed that GlobalFoundries, once a proponent of FD-SOI, has backed off somewhat, although some of its largest customers remain committed to an FD-SOI strategy for the foreseeable future. IBM, for one, has publicly stated it will use FD-SOI, finFETs and stacked die together at future nodes.

But what does this mean for the leading-edge foundries? As always they will have to be able to manufacture what their customers want. It may be that some chipmakers will choose to go the FD-SOI route and that could prove a competitive opportunity for any foundry.

Another wild card that the top-tier foundries will need to take into account is the overlapping of technology nodes, which may become more pronounced with the extension of the 28nm node coupled with the rush to get 20nm devices into production. “It’s happening faster than previous node transitions have happened,” Applied’s Ta, noting that it’s driven by the low-power promise of finFETs. In the past node transitions typically took two to 2.5 years; “This time we may see a 1.5 year transition to finFETs,” she added.

Another question mark in the foundry market itself is SMIC. While most would still classify the Chinese foundry as a top-tier foundry, it is in a very real way straddling the gap between first and second tier. The company, once relatively close behind TSMC and UMC, has foundered in red ink and legal woes in recent years. While it has subsequently experienced an impressive turnaround financially under the helm of current CEO Tzu-Yin Chiu in 2012, it’s capital expenditures fell dramatically, even as capacity utilization hit 95% in Q2, and it is well behind its rivals in terms of technology.

Customer tapeouts of 28nm devices won’t take place until the end of this year; One of SMIC’s largest domestic customers, Spreadtrum, already has been forced to move to rival TSMC to meet its current plans for 28nm devices.

SMIC’s Chiu has said that the company’s 28nm technology will include both standard polysilicon oxynitride devices and high-k metal gates, and that it has plans to manufacture finFET devices at the 20nm node. In the meantime, it has found a saving grace in applications typically manufactured by second-tier players: smart cards, CMOS image sensors and power management chips.

Which way will SMIC go? Will it continue its impressive turn around by abandoning the leading edge or will it continue to play technological catch up? Or perhaps a little bit of both?

Time will tell. But it’s certainly an interesting time for the foundry business, and certain that for the foreseeable future the pure-play foundries will have to work hard at the cutting edge of semiconductor technology.

By Mark LaPedus
The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs.

DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from the lab to the fab.

Perhaps the most glaring gap involves the ability to design chips around DSA. The existing EDA tools are not optimized for DSA, leaving many skeptics to ask a simple question: Can chipmakers design real and useful chips around DSA? Today, the answer is no or maybe someday.

Still, the lack of a design methodology opens up the door for new innovation and the emergence of a new field—design-for-DSA (DFD). In fact, there are some early methodologies surfacing for DFD. One idea is to tweak the current EDA tools for DSA. Another concept is to use 1D layouts. In another approach, Stanford University is developing a methodology using an alphabet soup of characters.

And not to be outdone, Cadence is working with GlobalFoundries to devise yet another approach. The technology, called Squish, uses an underlying classification engine and topological patterns as a means to enable IC designs using DSA, said Luigi Capodieci, director of DFM/CAD and an R&D fellow at GlobalFoundries.

“We have developed the first implementation of DSA modeling,” Capodieci said. “It’s a different way to look at physical design. The introduction of Squish topological patterns is a new way to look at how polygons and shapes come together. We can also enumerate how the patterns come together in a way we can match them.”

To make DSA viable, Capodieci also said that the EDA industry must look at the problem differently and develop an entirely new design methodology. “We need innovation,” he said. “We need a fundamental methodological change in how we put together the physical design.”

Assembling a design
DSA is not a next-generation lithography (NGL) tool per se. It’s more of a complementary and double-patterning scheme. There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

Over the last year, Albany Nanotech, CEA-Leti, IBM and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations and have shown their initial test structures using DSA.

It’s one thing to show intricate patterns and test structures, but it’s an entirely different matter to design chips around the technology. “It’s not good enough to have SEM pictures and show them at a conference,” said Lars Liebmann, a distinguished engineer for design technology co-optimization at IBM. “I can’t do anything with that. To really get your foot into the door you have to demonstrate some circuit-relevant patterns. If you show me a SEM, also show me a circuit pattern where a designer would say: ‘I can do something with that.’”

To satisfy the design community, DSA must meet some basic criteria. “You have to be able to integrate this patterning approach into a real CMOS flow. You have to demonstrate etch selectivity. And any new patterning technique should come with a set of compact models,” Leibmann said.

And, of course, there must be a robust design methodology and EDA tools. “The tools are not ready for DSA,” said Juan Rey, senior director of engineering at Mentor Graphics. “Essentially, the DSA community has developed a credible path for some layers. However, there is quite a bit of extensive research needed for full-chip-level development.”

All told, DSA still remains in the early stages of development and not ready for prime time. “We’ve seen some outstanding first steps in DSA,” Rey said. “But it’s pretty clear that more progress is required. The technology is still immature.”

Wanted: DFD
For some, the design-for-DSA debate centers around one question. “The question is not whether the EDA tools ready,” said GlobalFoundries’ Capodieci. “The question is what are the EDA tools required for DSA?”

One of the prevailing ideas is to use a complementary lithography approach as outlined by Intel. First, poly and metal lines are arranged into 1D gridded arrays. Then, a cut step is done to form a specified pattern. All told, DSA could enable lines and spaces, contact hole shrinks and even patterning a sea of fins.

Using a variant of complementary lithography, IBM has demonstrated the ability to pattern 29nm-pitch fins, which are etched onto a silicon-on-insulator (SOI) substrate. For DSA in general, IBM is using its own, in-house tools as well as conventional technology, said Kafai Lai, a senior scientist/engineer at IBM. “Our computational infrastructure basically builds upon conventional computational lithography platform. Many existing technical elements such as mask decomposition and coloring algorithms, model-based sub-resolution assist features (SRAF) and printable assist features (PRAF), source mask optimization (SMO), DSA optical proximity correction (DSA OPC), OPC verification, are still the building blocks of the DSA infrastructure. The optimum flow for DSA implementation depends on the feature types or the process layers of concern,” Lai said in a recent paper at SPIE.

“We have developed a set of computational lithography tools to enable us to evaluate the application of DSA to full-chip patterning. These toolsets involve new DSA-specific components such as DSA mask decomposition for guiding patterns, DSA-specific OPC or mask optimization and DSA-OPC verification. A fast DSA compact model is the backbone of these new CL components and we have reported such a fast DSA model for vias. A similar compact model for DSA L/S is under development now,” he added.

In any case, 1D layouts may enable DSA-friendly designs, but chipmakers must adhere to some rigid and restrictive design rules. “The designers will say I’m in left field, but I really think we need to spend more time working on the grid approach,” said Christopher Bencher, member of the technical staff at Applied Materials.

Using the 1D layout approach, memory makers could be the early adopters for DSA. For logic, Bencher and others have proposed a scheme that enables a sea of fins for use in future finFET designs. “For example, in the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which holes you want to keep and which ones you want to get rid of,” he said.

The downside to this approach is the inability to obtain a good aerial image of the holes. Still, Bencher said the 1D layout approach has several advantages over the rival alphabet-soup method. In this approach, a designer has the ability to choose a collection of shapes to develop a design. “As you try and stuff more and more (shapes on a pattern), the amount of positional error starts to go up,” he added.

The 1D gridded array approach also has some challenges. “You have to demonstrate some form of self-aligned trimming,” said IBM’s Leibmann. “Otherwise, in tight pitch gratings, it’s not useful at all because you can’t customize it. There is also no tool with the overlay capability to actually map that selectively without either damaging the fins you want to keep or residuals from the fins you want to erase.”

For this and other reasons, it’s unclear if the foundry industry can deploy this methodology. “Gridded with ultra-regular designs won’t work for us,” said Richard Farrell, a principal engineer at GlobalFoundries. “The biggest problem is that we incur a 3% to 5% area penalty for a gridded design, which is something we can’t give up.”

In the 1D layout approach, the IC industry would still require a new class of tools from the established EDA companies or startups willing to take a gamble. “This is possible, but you have to have a dedicated group of people with some capital who are willing to think differently,” said GlobalFoundries’ Capodieci. “But if we just wait for the commercial opportunity to present itself, we will miss the boat.”

Working with Cadence, GlobalFoundries proposes Squish, a design-for-DSA methodology that appears to combine the alphabet-soup approach and today’s pattern matching/classification technology. “This is like doing a Google search,” Capodieci said. “We actually create artificial structures in which patterns can come together.”

For example, the Squish methodology can create 1,716 or so different configurations or representations for a proposed IC layout. “We have the tools we need for classifying geometric and physical designs,” he said. “In literally a few hours, we can analyze a full-chip layout.”

Once this or another methodology is proven viable, the next step is to actually design and make a chip using DSA. “The next challenge for the industry is to process a couple of layers of a processor core using DSA,” he said. “We need a call for action.”