Part of the  

Solid State Technology

  Network

About  |  Contact

Posts Tagged ‘Applied Materials’

Next Page »

Blog review October 27, 2014

Monday, October 27th, 2014

Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.

Phil Garrou blogs that most of us know of Nanium as a contract assembly house in Portugal who licensed the Infineon eWLB fan out technology and is supplying such packages on 300mm wafers. NANIUM also has extensive volume manufacturing experience in WB multi-chip memory packages, combining Wafer-level RDL techniques (redistribution) with multiple die stacking in a package.

Gabe Moretti says it is always a pleasure to talk to Dr. Lucio Lanza and I took the opportunity of being in Silicon Valley to interview Lucio since he has just been awarded the 2014 Phil Kaufman award. Dr. Lanza poses this challenge: “The capability of EDA tools will grow in relation to design complexity so that cost of design will remain constant relative to the number of transistors on a die.”

Are we at an inflection point with silicon scaling and homogeneous ICs? Bill Martin, President and VP of Engineering, E-System Design thinks so. I lays out the case for considering Moore’s Law 2.0 where 3D integration becomes the key to continued scaling.

Congratulations to Applied Materials Executive Chairman Mike Splinter on receiving the Silicon Valley Education Foundation’s (SVEF) Pioneer Business Leader Award for driving change in business and education philanthropy by using his passion and influence to make a positive impact on people’s lives.

At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations. As Adele Hars reports, speakers included experts from Synopsys, ST, GF, Soitec, IBS, Synapse Design, VeriSilicon, Wave Semi and IBM.

Blog review September 22, 2014

Monday, September 22nd, 2014

Siobhan Kenney of Applied Materials reports that The Tech Museum of Innovation announced the ten recipients of the Tech Awards. Presented by Applied Materials, this is a global program honoring innovators who use technology to benefit humanity. These incredible Laureates are addressing some of the world’s most critical problems with creativity – in naming their organizations and in designing solutions to improve the way people live.

Jean-Pierre Aubert, RF Marketing Manager, STMicroelectronics says RF-SOI is good for more than integrating RF switches.  Other key functions typically found inside RF Front-End Modules (FEM) like power amplifiers (PA), RF Energy Management, low-noise amplifiers (LNA), and passives also benefit from integration.

Phil Garrou blogs Samsung finally announced that it has started mass producing 64 GB DDR4, dual Inline memory modules (RDIMMs) that use 3D TSV technology. The new memory modules are designed for use with enterprise servers and cloud base solutions as well as with data center solutions [link]. The release is timed to match the transition from DDR3 to DDR4 throughout the server market.

Stephen Whalley, Chief Strategy Officer, MEMS Industry Group, blogs about the inaugural MIG Conference Shanghai, September 11-12th, with their local partners, the Shanghai Industrial Technology Research Institute (SITRI) and the Shanghai Institute of Microsystem and Information Technology (SIMIT).  The theme was the Internet of Things and how the MEMS and Sensors supply chain needs to evolve to address the explosive growth in China.

SEMI praised the bipartisan effort in the United States House of Representatives to pass H.R. 2996, the Revitalize American Manufacturing and Innovation (RAMI) Act.  SEMI further urged the Senate to move quickly on the legislation that would create public private partnerships to establish institutes for manufacturing innovation.

Jeff Wilson, Mentor Graphics, writes that in integrated circuit (IC) design, we’re currently seeing the makings of a perfect storm when it comes to the growing complexity of fill. The driving factors contributing to the growth of this storm are the shrinking feature sizes and spacing requirements between fill shapes, new manufacturing processes that use fill to meet uniformity requirements, and larger design sizes that require more fill.

Zvi Or-Bach, president and CEO of MonolithIC 3D, blogs that at the upcoming 2014 IEEE S3S conference (October 6-9), MonolithIC 3D will unveil a breakthrough flow that is game-changing for 3D IC. For the first time ever monolithic 3D (“M3DI”) could be built using the existing fab and the existing transistor flow.

Design and Manufacturing Technology Development in Future IC Foundries

Tuesday, September 16th, 2014

thumbnail

By Ed Korczynski, Sr. Technical Editor

Virtual Roundtable provides perspective on the need for greater integration within the “fabless-foundry” ecosystem

Q1:  The fabless-foundry relationship in commercial IC manufacturing was established during an era of fab technology predictability—clear litho roadmaps for smaller and cheaper devices—but the future of fab technology seems unpredictable. The complexity which must be managed by a fabless company has already increased to justify leaders such as Apple or Qualcomm investing in technology R&D with foundries and with EDA- and OEM-companies. With manufacturing process technology integrating more materials with ever smaller nodes, how do we manage such complexity?

ANSWER:  Gregg Bartlett, Senior Vice President, Product Management, GLOBALFOUNDRIES

The vast majority of Integrated Device Manufacturers (IDMs) have either gone completely fabless or partnered with foundries for their leading-edge technology needs instead of making the huge investments necessary to keep pace with technology. The foundry opportunity is increasingly concentrated at the leading edge; this segment is expected to drive 60 percent of the total foundry market by 2016, representing a total of $27.5 billion. Yet there are fewer high-volume manufacturers that have the capabilities to offer leading-edge technologies beyond 28nm, even as the major companies have accelerated their technology roadmaps at 20nm and 14nm and added new device architectures.

This has led to a global capacity challenge. Leading-edge fabs are more expensive and fewer than ever. At the 130nm node, the cost to build a fab was just over $1B. For a 28nm fab, the cost is about $6B and a 14nm fab is nearly $10B. Technology development costs are rising at a similar rate, growing from a few $10M’s  at 130nm to several $100M’s at 28nm.

On top of these technology and manufacturing challenges, product life cycles are shrinking and end users are expecting more and more from their devices in terms of performance, power-efficiency, and features. Competing on manufacturing expertise alone is no longer a viable strategy in today’s semiconductor industry, and solutions developed in isolation are not adequate. The industry must work closer across all levels of the supply chain to understand these dynamics and how they put demands on the silicon chip.

Fortunately, the fabless/foundry model is evolving to accommodate these changing dynamics. We have been promoting this idea for years with what we like to call “Foundry 2.0.” In the 1970s/1980s, the industry was dominated by the IDM. Then the foundry model was invented and grew to prominence in the 1990s and early 2000s, but it was much more of a contract manufacturing model. A fabless company developed a design in isolation and then “threw it over the wall” to the foundry for manufacturing. There was not much need for interplay between the two companies. Of course, as technology complexity has increased in the past decade, this dynamic has changed dramatically. We have entered the era of collaborative device manufacturing. Collaboration is a buzz word that gets thrown around a lot, but today it really is critical and it needs to happen across all vectors, including design flow development, manufacturing supply chain, and customer engagement.

Q2:  3D in packaging started with wire-bonded-chip-stacks and now includes silicon-interposers (a.k.a. “2.5D”) and the memory-cube using through-silicon via (TSV). How about the complexity of 3D products using chip-package co-design, and many players in the ecosystem being needed hroughout design-ramp-HVM?

ANSWER:  Sesh Ramaswami, Managing Director, TSV and Advanced Packaging, Silicon Systems Group of Applied Materials

Enabling 3D requires the participation of the extended ecosystem. These include contributions from CAD, design tools for die architecture, floor plan, and layout circuit design test structures, as well as methodology wafer level process equipment and materials, wafer-level test assembly and packaging stacked die and package level testing.

Q3:  Due to challenges with lithographic scaling below 45nm half-pitch, how does the need to integrate new materials and device structures change the fabless-foundry relationship? How much of fully-depleted channels using SOI wafers and/or finFETs, followed by alternate channels can the industry afford without commited damand from IDMs and major fabless players for specific variants?

ANSWER:  Adam Brand, Director of Transistor Technology, Silicon Systems Group of Applied Materials

New materials and device structures are going to play a key role in advancing the technology to the next several nodes.

With EUV delayed, multi-patterning is growing in use, and new materials are enabling the sophisticated and precise extension of multi-patterning to the 7nm node and beyond.  The multi-patterning schemes however bring specific restrictions on layout which will affect the design process.

For device structures, Epi in particular is going to enable the next generation of complex device designs with improved mobility and by supporting very thin precisely defined channel structures to scale to smaller gate length and pitch. For these next generation devices, the R&D challenges will be high, but the industry cannot afford to skimp on R&D to find the winning solution to the low power transistor technology required for the 7nm and 5nm and beyond nodes.

Q4:  Mobile consumer devices now seem to drive the leading edge of demand for many ICs. However, the Internet-of-Things (IoT) is often spoken of needing just 65nm node chips to keep costs as low as possible, and these designs are expected to run in high volume for many years. How will these different devices that will continue to evolve in different ways get integrated together?

ANSWER: Michael Buehler-Garcia, Senior Director of Marketing, Calibre Design Solutions of Mentor Graphics

IOT has become the new industry buzz word.  What it has done is spotlight the multiple elements of a complete solution that do not require emerging process technologies for their chip design. Moreover, while a chip may use a well established process node, the actual design may be very complex. For example Mentor is participating in the German RESCAR program to increase the reliability of automotive electronics using our Calibre PERC solution. The initial reliability checks written are targeted for 180nm and older process nodes. Why? Because today’s 180nm and older node designs are much more complex than when these nodes were mainstream digital nodes and as such require more advanced verification solutions. Bottom line:  as opposed to a strategy of only moving to the next process node, chip design companies today have multiple options.  It is up to the ecosystem to provide solutions that allow the designers be able to make trade-offs without major changes in their design flows.

FIGURE: Reliability simulation as part of “RESCAR” program. (Source: Fraunhofer IZM)

Blog review September 8, 2014

Monday, September 8th, 2014

Jeff Wilson of Mentor Graphics writes that, in IC design, we’re currently seeing the makings of a perfect storm when it comes to the growing complexity of fill. The driving factors contributing to the growth of this storm are the shrinking feature sizes and spacing requirements between fill shapes, new manufacturing processes that use fill to meet uniformity requirements, and larger design sizes that require more fill.

Is 3D NAND a Disruptive Technology for Flash Storage? Absolutely! That’s the view of Dr. Er-Xuan Ping of Applied Materials. He said a panel at the 2014 Flash Memory Summit agreed that 3D NAND will be the most viable storage technology in the years to come, although our opinions were mixed on when that disruption would be evident.

Phil Garrou takes a look at some of the “Fan Out” papers that were presented at the 2014 ECTC, focusing on STATSChipPAC (SCP) and the totally encapsulated WLP, Siliconware (SPIL) panel fan-out packaging (P-FO), Nanium’s eWLB Dielectric Selection, and an electronics contact lens for diabetics from Google/Novartis.

Ed Koczynski says he now knows how wafers feel when moving through a fab. Leti in Grenoble, France does so much technology integration that in 2010 it opened a custom-developed people-mover to integrate cleanrooms (“Salles Blanches” in French) it calls a Liaison Blanc-Blanc (LBB) so workers can remain in bunny-suits while moving batches of wafers between buildings.

Handel Jones of IBS provides a study titled “How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales” that concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics.

Gabe Moretti of Chip Design blogs that a grown industry looks at the future, not just to short term income.  EDA is demonstrating to be such an industry with significant participation by its members to foster and support the education of its future developers and users through educational licenses and other projects that foster education.

Lithography: What are the alternatives to EUV?

Thursday, August 28th, 2014

By Pete Singer, Editor-in-Chief

EUV received a recent boost with IBM reporting good results on a 40W light source upgrade to its ASML NXE3300B scanner, at the EUV Center of Excellence in Albany. The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.  In the first 24 hours of operation after the upgrade, 637 wafer exposures were completed in normal production lot mode. Dan Corliss, the EUV Development Program Manager for IBM, called it a “watershed moment.”

Critics, most notably analyst Robert Maire of Semiconductor Advisors, said it was “not that much of a real increase in power and certainly no breakthrough, just incremental improvement.” He adds: “We still don’t have the reticle “ecosystem,” the resist and many other components to make for viable, commercial EUV production. We are still a very long way away and this does not change the view that EUV will not be implemented at 10nm.” The 10nm node is slated to go into production in late 2015/early 2016.

Yet EUV proponents remain optimistic. Kevin Cummings, the director of lithography at SEMATECH, said “It is good news indeed to hear that IBM in conjunction with ASML has met/exceeded their projected productivity. It is clear to this industry that the EUV LPP source was not meeting the desired schedule and the source improvements timelines were over promised. However this announcement give us some confidence that we are making progress against that schedule. In addition, this milestone is significant in that it allows the wafer throughput needed to continue EUVL HVM development. With the throughputs obtained on the scanner and the recent successes from SEMATECH on zero defect mask blanks and low-dose high-resolution resists now is an excellent time to take advantage of the Albany NY based capability to develop the materials and processes that will be needed for EUVL manufacturing.”

Luc Van den hove, president and CEO of imec, described EUV as a cost-effective lithography approach that is “absolutely needed.” In terms of imaging performance, imec has been characterizing some of the latest hardware together with ASML and have showed very good resolution performance of 13nm half pitch and 22nm contact holes. “With double patterning, we have even demonstrated 9nm half pitch,” Van den hove said. “Who would have thought a couple of years ago that this would be realizable with lithography?”

An Steegen, senior vice president of process technology at imec, said the ideal entry point for EUV is the 10nm node (or N10 using imec’s terminology). “If you look at the cost calculation, the best entry point for EUV is actually at N10 because you can replace triple patterning layers in immersion with a single patterning layer in EUV,” Steegen said. Since that will come relatively soon with early production occurring toward the end of 2015 and in early 2016, that means that likely the whole development phase will have already been built on immersion and multi-patterning. “Likely you will see on the most difficult levels, a swap, an introduction of EUV at the most critical levels later on in manufacturing for N10,” Steegen said.

Interestingly, industry-leader Intel has said that it will not use EUV for 14nm, and even sees a path to 10nm without EUV. At the Intel Developer’s Forum in 2012, Mark Bohr, director of Intel’s technology and manufacturing group said 10nm “would require quadruple patterning for some mask layers but it’s still economical.”

FIGURE 1. Multi-patterning can achieve sub-10nm dimensions. Source: Applied Materials.

FIGURE 2. Multi-patterning adds many process steps, and cost. Source: ASML.

FIGURE 1 shows that the use of spacers can enable sub-10nm dimensions without EUV. FIGURE 2 shows multi-patterning adds to process cost and complexity.

Earlier this year, at the SEMI Northeast Forum held in North Reading, MA, Patrick Martin, Senior Technology Director at Applied Materials, talked about scaling and the rising cost and complexity of patterning. “There’s a lot of talk in the industry about how scaling is dead,” he said. I think a lot of the discussions are if we look at the current architectures entitlements – finFET related technologies that scale to 7nm and 5nm, and the complexity associated with litho, driving those types of cost models, I would have to agree. But the argument is really going to be on architecture entitlement. How the devices are going to adapt to these pattern complexity limited challenges.”

Terry Lee, the chief marketing officer for the DSM business unit at Applied Materials says continued scaling will not be driven as much by lithography, but by 3D. “Scaling used to be enabled by lithography,” he said in a presentation at this year’s Semicon West. “What we’re seeing is the move to enable scaling using both materials and 3D device architectures.” 3D devices include FinFETs, 3D NAND DRAMs with buried word lines and bit lines. These devices represent “the drive to further scale on a third dimension versus scaling using lithography on a horizontal plane,” Lee said. Appled Materials recently introduced a several new products aimed at the 3D device market, including the Producer XP Precision CVD system.

“We’re really in a dilemma when it comes to semi-related production capability,” Martin said. The device features are much smaller than the wavelength that we’re using. We’re into these complex processing related technologies that require double patterning, triple patterning, multiple patterning. The great equalizer here is EUV. If we can ever get to EUV-related manufacturing capability, it gets us to a regime where the devices are relatively the same size as the wavelength of light. The problem is that it’s been delayed. The challenge is if it doesn’t hit 10nm, we’re looking at 7nm. If we start looking at the insertion opportunity for EUV at 7nm and 5nm, we’re now below wavelength. 13.5 nm is the wavelength of EUV. The complexities associated with double patterning come back into play,” Martin added.

The EUV mask challenge

The next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. According to Veeco’s Tim Pratt, Senior Director, Marketing, the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV. “Based on the yield today, the mask blank manufacturing capacity can’t produce enough mask blanks to support the ASML scanners that they’re planning to ship,” Pratt said. “ASML is going to be delivering some light source upgrades in the field and when those start happening, the effective total wafer throughput of EUV scanners in the field is going to multiply and there’s just not the supply of usable mask blanks to be able to support those.”

The requirement for 2015 is to have zero blank defects larger than 62nm. SEMATECH in 2012 reported work showing eight defects larger than 50nm. “A lot of progress being made but the elusive zero defects has not yet been hit,” Pratt said. Veeco, which is the sole supplier of EUV multilayer deposition tools, has plans to upgrade the existing Odyssey tool and launch a new platform in the 2017/2018 timeframe.

FIGURE 3. EUV masks are considerably more complicated than conventional photomasks. Source: Veeco.

FIGURE 3 shows an EUV mask, which is considerably more complicated than conventional photomasks.

What could derail the EUV ramp, according to Pratt, is a supply of defect-free mask blanks. “EUV is, despite many years and many dollars of investment, not yet in production. The two main gaps are the EUV light sources and the defects on the mask. As they start to make progress, people start to look more seriously at the list of things to worry about for EUV going to production.

The e-beam alternative

There are only a few alternatives to EUV and complex (and costly) mutli-patterning approaches: multi-e-beam (MEB), nanoimprint and directed self-assembly. Electron beam lithography with a single beam has been used for many years for mask writing and device prototyping, and tools available from a number of companies, such as Advantest, IMS, JEOL and Vistec.

Single-beam writing has never been able to compete with massively parallel optical systems in throughput and cost. Now, TSMC’s Burn Lin says that the time for e-beam lithography has arrived. Why? Digital electronics can affordably provide a gigabit per second data rate in a manageable space, enabling very high wafer throughput. Microelectrical mechanical systems and packaging techniques have advanced sufficiently to support a several order of magnitude increase in beam number and high-speed beam writing. And e-beam techniques generally offer higher resolution than optical systems. [1] Last year, TSMC and KLA-Tencor presented a reflective e-beam lithography (REBL) system that can potentially enable multiple-e-beam direct-write for high-volume manufacturing.

Multiple beam systems are also being developed by Multibeam Corp. (the well known David Lam is CEO), IMS and MAPPER. MAPPER was founded in 2000 by Professor Pieter Kruit and two of his recent graduates Marco Wieland and Bert Jan Kampherbeek.

What’s intriguing about e-beam direct write is that it could be used in conjunction with more conventional immersion lithography. Yan Borodovsky, Intel Corporation Sr. Fellow and Director of Advanced Lithography, calls it “complementary lithography.” He says that EBDW could be used instead of EUV to break the continuity of the grating made using 193i with pitch division. In addition to again maintaining the benefits of mature 193i on the critical layer, this solution has lower mask costs (no mask required for grating cutting and vias), and the escalating cost of the mask-making infrastructure is avoided.

He reported that EBDW could also be used instead of EUV for the complementary solution to break the continuity of the grating made using 193i with pitch division. In addition to again maintaining the benefits of mature 193i on the critical layer, this solution has lower mask costs (no mask required for grating cutting and vias), and the escalating cost of the mask-making infrastructure is avoided.

An organization that is focused on developing e-beam technology for mask writing and direct write is the E-beam Initiative (www.ebeam.org).

Nanoimprint

Step and Flash Imprint Lithography (SFIL), a form of ultraviolet nanoimprint lithography (UV-NIL), is recognized for its resolution and patterning abilities. It is one of the few next generation lithography techniques capable of meeting the resolution requirements of future semiconductor devices. Austin-based Molecular Imprints, now a wholly owned subsidiary of Canon, has successfully commercialized the technology. Molecular Imprints invested $165 million over the last decade on platforms, materials, templates and applications.

In 2004, Canon began conducting research into nanoimprint technology to realize sub-20nm high-resolution processes began carrying out joint development with Molecular Imprints and a major semiconductor manufacturer in 2009. Canon says NIL offers such benefits as high-resolution performance, exceptional alignment accuracy and low cost. However, others report that many integration issues such as defectivity, throughput, and overlay must be resolved before SFIL can be used for leading-edge semiconductor high volume manufacturing.

DSA is very promising

Imec’s Van den hove described direct self-assembly (DSA) as “very promising” and Steegen said work there has largely focused on reducing defectivity. In DSA, resists that contain block copolymers are deposited on top of guiding structures. The self-directed nature of the process results in very regular patterns with very high resolution.

The trick with DSA is that it requires a double exposure to take away the random patterns at the edge of the device, and the resolution needed for this “cut mask” is also very high. “We’re convinced that it’s not a replacement for EUV or any high resolution lithography technique. We are very convinced it will be used in conjunction with EUV,” Van den hove said. “It certainly keeps the pressure on EUV very high.”

Steegen described DSA as a complimentary litho technique that is having quite some momentum. The process starts with a “relaxed” guiding pattern on your wafer.  Then, depending on the polymer length in the block copolymer, the space in between the guiding structure is replicated into multiple lines and spaces. “The defectivity of these materials are going to be key to bring the defects down. Our year end target is 60 defects/cm2 and this needs to go down even further next year,” she said.

Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” Steegen said. Imec is already looking at where DSA levels could be inserted into the logic N7 flow, with fins and spacers being primary targets. Steegen said the Metal1 level would be a challenge due to its irregular pattern. “That makes it not easy to be replaced with DSA, but we’re looking into techniques to do that,” she said.

Here’s how imec summed up DSA readiness:

• Good progress in material selection and integration flow optimization for line-multiplication down to 14nm, pattern transfer into bulk Si demonstrated.

• First templated DSA process available using SOG/SOC hard mask stack.

• Focus on defectivity reduction & understanding, currently at 350 defects/cm2, YE13 target 60 def/cm2

• Alignment and overlay strategy needs to be worked out

• First N7 implementation levels identified: Finfet (replace SADP EUV or SAQP 193i) and Via (replace EUV SP/DP or 193i LE3).

Conclusion

Hopes remain high for EUV, but long delays has caused attention to shift to possible alternatives. Multi-level patterning is costly but it works; Intel, for example, says it will soon have 14nm devices in production without using EUV. Mutli-ebeam work continue apace, and we could see a role in direct write e-beam in a complementary approach with conventional lithography. Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. Some new device structures, such as vertical NAND and FinFETs, take the pressure off of lithography, but create challenges in other process areas, such as deposition and etch.

Blog review July 14, 2014

Monday, July 14th, 2014

Ed Korzynski blogs that Moore’s Law is dead – including what and when in the first two parts of a four part series that reference an interview with Gordon Moore and the “so-called” Moore’s Law (by Moore himself).

Pete Singer also blogs on continued scaling, as discussed by IBM’s Gary Patton at The ConFab in June. Patton said scaling will continue but the industry needs to address costs in addition to continued technology innovation.

Many of the developments in the semiconductor industry have stemmed from the continued progress in lithography. However, with the persistent uncertainty of extreme ultraviolet EUV for future-generation patterning, the industry has developed techniques such as self-alignment double patterning (SADP) to extend optical lithography. In a video produced by SPIETV, Chris Bencher of Applied Materials Office of the Chief Technology Officer, reviews the evolution of SADP and looks to its future.

The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu. Adele Hars reports.

The 5th annual Suss Technology Forum was recently held at SEMICON West focused on trends in 3DIC and WLP. Phil Garrou reports in his latest blog.

Blog review June 30, 2014

Monday, June 30th, 2014

Pete Singer blogs that at The ConFab last week, IBM’s Gary Patton gave us three reasons to be very positive about the future of the semiconductor industry: an explosion of applications, the rise of big data and the need to analyze all that data.

Tony Chao of Applied Materials writes that Applied Ventures will be participating in the second-annual Silicon Innovation Forum (SIF) held in conjunction with SEMICON West 2014 in San Francisco on Tuesday, July 8. The forum is designed to bring new and emerging innovators together with the semiconductor industry’s top strategic investors and venture capitalists (VCs), in order to enable closer collaboration and showcase the next generation of entrepreneurs in microelectronics.

Adele Hars of ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news. Malier said that CEA-Let has been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development.

Phil Garrou blogs that last week at the 2014 ISC (International Supercomputing Conference) it was announced that the Intel Xenon Phi processor “Knights Landing” would debut in 2015. It will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can work on up to four threads per core.

Solid State Watch: May 23-29, 2014

Wednesday, June 4th, 2014
YouTube Preview Image

Blog review June 2, 2014

Monday, June 2nd, 2014

The Internet of Things alone will surpass the PC, tablet and phone market combined by 2017, with a global internet device installed base of around 7,500,000,000 devices. Speaking at ASMC, TSMC’s John Lin said in addition to a continued push to smaller geometries and ultra-low power, the company will focus on “special” technologies such as image sensor, embedded DRAMs, high-voltage power ICs, RF, analog, and embedded flash. “All this will support all of the future Internet of Things,” he said.

Kavita Shah of Applied Materials blogs about the company’s new Volta system. She says desighed to alleviate roadblocks to copper interconnect scaling beyond the 2Xnm node through two enabling applications—a conformal cobalt liner and a selective cobalt capping layer, which together completely encapsulate the copper wiring.

In an interview, Christophe Maleville, Senior Vice President of Soitec’s Microelectronics Business Unit, talks about why FD-SOI provides a much better combination of power consumption, performance and cost than any alternative. Talking about Samsung’s move to FDSOI, he said “at 28nm, FD-SOI gets them an unprecedented combination of performance and power consumption for a cost comparable to that of standard low-power 28nm technology, making 28FD an extremely attractive alternative to any flavor of bulk CMOS at this node.”

Phil Garrou continues his analysis of presentations from the recent SEMI 2.5/3D IC forum in Singapore. In his third blog post on the topic, he reviews Nanium’s presentation “Wafer Level Fan-Out as Fine-Pitch Interposer” which focused on the premise that FO-WLP technology, eWLB, has closed the gap caused by the delay in the introduction of Si or glass interposers as mainstream high volume commodity technology.

Vivek Bakshi blogs that it takes a large infrastructure to make EUVL a manufacturing technology. So many tool suppliers, large and small, want to know when EUVL will be inserted into fabs for production and how and how much it will be used. Their business depends on these answers and some, especially smaller suppliers, are getting cold feet as delays in EUVL readiness continue. The answers to these questions mostly depend on knowing what we can expect from sources in the short- and near term, but there are many additional questions one must ask as well.

Karen Lightman of the MEMS Industry Group blogs about recent events in Japan, including the MIG Conference Japan. The focus of the conference was on navigating the challenges of the global MEMS supply chain. Several of the speakers gave their no-holds-barred view of these challenges, including the keynote from Sony Communications, Takeshi Ito, Chief Technology Officer, Head of Technology, Sony Mobile Communications.

The Week in Review: May 30, 2014

Friday, May 30th, 2014

Applied Materials, Inc. introduced the Endura Ventura PVD system that helps customers reduce the cost of fabricating smaller, lower power, high-performance integrated 3D chips.

STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, today introduced encapsulated Wafer Level Chip Scale Package, a packaging technology that raises the industry standard of durability for Wafer Level Chip Scale Packaging (WLCSP).

The Semiconductor Industry Association announced that global semiconductor industry leaders reached an agreement at the 18th annual meeting of the World Semiconductor Council (WSC) last week on a series of policy proposals to strengthen the industry through international cooperation.

The 60th annual IEEE International Electron Devices Meeting (IEDM) has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development.

SEMI announced that SEMICON West 2014 will feature Bob Metcalfe, professor at the University of Texas at Austin, as the Silicon Innovation Forum’s keynote speaker.

Next Page »