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Mentor Graphics U2U Meeting April 26 in Santa Clara

Monday, April 11th, 2016

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Mentor Graphics’ User2User meeting will be held in Santa Clara on April 26, 2016. The meeting is a highly interactive, in-depth technical conference focused on real world experiences using Mentor tools to design leading-edge products.

Admission and parking for User2User is free and includes all technical sessions, lunch and a networking reception at the end of the day. Interested parties can register on-line in advance.

Wally Rhines, Chairman and CEO of Mentor Graphics, will kick things off at 9:00am with a keynote talk on “Merger Mania.“ Wally notes that in 2015, the transaction value of semiconductor mergers was at an all-time historic high.  What is much more remarkable is that the average size of the merging companies is five times as large as in the past five years, he said. This major change in the structure of the semiconductor industry suggests that there will be changes that affect everything from how we define and design products to how efficiently we develop and manufacture them. Dr. Rhines will examine the data and provide conclusions and predictions.

He will be followed by another keynote talk at 10:00 by Zach Shelby, VP of Marketing for the Internet of Things at ARM. Zach was co-founder of Sensinode, where he was CEO, CTO and Chief Nerd for the ground-breaking company before its acquisition by ARM. Before starting Sensinode, Zach led wireless networking research at the Centre for Wireless Communications and at the Technical Research Center of Finland.

After user sessions and lunch, a panel will convene at 1:00pm to address the topic “Ripple or Tidal Wave: What’s driving the next wave of innovation and semiconductor growth?” Technology innovation was once fueled by the personal computer, communications, and mobile devices. Large capital investment and startup funding was rewarded with market growth and increased silicon shipments. Things are certainly consolidating, perhaps slowing down in the semiconductor market, so what’s going to drive the next wave of growth?  What types of designs will be staffed and funded? Is it IoT?  Wearables?  Automotive?  Experts will address these and other questions and examine what is driving growth and what innovation is yet to come.

Attendees can pick from nine technical tracks focused on AMS Verification, Calibre I and II, Emulation, Functional Verification, High Speed, IC Digital Implementation, PCB Flow, and Silicon Test & Yield Solutions. You’ll hear cases studies directly from users and also updates from Mentor Graphics experts.

These user sessions will be held at 11:10-12:00am, 2:00-2:50pm and 3:10-5:00pm.

A few of the highlights:

  • Oracle’s use of advanced fill techniques for improving manufacturing yield
  • How Xilinx built a custom ESD verification methodology on the Calibre platform
  • Qualcomm used emulation for better RTL design exploration for power, leading to more accurate power analysis and sign-off at the gate level
  • Micron’s experience with emulation, a full environment for debug of SSD controller designs, plus future plans for emulation
  • Microsoft use of portable stimulus to increase productivity, automate the creation of high-quality stimulus, and increase design quality
  • Formal verification at MicroSemi to create a rigorous, pre-code check-in review process that prevents bugs from infecting the master RTL
  • A methodology for modeling, simulation of highly integrated multi-die package designs at SanDisk
  • How Samsung and nVidia use new Automatic RTL Floorplanning capabilities on their advanced SoC designs
  • Structure test at AMD: traditional ATPG and Cell-Aware ATPG flows, as well as verification flows and enhancements

Other users presenting include experts from Towerjazz, Broadcom, GLOBALFOUNDRIES, Silicon Creations, MaxLinear, Silicon Labs, Marvell, HiSilicon, Qualcomm, Soft Machines, Agilent, Samtec, Honewell, ST Microelectronics, SHLC, ViaSat, Optimum, NXP, ON Semiconductor and MCD.

The day winds up with a closing session and networking reception from 5:00-6:00pm.

Registration is from 8:00-9:00am in the morning.

AMD Net Loss Widens in 2015 on Lower Revenue

Wednesday, January 20th, 2016

By Jeff Dorsch, Contributing Editor

Advanced Micro Devices on Tuesday reported a net loss of $660 million on revenue of $3.99 billion for 2015, compared with a net loss of $403 million on revenue of $5.51 billion in 2014.

In the fourth quarter, the fabless semiconductor company posted a net loss of $102 million on revenue of $958 million. A year ago, AMD had a net loss of $364 million on revenue of $1.24 billion.

“AMD closed 2015 with solid execution fueled by the second straight quarter of double-digit percentage revenue growth in our Computing and Graphics segment and record annual semi-custom unit shipments,” AMD President and Chief Executive Officer Lisa Su said in a statement. She added, “While 2015 was challenging from a financial perspective, key R&D investments and a sharpened focus on innovation position us well to deliver great products, improved financial results and share gains in 2016.”

The IC design company’s Computing and Graphics segment had Q4 revenue of $470 million, down 29 percent from a year earlier while growing 11 percent from the third quarter, largely due to higher sales of notebook processors. AMD’s Enterprise, Embedded and Semi-Custom segment posted revenue of $488 million in Q4, down 15 percent from a year ago due to lower game-console royalties and decreased sales in embedded and server chips.  Q4 revenue in that segment fell 23 percent from Q3 owing to seasonally lower sales of semi-custom system-on-a-chip devices.

AMD forecast revenue in the first quarter of this year will be down 14 percent from Q4, to about $824 million.

Matthew Ramsay, an analyst for Canaccord Genuity, said of AMD’s financial results, “Overall, we believe AMD’s diversification strategy continues to show gradual progress and a refreshed roadmap could position the company for more defensible long-term sales beginning 2H/16 as the roadmap moves to FinFET, crossing a significant competitive hurdle for the company. While Q4/15 results marked the second consecutive quarter of sequential growth for the C&S business where the roadmap is now more competitive, Q1/16 guidance was disappointing and management’s commentary regarding the macro environment was less than encouraging given a recent decline in channel and OEM forecasts in China. Looking forward to 2016, we anticipate stronger GPU sales as Polaris GPUs launch midyear, solid unit growth of console sales largely offset by ASP declines, and new semi-custom wins to contribute to 2H/16 growth, leaving GPU or semi-custom sales catalyzed by virtual reality as upside to our estimates. We are starting to see the righting of the ship at AMD, but remain on the sidelines for now given the decidedly uncertain macro environment.”

Conference Features “The Year of Stacked Memory” in 2015

Thursday, December 17th, 2015

By Jeff Dorsch, Contributing Editor

The theme of this year’s 3D Architectures for Semiconductor Integration and Packading (3D ASIP) conference is “The Year of Stacked Memory,” noting how memory die stacked in one package are becoming more commonplace in 2015.

Put on by RTI International, the 3D ASIP conference is in its 12th year. Attendees and presenters are generally people involved in chip packaging, from academia and industry.

One presentation on Wednesday (December 16) was by Teruo Hirayama of Sony, which has a long history of developing CMOS image sensors, dating back to 1998 with the graphics synthesizer for the PlayStation 2 video-game console, employing embedded DRAMs.

Embedded DRAMs present a number of manufacturing challenges, such as requiring four photomasks at the time, compared with three masks for commodity DRAMs and two or so masks for “pure logic” chips, Hirayama noted.

To address the issue, Sony turned to “chip-on-chip” technology, combining the merits of system-on-a-chip devices and system-in-package technology, according to Hirayama. The chipmaker later resorted to stacked CMOS image sensors, which offer a cost advantage over conventional CMOS image sensors.

During fiscal 2014, stacked CMOS image sensors accounted for 64 percent of Sony’s CMOS image sensor shipments, with back-illuminated image sensors representing 31 percent and front-illuminated image sensors 5 percent, Hirayama reported.

For future directions in stacked image sensors, Hirayama pointed to connecting pixels to analog-to-digital converters, with a device that has memory, a microelectromechanical system device, and a radio-frequency chip on the bottom layer, topped with a logic device, the ADC, and pixels, in that order.

The conference also heard Wednesday from Bryan Black of Advanced Micro Devices, a senior AMD fellow who spearheaded development of the company’s Fiji graphics processing unit.

The project started in 2007 and took 8.5 years to complete, Black said. “The industry needed a new memory system,” he commented. “We ended up with a die-stacking solution.”

Virtual prototyping was employed along the way, according to Black.

With a silicon interposer measuring 1,011 square millimeters and an ASIC coming in at 592 square millimeters, with four high-bandwidth memories, the Fiji GPU module is a big device. “We realized the part was going to be much bigger than we expected,” Black recalled. “Then we realized this thing would be huge.”

Wrapping up on Wednesday, the conference also heard presentations by three suppliers of semiconductor production equipment – EV GroupSPTS Technologies, and Rudolph Technologies.

3DIC Technology Drivers and Roadmaps

Monday, June 22nd, 2015

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By Ed Korczynski, Sr. Technical Editor

After 15 years of targeted R&D, through-silicon via (TSV) formation technology has been established for various applications. Figure 1 shows that there are now detailed roadmaps for different types of 3-dimensional (3D) ICs well established in industry—first-order segmentation based on the wiring-level/partitioning—with all of the unit-processes and integration needed for reliable functionality shown. Using block-to-block integration with 5 micron lines at leading international IC foundries such as GlobalFoundries, systems stacking logic and memory such as the Hybrid Memory Cube (HMC) are now in production.

Fig. 1: Today’s 3D technology landscape segmented by wiring-level, showing cross-sections of typical 2-tier circuit stacks, and indicating planned reductions in contact pitches. (Source: imec)

“There are interposers for high-end complex SOC design with good yield,” informed Eric Beyne, Scientific Director Advanced Packaging & Interconnect for imec in an exclusive interview with Solid State Technology. ““For a systems company, once you’ve made the decision to go 3D there’s no way back,” said Beyne. “If you need high-bandwidth memory, for example, then you’re committed to some sort of 3D. The process is happening today.” Beyne is scheduled to talk about 3D technology driven by 3D application requirements in the imec Technology Forum to be held July 13 in San Francisco.

Adaptation of TSV for stacking of components into a complete functional system is key to high-volume demand. Phil Garrou, packaging technologist and SemiMD blogger, reported from the recent ConFab that Hynix is readying a second generation of high-bandwidth memory (HBM 2) for use in high performance computing (HPC) such as graphics, with products already announced like Pascal from Nvidia and Greenland from AMD.

For a normalized 1 cm2 of silicon area, wide-IO memory needs 1600 signal pins (not counting additional power and ground pins) so several thousand TSV are needed for high-performance stacked DRAM today, while in more advanced memory architectures it could go up by another factor of 10. For wide-IO HVM-2 (or Wide-IO2) the silicon consumed by IO circuitry is maybe 6 cm2 today, such that a 3D stack with shorter vertical connections would eliminate many of the drivers on the chip and would allow scaling of the micro-bumps to perhaps save a total of 4 cm2 in silicon area. 3D stacks provide such trade-offs between design and performance, so the best results are predicted for 3DICs where the partitioning can be re-done at the gate or transistor level. For example, a modern 8-core microprocessor could have over 50% of the silicon area consumed by L3-cache-memory and IO circuitry, and moving from 2D to 3D would reduce total wire-lengths and interconnect power consumptions by >50%.

There are inherent thresholds based on the High:Width ratio (H:W) that determine costs and challenges in process integration of TSV:

-    10:1 ratio is the limit for the use of relatively inexpensive physical vapor deposition (PVD) for the Cu barrier/seed (B/S),

-    20:1 ratio is the limit for the use of atomic-layer deposition (ALD) for B/S and electroless deposition (ELD) for Cu fill with 1.5 x 30 micron vias on the roadmap for the far future,

-    30:1 ratio and greater is unproven as manufacturable, though novel deposition technologies continue to be explored.

TSV Processing Results

The researchers at imec have evaluated different ways of connecting TSV to underlying silicon, and have determined that direct connections to micro-bumps are inherently superior to use of any re-distribution layer (RDL) metal. Consequently, there is renewed effort on scaling of micro-bump pitches to be able to match up with TSV. The standard minimum micro-bump pitch today of 40 micron has been shrunk to 20, and imec is now working on 10 micron with plans to go to 5 micron. While it may not help with TSV connections, an RDL layer may still be needed in the final stack and the Cu metal over-burden from TSV filling has been shown by imec to be sufficiently reproducible to be used as the RDL metal. The silicon surface area covered by TSV today is a few percents not 10s of percents, since the wiring level is global or semi-global.

Regarding the trade-offs between die-to-wafer (D2W) and wafer-to-wafer (W2W) stacking, D2W seems advantageous for most near-term solutions because of easier design and superior yield. D2W design is easier because the top die can be arbitrarily smaller silicon, instead of the identically sized chips needed in W2W stacks. Assuming the same defectivity levels in stacking, D2W yield will almost always be superior to W2W because of the ability to use strictly known-good-die. Still, there are high-density integration concepts out on the horizon that call for W2W stacking. Monolithic 3D (M3D) integration using re-grown active silicon instead of TSV may still be used in the future, but design and yield issues will be at least comparable to those of W2W stacking.

Beyne mentioned that during the recent ECTC 2015, EV Group showed impressive 250nm overlay accuracy on 450mm wafers, proving that W2W alignment at the next wafer size will be sufficient for 3D stacking. Beyne is also excited by the fact the at this year’s ECTC there was, “strong interest in thermo-compression bonding, with 18 papers from leading companies. It’s something that we’ve been working on for many years for die-to-wafer stacking, while people had mistakenly thought that it might be too slow or too expensive.”

Thermal issues for high-performance circuitry remain a potential issue for 3D stacking, particularly when working with finFETs. In 2D transistors the excellent thermal conductivity of the underlying silicon crystal acts like a built-in heat-sink to diffuse heat away from active regions. However, when 3D finFETs protrude from the silicon surface the main path for thermal dissipation is through the metal lines of the local interconnect stack, and so finFETs in general and stacks of finFETs in particular tend to induce more electro-migration (EM) failures in copper interconnects compared to 2D devices built on bulk silicon.

3D Designs and Cost Modeling

At a recent North California Chapter of the American Vacuum Society (NCCAVS) PAG-CMPUG-TFUG Joint Users Group Meeting discussing 3D chip technology held at Semi Global Headquarters in San Jose, Jun-Ho Choy of Mentor Graphics Corp. presented on “Electromigration Simulation Flow For Chip-Scale Parametric Failure Analysis.” Figure 2 shows the results from use of a physics-based model for temperature- and residual-stress-aware void nucleation and growth. Mentor has identified new failure mechanisms in TSV that are based on coefficient of thermal expansion (CTE) mismatch stresses. Large stresses can develop in lines near TSV during subsequent thermal processing, and the stress levels are layout dependent. In the worst cases the combined total stress can exceed the critical level required for void nucleation before any electrical stressing is applied. During electrical stress, EM voids were observed to initially nucleate under the TSV centers at the landing-pad interfaces even though these are the locations of minimal current-crowding, which requires proper modeling of CTE-mismatch induced stresses to explain.

Fig. 2: Calibration of an Electronic Design Automation (EDA) tool allows for accurate prediction of transistor performance depending on distance from a TSV. (Source: Mentor Graphics)

Planned for July 16, 2015 at SEMICON West in San Francisco, a presentation on “3DIC Technology Past, Present and Future” will be part of one of the side Semiconductor Technology Sessions (STS). Ramakanth Alapati, Director of Packaging Strategy and Marketing, GLOBALFOUNDRIES, will discuss the underlying economic, supply chain and technology factors that will drive productization of 3DIC technology as we know it today. Key to understanding the dynamic of technology adaptation is using performance/$ as a metric.

Blog review April 14, 2014

Monday, April 14th, 2014

The increased performance and the rapid shift from traditional handsets to consumer computing device post a number of manufacturing and supply chain challenges for fabless chip makers. Dr. Roawen Chen of Qualcomm says the scale of the challenges also creates an “extreme stress” for the existing foundry/fabless model to defend its excellence in this dynamic landscape. In a keynote talk at The ConFab, titled “what’s on our mind?” Dr. Chen will deliberate on a number of headwinds and opportunities.

Jean-Eric Michallet, Hughes Metras and Perrine Batude of CEA-Leti describe how the research group has already demonstrated the successful stacking of Si CMOS on Si CMOS, achieving benchmark performance for both layers of transistors. The main process challenge is to develop a sufficiently low-temperature process for the top transistor layer to limit the impact on the lower transistor layers.

Phil Garrou continues his analysis of the IMAPS Device Packaging Conference with a review of the keynote by AMD’s Bryan Black, titled“Die Stacking and High Bandwidth Memory.” Black stated that “…while die stacking is catching on in FPGAs, Power Devices, and MEMs, there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!” Garrou also reviews the newly announced STATSChipPAC FlexLine, which uses eWLB technology to dice and reconstitute incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size.

Karen Savala, president, SEMI Americas, blogs about the sustainable manufacturing imperative, noting that sustainability is increasingly considered a differentiating factor in global competitiveness relative to the technologies and products being provided. In conjunction with SEMICON West and INTERSOLAR North America, SEMI is organizing a four-day Sustainable Manufacturing Forum to share information about the latest technologies, products, and management approaches that promote sustainable manufacturing.

The Week in Review: Dec. 20, 2013

Friday, December 20th, 2013

3DIC memory, and therefore all of 2.5/3D technology, took one step closer to full commercialization last week with the HBM joint development announcement from AMD and Hynix at the RTI 3D ASIP meeting in Burlingame, CA. Bryan Black, Sr Fellow and 3D program manager at AMD noted that while die stacking has caught on in FPGAs and image sensors “..there is nothing yet in mainstream computing CPUs, GPUs or APUs” but that “HBM (high bandwidth memory) will change this.”  Black continued,  “Getting 3D going will take a BOLD move and AMD is ready to make that move.” Black announced that AMD is co-developing HBM with SK Hynix which is currently sampling the HBM memory stacks and that AMD “…is ready to work with customers.”

ABI Research verified that Intel has a leading position in the mobile processor technology race; launching the first 22nm mobile application processor. The 22nm quad-core application processor (Intel Z3740D) was found in a Dell tablet that was recently launched for the Christmas season. “2013 saw a number of new processor launches with 32nm and 28nm technology (most from fabless companies) but Intel has used one of its core advantages [process technology] to pass them all,” Jim Mielke, VP of engineering at ABI Research, commented. “The 22nm process node used for the Z3740D is not just the smallest geometry in a mobile device today; it also introduces a new transistor. The core transistor structure used in the 22nm Z3740D is quite different than structures used in previous generations. The core transistor found in the device ABI Research analyzed has a gate that surrounds source/drain diffusion fins on three sides giving it the name tri-gate or 3D transistor.

North America-based manufacturers of semiconductor equipment posted $1.24 billion in orders worldwide in November 2013 (three-month average basis) and a book-to-bill ratio of 1.11, according to the November EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.11 means that $111 worth of orders were received for every $100 of product billed for the month. “The continuing rise in equipment bookings clearly points to year-end order activity that is substantially stronger compared to one year ago,” said Denny McGuirk, president and CEO of SEMI.  ”This trend supports the current outlook showing a rebound in equipment spending for 2014.”

Soitec and CEA have renewed their partnership for the next five years. This new contract aims to support Soitec’s strategy for the electronics, solar energy and lighting markets. It will focus on engineered substrates and materials offering higher performances and energy savings at a competitive cost. As the new partnership is putting in place a powerful R&D ecosystem, time from research to product will be considerably reduced. Thanks to the strengths of CEA-Leti in electronic materials, multi-domain research and its pre-industrialization infrastructure, competitive R&D sample prototyping will be enabled thru a common platform, reducing time to market and R&D costs for Soitec and its customers.

Micron Technology, Inc. announced its collaboration with Broadcom Corporation to develop the industry’s first solution designed for customers challenged by an intrinsic DDR3 timing parameter called tFAW, or four activate window.

Solid State Watch: Dec. 13-19, 2013

Friday, December 20th, 2013
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Blog review December 16, 2013

Monday, December 16th, 2013

Randhir Thakur of Applied Materials wishes the transistor a happy 66th birthday, noting that the transistor is truly one of the most amazing technological innovations of all time! He says it’s estimated that more than 1200 quintillion transistors will be manufactured in 2015, making the transistor the most ubiquitous man-made device on the planet.

Phil Garrou writes that 3DIC memory, and therefore all of 2.5/3D technology, took one step closer to full commercialization last week with the High Bandwidth Memory HBM joint development announcement from AMD and Hynix at the RTI 3D ASIP meeting in Burlingame CA.

Zhihong Liu, Executive Chairman of ProPlus Design Solutions is celebrating 20 years of BSIM3v3 SPICE models. He notes that with continuous geometry down-scaling in CMOS devices, compact models became more complicated as they needed to cover more physical effects, such as gate tunneling current, shallow trench isolation (STI) stress and well proximity effect (WPE).

Applied Materials and Tokyo Electron held a media roundtable in Japan to discuss the merger of equals announced on September 24, 2013. Tetsuro Higashi, Chairman, President and CEO of Tokyo Electron, who will become Chairman of the new company, and Mike Splinter, Executive Chairman of Applied Materials, who will serve as Vice-Chairman, addressed the audience of more than 20 members of the Japanese media. Kevin Winston blogs about the event.

Pete Singer is freshly back from the International Electron Devices Meeting (IEDM). “A dream for the device engineer could be a nightmare for a process integration engineer,” said Frederic Boeuf of ST Microelectronics in the opening talk. That seemed to be echoed throughout the conference, where the potential of new devices such as tunnel FETs or materials such as graphene were always tempered with a dose of reality that materials had to be deposited, patterned, annealed to create devices, and those devices had to be connected.

Research Alert: Nov. 26, 2013

Tuesday, November 26th, 2013

What can happen when graphene meets a semiconductor

For all the promise of graphene as a material for next-generation electronics and quantum computing, scientists still don’t know enough about this high-performance conductor to effectively control an electric current. Graphene, a one-atom-thick layer of carbon, conducts electricity so efficiently that the electrons are difficult to control. And control will be necessary before this wonder material can be used to make nanoscale transistors or other devices. A new study by a research group at the University of Wisconsin-Milwaukee (UWM) will help.

The researchers demonstrated that when electrons are rerouted at the interface of the graphene and its semiconducting substrate, they encounter what’s known as a Schottky barrier. If it’s deep enough, electrons don’t pass, unless rectified by applying an electric field – a promising mechanism for turning a graphene-based device on and off.

The group also found, however, another feature of graphene that affects the height of the barrier. Intrinsic ripples form on graphene when it is placed on top of a semiconductor.

Nanotubes can solder themselves

University of Illinois researchers have developed a way to heal gaps in wires too small for even the world’s tiniest soldering iron. Led by electrical and computer engineering professor Joseph Lyding and graduate student Jae Won Do, the Illinois team published its results in the journal Nano Letters.

Carbon nanotubes themselves are high-quality conductors, but creating single tubes suitable to serve as transistors is very difficult. Arrays of nanotubes are much easier to make, but the current has to hop through junctions from one nanotube to the next, slowing it down. In standard electrical wires, such junctions would be soldered, but how could the gaps be bridged on such a small scale?

“It occurred to me that these nanotube junctions will get hot when you pass current through them,” said Lyding, “kind of like faulty wiring in a home can create hot spots. In our case, we use these hot spots to trigger a local chemical reaction that deposits metal that nano-solders the junctions.”

The nano-soldering process is simple and self-regulating. A carbon nanotube array is placed in a chamber pumped full of the metal-containing gas molecules. When a current passes through the transistor, the junctions heat because of resistance as electrons flow from one nanotube to the next. The molecules react to the heat, depositing the metal at the hot spots and effectively “soldering” the junctions. Then the resistance drops, as well as the temperature, so the reaction stops.

U.S. government awards AMD contract to research interconnect architectures

AMD today announced that it was selected for an award of $3.1 million for a research project associated with the U.S. Department of Energy (DOE) Extreme-Scale Computing Research and Development Program, known as “DesignForward.” The DOE award is an expansion of work started as part of another two-year award AMD received in 2012 called “FastForward.” The FastForward award aims to accelerate the research and development of processor and memory technologies needed to support extreme-scale computing. The DesignForward award supports the research of the interconnect architectures and technologies needed to support the data transfer capabilities in extreme-scale computing environments.

DesignForward is a jointly funded collaboration between the DOE Office of Science and the U.S. National Nuclear Security Administration (NNSA) to accelerate the research and development of critical technologies needed for extreme-scale computing, on the path toward Exascale computing. Exascale supercomputers are expected to be capable of performing computation hundreds of times faster than today’s fastest computers, with only slightly higher power utilization. Exascale supercomputers are designed to break through the current limitations of today’s supercomputers by dramatically reducing the length of run time required to perform calculations and improving the capability to perform detailed simulations, modeling, and analyses of complex systems.

In order to achieve this dramatic increase in computing capability while maintaining low power consumption, leaps in research and development need to be advanced in all aspects of computing.