Mentor Graphics Corporation (NASDAQ: MENT) today announced further enhancements and optimizations to the Calibre® platform and Analog FastSPICE™ (AFS) platform by completing TSMC 10nm FinFET V1.0 certification. In addition, the Calibre and Analog FastSPICE platforms are ready for early design starts and IP design on TSMC’s 7nm FinFET process based on the most current Design Rule Manual (DRM) and SPICE model.
To help mutual customers prepare their designs for advanced manufacturing processes, Mentor has made improvements for 10nm physical verification, accelerating the runtime of the Calibre nmDRC™ sign-off tool compared to the tool’s runtime when it was initially certified for required 10nm accuracy last year. New device parameters of the 10nm process are supported in the Calibre nmLVS™ tool for more accurate SPICE models and self-heating simulation. Mentor has also enhanced the parasitic accuracy in the Calibre xACT™ solution, and is actively improving layout parasitic extraction flow to meet 10nm requirements.
The Calibre platform also helps designers improve design reliability and manufacturability. The TSMC reliability offering leverages the Calibre PERC™ reliability verification solution, now with enhanced techniques for 10nm resistance and current density checking. For design for manufacturing (DFM), Mentor added color-aware fill and more sophisticated alignment and spacing rules to the SmartFill feature of the Calibre YieldEnhancer tool. Mentor also optimized the Calibre DesignREV™ chip finishing tool, the Calibre RVE™ results viewer, and the Calibre RealTime interface to give designers easier integration and debugging capabilities for multi-patterning, layout vs. schematic (LVS) comparison, and electrical rule checking (ERC) and reliability verification.
Mentor and TSMC are now collaborating on bringing the Calibre platform’s broad capabilities to the 7nm FinFET process. The Calibre nmDRC and Calibre nmLVS tools are already certified for customers’ early design starts. TSMC and Mentor are expanding use of the SmartFill functionality and Calibre multi-patterning capabilities to support the technology requirements of 7nm.
For fast, accurate circuit simulation, TSMC certified the AFS platform, including the AFS Mega circuit simulator, for 10nm V1.0. The AFS platform is also certified for the latest version of the 7nm DRM and SPICE for early design starts.
The Mentor place-and-route platform—including the Olympus-SoC™ system—has been enhanced to support advanced design rules at 10nm, and Mentor is optimizing its correlation with sign-off extraction and static timing analysis tools. This collaboration has also been extended to 7nm.
“We continue to collaborate with Mentor Graphics to provide design solutions and services that will help our mutual customers become successful with their 7nm designs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Working together, we are also enabling the full production release of our 10nm technology design support.”
“To get the world’s most advanced processes into the hands of today’s leading SoC designers requires intense collaboration between the foundry and the EDA supplier,” said Joe Sawicki, vice president and general manager of Mentor Graphics Design-to-Silicon Division. “We’re honored that TSMC continues to leverage the proven quality, performance and breadth of Mentor platforms in its ecosystem strategy for the future.”