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Edge Placement Error Control in Multi-Patterning

Thursday, March 2nd, 2017

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By Ed Korczynski, Sr. Technical Editor

SPIE Advanced Lithography remains the technical conference where the leading edge of minimum resolution patterning is explored, even though photolithography is now only part of the story. Leading OEMs continue to impress the industry with more productive ArFi steppers, but the photoresist suppliers and the purveyors of vacuum deposition and etch tools now provide most of the new value-add. Tri-layer-resist (TLR) stacks, specialty hard-masks and anti-reflective coatings (ARC), and complex thin-film depositions and etches all combine to create application-specific lithography solutions tuned to each critical mask.

Multi-patterning using complementary lithography—using argon-fluoride immersion (ArFi) steppers to pattern 1D line arrays plus extreme ultra-violet (EUV) tools to do line cuts—is under development at all leading edge fabs today. Figure 1 shows that edge placement error (EPE) in lines, cut layers, and vias/contacts between two orthogonal patterned layers can result in shorts and opens. Consequently, EPE control is critical for yield within any multi-patterning process flow, including litho-etch-litho-etch (LELE), self-aligned double-patterning (SADP) and self-aligned quadruple-patterning (SAQP).

Fig.1: Plan view schematic of 10nm half-pitch vertical lines overlaid with lower horizontal lines, showing the potential for edge-placement error (EPE). (Source: Y. Borodovsky, SPIE)

Happening the day before the official start of SPIE-AL, Nikon’s LithoVision event featured a talk by Intel Fellow and director of lithography hardware solutions Mark Phillips on the big picture of how the industry may continue to pattern smaller IC device features. Regarding the timing of Intel’s planned use of EUV litho technology, Phillips re-iterated that, “It’s highly desirable for the 7nm node, but we’ll only use it when it’s ready. However, EUVL will remain expensive even at full productivity, so 193i and multi-patterning will continue to be used. In particular we’ll need continued improvement in the 193i tools to meet overlay.”

Yuichi Shibazaki— Nikon Fellow and the main architect of the current generation of Nikon steppers—explained that the current generation of 193i steppers, featuring throughputs of >200 wafers per hour, have already been optimized to the point of diminishing returns. “In order to improve a small amount of performance it requires a lot of expense. So just improving tool performance may not decrease chip costs.” Nikon’s latest productivity offering is a converted alignment station as a stand-alone tool, intended to measure every product wafer before lithography to allow for feed-forward tuning of any stepper; cost and cost-of-ownership may be disclosed after the first beta-site tool reaches a customer by the end of this year.

“The 193 immersion technology continues to make steady progress, but there are not as many new game-changing developments,” confided Michael Lercel, Director of Strategic Marketing for ASML in an exclusive interview with SemiMD. “A major theme of several SPIE papers is on EPE, which traditionally we looked at as dependent upon CD and overlay. Now we’re looking at EPE in patterning more holistically, with need to control the complexity with different error-variables. The more information we can get the more we can control.”

At LithoVision this year, John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—discussed the challenges of controlling variability in multi-layer patterning. “A key challenge is predicting and then mitigating total EPE control,” reminded Sturtevant. “We’ve always paid attention to it, but the budgets that are available today are smaller than ever. Edge-placement is very important ” At the leading edge, there are multiple steps within the basic litho flow that induce proximity/local-neighbor effects which must be accounted for in EDA:  mask making, photoresist exposure, post-exposure bake (PEB), pattern development, and CD-SEM inspection (wherein there is non-zero resist shrinkage).

Due to the inherent physics of EUV lithography, as well as the atomic-scale non-uniformities in the reflective mirrors focusing onto the wafer, EUV exposure tools show significant variation in exposure uniformities. “For any given slit position there can be significant differences between tools. In practice we have used a single model of OPC for all slit locations in all scanners in the fab, and that paradigm may have to change,” said Sturtevant. “It’s possible that because the variation across the scanner is as much as the variation across the slit, it could mean we’ll need scanner-specific cross-slit computational lithography.” More than 3nm variation has been seen across 4 EUVL steppers, and the possible need for tool-specific optical proximity correction (OPC) and source-mask optimization (SMO) would be horrible for managing masks in HVM.

Thin Films Extend Patterning Resolution

Applied Materials has led the industry in thin-film depositions and etches for decades, and the company’s production proven processing platforms are being used more and more to extend the resolution of lithography. For SADP and SAQP MP, there are tunable unit-processes established for sidewall-spacer depositions, and chemical downstream etching chambers for mandrel pull with extreme material selectivity. CVD of dielectric and metallic hard-masks when combined with highly anisotropic plasma etching allows for device-specific and mask-specific pattern transfers that can reduce the line width/edge roughness (LWR/LER) originally present in the photoresist. Figure 2 from the SPIE-AL presentation “Impact of Materials Engineering on Edge Placement Error” by Regina Freed, Ying Zhang, and Uday Mitra of Applied Materials, shows LER reduction from 3.4 to 1.3 nm is possible after etch. The company’s Sym3 chamber features very high gas conductance to prevent etch byproducts from dissociation and re-deposition on resist sidewalls.

Fig.2: 3D schematics (top) and plan view SEM images (bottom) showing that control of plasma parameters can tune the byproducts of etch processes to significantly reduce the line-width roughness (LWR) of minimally scaled lines. (Source: Applied Materials)

TEL’s new SAQP spacer-on-spacer process builds on the work shown last year, using oxide as first spacer and TiO2 as second spacer. Now TEL is exploring silicon as the mandrel, then silicon-nitride as the first spacer, and titanium-oxide as second spacer. This new flow can be tuned so that all-dry etch in a single plasma etch chamber can be used for the final mandrel pull and pattern transfer steps.

Coventor’s 3D modeling software allows companies to do process integration experiments in virtual space, allowing for estimation of yield-losses in pattern transfer due to variations in side-wall profiles and LER. A simulation of 9 SRAM cells with 54 transistors shows that photoresist sidewall taper angle determines both the size and the variability of the final fins. The final capacitance of low-k dielectric in dual-damascene copper metal interconnects can be simulated as a function of the initial photoresist profile in a SAQP flow.

—E.K.

Air-Gaps for FinFETs Shown at IEDM

Friday, October 28th, 2016

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By Ed Korczynski, Sr. Technical Editor

Researchers from IBM and Globalfoundries will report on the first use of “air-gaps” as part of the dielectric insulation around active gates of “10nm-node” finFETs at the upcoming International Electron Devices Meeting (IEDM) of the IEEE (ieee-iedm.org). Happening in San Francisco in early December, IEDM 2016 will again provide a forum for the world’s leading R&D teams to show off their latest-greatest devices, including 7nm-node finFETs by IBM/Globalfoundries/Samsung and by TSMC. Air-gaps reduce the dielectric capacitance that slows down ICs, so their integration into transistor structures leads to faster logic chips.

History of Airgaps – ILD and IPD

As this editor recently covered at SemiMD, in 1998, Ben Shieh—then a researcher at Stanford University and now a foundry interface for Apple Corp.—first published (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) on the use of controlled pitch design combined with CVD dielectrics to form “pinched-off keyholes” in cross-sections of inter-layer dielectrics (ILD).

In 2007, IBM researchers showed a way to use sacrificial dielectric layers as part of a subtractive process that allows air-gaps to be integrated into any existing dielectric structure. In an interview with this editor at that time, IBM Fellow Dan Edelstein explained, “we use lithography to etch a narrow channel down so it will cap off, then deliberated damage the dielectric and etch so it looks like a balloon. We get a big gap with a drop in capacitance and then a small slot that gets pinched off.

Intel presented on their integration of air-gaps into on-chip interconnects at IITC in 2010 but delayed use until the company’s 14nm-node reached production in 2014. 2D-NAND fabs have been using air-gaps as part of the inter-poly dielectric (IPD) for many years, so there is precedent for integration near the gate-stack.

Airgaps for finFETs

Now researchers from IBM and Globalfoundries will report in (IEDM Paper #17.1, “Air Spacer for 10nm FinFET CMOS and Beyond,” K. Cheng et al) on the first air-gaps used at the transistor level in logic. Figure 1 shows that for these “10nm-node” finFETs the dielectric spacing—including the air-gap and both sides of the dielectric liner—is about 10 nm. The liner needs to be ~2nm thin so that ~1nm of ultra-low-k sacrificial dielectric remains on either side of the ~5nm air-gap.

Fig.1: Schematic of partial air-gaps only above fin tops using dielectric liners to protect gate stacks during air-gap formation for 10nm finFET CMOS and beyond. (source: IEDM 2016, Paper#17.1, Fig.12)

These air-gaps reduced capacitance at the transistor level by as much as 25%, and in a ring oscillator test circuit by as much as 15%. The researchers say a partial integration scheme—where the air-gaps are formed only above the tops of fin— minimizes damage to the FinFET, as does the high-selectivity etching process used to fabricate them.

Figure 2 shows a cross-section transmission electron micrograph (TEM) of what can go wrong with etch-back air-gaps when all of the processes are not properly controlled. Because there are inherent process:design interactions needed to form repeatable air-gaps of desired shapes, this integration scheme should be extendable “beyond” the “10-nm node” to finFETs formed at tighter pitches. However, it seems likely that “5nm-node” logic FETs will use arrays of horizontal silicon nano-wires (NW), for which more complex air-gap integration schemes would seem to be needed.

Fig.2: TEM image of FinFET transistor damage—specifically, erosion of the fin and source-drain epitaxy—by improper etch-back of the air-gaps at 10nm dimensions. (source: IEDM 2016, Paper#17.1, Fig.10)

—E.K.

Mentor Graphics Enhances Support for TSMC 7nm Design Starts and 10nm Production

Thursday, March 17th, 2016

Mentor Graphics Corporation (NASDAQ: MENT) today announced further enhancements and optimizations to the Calibre® platform and Analog FastSPICE™ (AFS) platform by completing TSMC 10nm FinFET V1.0 certification. In addition, the Calibre and Analog FastSPICE platforms are ready for early design starts and IP design on TSMC’s 7nm FinFET process based on the most current Design Rule Manual (DRM) and SPICE model.

To help mutual customers prepare their designs for advanced manufacturing processes, Mentor has made improvements for 10nm physical verification, accelerating the runtime of the Calibre nmDRC™ sign-off tool compared to the tool’s runtime when it was initially certified for required 10nm accuracy last year. New device parameters of the 10nm process are supported in the Calibre nmLVS™ tool for more accurate SPICE models and self-heating simulation. Mentor has also enhanced the parasitic accuracy in the Calibre xACT™ solution, and is actively improving layout parasitic extraction flow to meet 10nm requirements.

The Calibre platform also helps designers improve design reliability and manufacturability. The TSMC reliability offering leverages the Calibre PERC™ reliability verification solution, now with enhanced techniques for 10nm resistance and current density checking. For design for manufacturing (DFM), Mentor added color-aware fill and more sophisticated alignment and spacing rules to the SmartFill feature of the Calibre YieldEnhancer tool. Mentor also optimized the Calibre DesignREV™ chip finishing tool, the Calibre RVE™ results viewer, and the Calibre RealTime interface to give designers easier integration and debugging capabilities for multi-patterning, layout vs. schematic (LVS) comparison, and electrical rule checking (ERC) and reliability verification.

Mentor and TSMC are now collaborating on bringing the Calibre platform’s broad capabilities to the 7nm FinFET process. The Calibre nmDRC and Calibre nmLVS tools are already certified for customers’ early design starts. TSMC and Mentor are expanding use of the SmartFill functionality and Calibre multi-patterning capabilities to support the technology requirements of 7nm.

For fast, accurate circuit simulation, TSMC certified the AFS platform, including the AFS Mega circuit simulator, for 10nm V1.0. The AFS platform is also certified for the latest version of the 7nm DRM and SPICE for early design starts.

The Mentor place-and-route platform—including the Olympus-SoC™ system—has been enhanced to support advanced design rules at 10nm, and Mentor is optimizing its correlation with sign-off extraction and static timing analysis tools. This collaboration has also been extended to 7nm.

“We continue to collaborate with Mentor Graphics to provide design solutions and services that will help our mutual customers become successful with their 7nm designs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Working together, we are also enabling the full production release of our 10nm technology design support.”

“To get the world’s most advanced processes into the hands of today’s leading SoC designers requires intense collaboration between the foundry and the EDA supplier,” said Joe Sawicki, vice president and general manager of Mentor Graphics Design-to-Silicon Division. “We’re honored that TSMC continues to leverage the proven quality, performance and breadth of Mentor platforms in its ecosystem strategy for the future.”

TSMC Readies 7nm Chip Ecosystem, Infrastructure for 2017

Wednesday, March 16th, 2016

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By Jeff Dorsch, Contributing Editor

Taiwan Semiconductor Manufacturing Company came to Silicon Valley on Tuesday for a day of presentations on its latest chip technology. The TSMC Technology Symposium for North America drew more than 1,000 attendees at the San Jose Convention Center.

The world’s largest silicon foundry led off the day with a pair of announcements: ARM Holdings and TSMC said they would collaborate on 7-nanometer FinFET process technology for ultra-low-power high-performance computing (HPC) system-on-a-chip devices, building on their previous experience with 16nm and 10nm FinFET process technology, while MediaTek and TSMC extended their partnership to develop Internet of Things and wearable electronics products, using the IC design house’s MT2523 chipset for fitness smartwatches, introduced in January and fabricated with TSMC’s 55nm ULP process.

TSMC’s work with ARM on the 16nm and 10nm nodes employed ARM’s Artisan foundation physical intellectual property, as will their 7nm efforts.

On Tuesday afternoon, the hundreds of attendees heard first from BJ Woo, TSMC’s vice president of business development, on the company’s advanced technology, including its moves toward supporting radio-frequency IC (RFIC) designs for smartphone chips and other areas of wireless communications.

“Cellular RF and WLAN are RF technology drivers,” she said. Looking toward 4G LTE Carrier Aggregation, TSMC began offering its 28HPC RF process to customers in late 2015 and will roll out the 28HPC+ RF process in the second quarter of this year, Woo added.

TSMC has won 75 percent of the business for RFIC applications, she asserted.

The foundry will start making 10nm FinFET chips for flagship smartphones and “phablets” this year, with 7nm FinFET devices for those products in 2017, according to Woo.

The business development executive also touted the company’s “mature 28-nanometer processes,” the 28HPC and 28HPC+, saying they are “rising in both volume and customer tape-outs.”

TSMC has been shipping automotive chips meeting industry standards since 2014, Woo noted, primarily for advanced driver assistance systems (ADAS) and infotainment electronics. The foundry is now working on vehicle control technology, employing microcontrollers.

The company’s 16FF+ process has been used in 50 customer tape-outs, Woo said. “Many have achieved first-silicon success,” she added. TSMC is putting its 16FFC process into volume production during this quarter.

“Automotive will be the [semiconductor] industry focus,” Woo predicted.

She also spoke about the company’s MD2 local interconnect technology, its 1D back-end-of-line process, and its spacer BEOL process.

Regarding 7nm chips, Woo said the company will offer two “tracks” of such chips, for high-performance computing and mobile applications. “Both will be available at the same time,” she said.

Most of the semiconductor production equipment being used for fabrication of 10nm chip will also be used for 7nm manufacturing, according to Woo. Those 7nm chips will be 10 to 15 percent faster than 10nm chips, while reducing power consumption by 35 to 40 percent, she said.

Risk production of 7nm chips will begin one year from now, in March of 2017, she said.

Suk Lee, senior director of TSMC’s Design Infrastructure Marketing Division, reported on development of electronic design automation (EDA) products for the 16nm node and beyond.

“Low-power solutions are ready,” he said of the foundry’s 16FFC process. IP is available to use with 16FFC for automotive, IoT, HPC, and mobile computing applications, he noted.

Lee reviewed what the company’s EDA partners – Mentor Graphics, Synopsys, Cadence Design Systems, ANSYS, and ATopTech – have available for 10nm chip design and verification.

Design and manufacturing of 7nm chips will involve cut-metal handling and multiple patterning, according to Lee. “We’ve used this technology on 16 nanometer and previous generations,” he said of cut-metal handling.

TSMC will support multiple SPICE simulators, having developed hybrid-format netlist support, Lee said. Pre-silicon design kits for 7nm chips will be available in the third quarter of 2016, he added.

The TSMC9000 Program for automotive/IoT products will be “up and running” in Q3 of this year, providing “automotive-grade qualification requirements in planning,” he said.

Lee also spoke about the foundry’s offerings in 3D chips, featuring “full integration of packaging and IC design” with TSMC’s InFO technology. The HBM2 CoWoS design kit will be out in the second quarter of 2016, he said. “We’re very excited about that,” Lee added.

George Liu, senior director of TSMC’s Sensor & Display Business Development, said, “The Internet of Things will drive the next semiconductor growth.” When it comes to the IoT and the Internet of Everything, “forecasts are all over the map,” he noted.

Taking diversification as his theme, Liu said TSMC’s specialty technology will help bridge the connection between the natural world and the computing cloud. First there is the “signal chain” of analog chips and sensors, leading to the “data chain” of connectivity, he said.

Liu reviewed a wide variety of relevant technologies, such as CMOS image sensors, microelectromechanical system (MEMS devices, embedded flash memories, biometrics, touch and display technology, and power management ICs.

At the all-day conference, which included an ecosystem exhibition by partner companies, TSMC emphasized its readiness to take on 28nm, 16nm, 10nm, and 7nm chip designs, along with the more mature process technologies. It’s game on for the foundry business.

EUV Resists and Stochastic Processes

Friday, March 4th, 2016

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By Ed Korczynski, Sr. Technical Editor

In an exclusive interview with Solid State Technology during SPIE-AL this year, imec Advanced Patterning Department Director Greg McIntyre said, “The big encouraging thing at the conference is the progress on EUV.” The event included a plenary presentation by TSMC Nanopatterning Technology Infrastructure Division Director and SPIE Fellow Anthony Yen on “EUV Lithography: From the Very Beginning to the Eve of Manufacturing.” TSMC is currently learning about EUVL using 10nm- and 7nm-node device test structures, with plans to deploy it for high volume manufacturing (HVM) of contact holes at the 5nm node. Intel researchers confirm that they plan to use EUVL in HVM for the 7nm node.

Recent improvements in EUV source technology— 80W source power had been shown by the end of 2014, 185W by the end of 2015, and 200W has now been shown by ASML—have been enabled by multiple laser pulses tuned to the best produce plasma from tin droplets. TSMC reports that 518 wafers per day were processed by their ASML EUV stepper, and the tool was available ~70% of the time. TSMC shows that a single EUVL process can create 46nm pitch lines/spaces using a complex 2D mask, as is needed for patterning the metal2 layer within multilevel on-chip interconnects.

To improve throughput in HVM, the resist sensitivity to the 13.54nm wavelength radiation of EUV needs to be improved, while the line-width roughness (LWR) specification must be held to low single-digit nm. With a 250W source and 25 mJ/cm2 resist sensitivity an EUV stepper should be able to process ~100 wafer-per-hour (wph), which should allow for affordable use when matched with other lithography technologies.

Researchers from Inpria—the company working on metal-oxide-based EUVL resists—looked at the absorption efficiencies of different resists, and found that the absorption of the metal oxide based resists was ≈ 4 to 5 times higher than that of the Chemically-Amplified Resist (CAR). The Figure shows that higher absorption allows for the use of proportionally thinner resist, which mitigates the issue of line collapse. Resist as thin as 18nm has been patterned over a 70nm thin Spin-On Carbon (SOC) layer without the need for another Bottom Anti-Reflective Coating (BARC). Inpria today can supply 26 mJ/cm2 resist that creates 4.6nm LWR over 140nm Depth of Focus (DoF).

To prevent pattern collapse, the thickness of resist is reduced proportionally to the minimum half-pitch (HP) of lines/spaces. (Source: JSR Micro)

JEIDEC researchers presented their summary of the trade-off between sensitivity and LWR for metal-oxide-based EUV resists:  ultra high sensitivity of 7 mJ/cm2 to pattern 17nm lines with 5.6nm LWR, or low sensitivity of 33 mJ/cm2 to pattern 23nm lines with 3.8nm LWR.

In a keynote presentation, Seong-Sue Kim of Samsung Electronics stated that, “Resist pattern defectivity remains the biggest issue. Metal-oxide resist development needs to be expedited.” The challenge is that defectivity at the nanometer-scale derives from “stochastics,” which means random processes that are not fully predictable.

Stochastics of Nanopatterning

Anna Lio, from Intel’s Portland Technology Development group, stated that the challenges of controlling resist stochastics, “could be the deal breaker.” Intel ran a 7-month test of vias made using EUVL, and found that via critical dimensions (CD), edge-placement-error (EPE), and chain resistances all showed good results compared to 193i. However, there are inherent control issues due to the random nature of phenomena involved in resist patterning:  incident “photons”, absorption, freed electrons, acid generation, acid quenching, protection groups, development processes, etc.

Stochastics for novel chemistries can only be controlled by understanding in detail the sources of variability. From first-principles, EUV resist reactions are not photon-chemistry, but are really radiation-chemistry with many different radiation paths and electrons which can be generated. If every via in an advanced logic IC must work then the failure rate must be on the order of 1 part-per-trillion (ppt), and stochastic variability from non-homogeneous chemistries must be eliminated.

Consider that for a CAR designed for 15mJ/cm2 sensitivity, there will be just:

145 photons/nm2 for 193, and

10 photons/nm2 for EUV.

To improve sensitivity and suppress failures from photon shot-noise, we need to increase resist absorption, and also re-consider chemical amplification mechanisms. “The requirements will be the same for any resist and any chemistry,” reminded Lio. “We need to evaluate all resists at the same exposure levels and at the same rules, and look at different features to show stochastics like in the tails of distributions. Resolution is important but stochastics will rule our world at the dimensions we’re dealing with.”

—E.K.

Optimism Reigns at SPIE Lithography Conference, Despite Challenges

Tuesday, February 23rd, 2016

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By Jeff Dorsch, Contributing Editor

Semiconductor manufacturing and design is growing increasingly complicated and just plain hard. Everyone knows that. The bad news is it’s only going to get worse.

Relax, there are many smart people gathered in San Jose, Calif., this week for the SPIE Advanced Lithography Symposium to discuss the challenges and figure out how to surmount them.

The changes required in lithography and related technologies to continue IC scaling promise to be painful and costly. Mitigating the pain and the cost is a common theme at the SPIE conference.

The annual SPIE Advanced Lithography conference is often dominated by discussions on the state of extreme-ultraviolet lithography (EUVL). In presentations on Sunday and Monday, the theme was generally the same as 2015 – EUV is making progress, yet it’s still not ready for high-volume semiconductor manufacturing.

Intel Fellow Mark Phillips said the technology has seen “two years of solid progress,” speaking Sunday at Nikon’s LithoVision 2016 event. He added, “There’s no change in Intel’s position: We’ll use EUV only when it’s ready.”

Anthony Yen of Taiwan Semiconductor Manufacturing covered the 30-year history of EUV development in his Monday morning presentation at the SPIE conference. Asked during the question-and-answer session following the presentation on when the world’s largest silicon foundry will use EUV, Yen stuck to the official company line of implementing EUV in production for the 7-nanometer process node, after some involvement at 10nm.

Seong-Sam Kim of Samsung Electronics also sees EUV realizing its long-aborning potential at 7nm, a node at which “argon fluoride multipatterning will hit the wall.” He touted the 80-watt power source Samsung has achieved with its NXE-3300 scanner from ASML Holding, saying it had maintained that level over more than eight months.

Intel’s Britt Turkot reported 200W source power “has been achieved recently,” and said the tin droplet generator in its ASML scanner has been significantly improved, increasing its typical lifetime by three times. EUV has demonstrated “solid progress,” she said, including ASML’s development of a membrane pellicle for EUV reticles.

While work with the ASML scanner on Intel’s 14nm pilot fab line has been “encouraging,” Turkot said, she added, “We do need to keep the momentum going.” Intel sees EUV entering into volume production with 7nm chips, according to Turkot. “It will be used when it’s ready,” she said.

EUV technology has shown “good progress” in productivity, while its availability and cost considerations have “a long way to go,” Turkot concluded, adding, “We need an actinic solution for the long term.”

An industry consensus has emerged that EUV will be used with ArF 193i immersion lithography in the near future, and this trend is likely to continue for some time, according to executives at the SPIE conference. There may also be wider adoption of directed self-assembly (DSA) and nanoimprint lithography technology, among other alternative lithography technologies.

Mark Phillips of Intel pointed to complementary implementation of EUV and 193i. “We must use EUV carefully,” he said. “We need to replace three-plus 193i masks.” Phillips added, “EUV can’t be applied everywhere affordably. 193i will continue to be used whenever possible.”

Nikon executives touted the capabilities of their new NSR-S631E ArF immersion scanner, introduced just before the SPIE conference. The new scanner can turn out 250 wafers per hour, and can be pushed to 270 wph with certain options, according to Nikon’s Ryoichi Kawaguchi.

Yuichi Shibazaki of Nikon said the company will next year introduce the S63xE scanner, improving on S631E.

For all the challenges of transitioning to 7nm and beyond, executives at SPIE remain optimistic about solving the issues of 193i multipatterning, DSA, and EUV. Harry Levinson of GlobalFoundries said in response to a question, “The ultimate resource is the human mind.”

Slowdown in Equipment Business Hits Applied’s Quarterly Results

Friday, February 19th, 2016

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By Jeff Dorsch, Contributing Editor

Applied Materials reported net income of $286 million on revenue of $2.257 billion for the fiscal first quarter ended January 31, compared with net income of $348 million on revenue of $2.359 billion in the same quarter of a year ago.  Orders in Q1 were $2.275 billion, flat with $2.273 billion a year earlier.

Applied said foundry customers accounted for 38 percent of orders in the first quarter of fiscal 2016, while DRAM manufacturers represented 29 percent, flash memory suppliers 22 percent, and logic/others 11 percent. One year ago, orders were evenly split between foundry and DRAM customers, at 34 percent for each segment.

The 4 percent reduction in Q1 revenue, year over year, reflects the current softness in the semiconductor equipment business. SEMI’s book-to-bill ratio for North American equipment suppliers has been below parity for the last three months, with a preliminary figure of 0.99 in January, subject to revision.

“As the market moves into the sweet spot for Applied’s materials engineering technology, we see strong demand for our semiconductor, display and service businesses,” Gary Dickerson, Applied’s president and chief executive officer, said in a statement. “We are maintaining a positive outlook for 2016 as our customers make strategic, inflection-driven investments that play to our strengths.”

Dickerson told analysts Wednesday, “We are growing beyond semiconductor.” Applied’s display business is being driven by the industry’s move to organic light-emitting diode displays, he said.

An OLED fabrication facility represents three times the potential spending on equipment for an amorphous silicon liquid crystal display plant, according to Dickerson. “I am confident about our growth,” he said. The company’s etch and chemical vapor deposition businesses are “making significant gains,” the CEO added.

While there are “global economic risks” in 2016, similar to those in 2015, 10-nanometer chips and 3D NAND flash memory devices are creating demand for production equipment, along with “increased spending in China” by domestic and foreign companies, Dickerson said. “There is a fierce battle for leadership in these new device categories,” he commented.

Capital spending at the silicon foundries in 2016 will be at “levels more or less the same as last year,” Dickerson added. Their capital expenditures for 10nm ICs is expected to pick up in the second half of calendar 2016, he predicted.

NAND flash investment will be up 25 percent from 2015, particularly for 3D NAND, Dickerson said. The “heavy DRAM investment” of 2015 will cool off this year, falling about 20 percent in 2016, he added.  Logic spending will be “relatively flat, year over year,” he said.

Bob Halliday, the company’s senior vice president and chief financial officer, forecast net income in the fiscal second quarter would be in the range of 30 to 34 cents per share, compared with 25 cents per share in Q1 and 28 cents per share in the first quarter of fiscal 2015. Thomson Reuters I/B/E/S said analysts were expecting an average of 26 cents per share for Q2.

Worldwide spending on wafer fabrication equipment will be flat in 2016, compared with 2015, Halliday said. “We expect our share to increase,” he added.

The Applied Global Services business is in its third year of growth and display is in its fourth year of growth, the CFO noted.

New Applied PVD system targets TiN hardmasks for 10nm, 7nm chips

Tuesday, May 19th, 2015

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By Jeff Dorsch, Contributing Editor

Applied Materials today introduces the Applied Endura Cirrus HTX PVD, a physical vapor deposition system for creating titanium nitride hardmask films that could be used in fabricating 10-nanometer and 7nm chips.

“Titanium nitride is the metal hardmask of choice,” harder than copper and nearly as hard as diamond, says Sree Kesapragada, Applied’s global product manager for Metal Deposition Products.

“Patterning plays key role in defining the interconnect,” Kesapragada says. “Perfect via alignment is critical for device yield. Hardmask ensures the perfect via alignment critical for yield.”

The hardmasks created with the Endura Cirrus HTX TiN system strike the required balance between neutral stress and film density hardness, he asserts. The TiN hardmask, meant to resist the erosion of etching, helps ensure that via etches land where they are supposed to, and not too close to neighboring vias, which can creates shorts.

Metal hardmask layer manages alignment errors.

Applied has worked with customers at multiple sites in developing the new PVD system over the past two to three years, according to Kesapragada. He emphasizes that the Cirrus HTX TiN system offers “precision control over TiN crystal growth,” as the process chamber is “designed for tensile high-density TiN films.” The new PVD system enables high density, tensile films thanks to a high level of ionization during deposition made possible by a high frequency source.

High film desnity is needed to prevent erosion, and a neutral-to-tensile stress is needed for pattern fidelity. CVD/ALD films have tensile stress, but are low density. Traditionally deposited TiN films have good density, but compressive stress.

The formation of “islands” of TiN crystals is almost like chemical vapor deposition, “layer by layer,” Kesapragada says, “in a PVD chamber.”

In the process chamber, the first of its kind, titanium atoms are reactively sputtered in a nitrogen-based plasma, allowing for tunable composition, according to Applied. This chamber can be used for high-volume manufacturing of semiconductors with 7nm features, covering two process-node generations, Kesapragada says.

There is also “very established integration” with chemical mechanical planarization equipment, he adds.

Applied is the market leader in TiN PVD systems, with more than 200 systems shipped, according to Kesapragada. Those PVD systems have more than 700 process chambers, he adds.

The Endura Cirrus HTX TiN PVD system is being formally introduced this week at the IEEE’s 2015 International Interconnect Technology Conference in Grenoble, France.

Solid State Watch: April 17-23, 2015

Friday, April 24th, 2015
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TSMC Certifies Mentor Graphics Tools for Early Design Start in TSMC’s 10nm FinFET Technology

Monday, April 6th, 2015

Mentor Graphics Corp. (NASDAQ: MENT) announced that TSMC and Mentor Graphics have reached the first milestone of their collaboration on 10nm EDA certification. Calibre® physical verification and design for manufacturing (DFM) platform, and the Analog FastSPICE™ (AFS™) Circuit Verification Platform, including AFS Mega, are certified by TSMC based on the most current version of 10nm design rules and SPICE models.  New tool feature enhancement based on 10nm process requirements has been made in Olympus-SoC™ digital design platform with TSMC validation, and certification of full chip integration is actively on-going. In addition to 10nm, Mentor has also completed 16FF+ version 1.0 certification of the Calibre, Olympus-SoC and AFS platforms. These certifications provide designers with the earliest access to signoff technology optimized for TSMC’s most advanced process nodes, with improved performance and accuracy.

“The long-term partnership we have with Mentor Graphics enables us to work closely from the earliest phases of technology development so we can have production ready design kits and software available for our customers concurrently with the announcement of new process offerings,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “Mentor’s design solutions have successfully met the accuracy and compatibility requirements for TSMC 10nm FinFET technology, so customers can initiate their designs with accurate verification solutions.”

The Analog FastSPICE Platform provides fast circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. For large circuits the AFS Platform also delivers high capacity and fast mixed-signal simulation. For embedded SRAM and other array-based circuits, AFS Mega delivers highly accurate simulation results.

As circuit reliability remains a focus, Mentor and TSMC have enhanced the Calibre PERC™ product offering in 10nm to ensure that design and IP development teams have robust verification solutions for identifying sources of electrical error. Additionally, the Calibre xACT™ extraction suite includes updated models to deliver more accurate results to fulfill tighter accuracy requirements of 10nm.

For TSMC’s 16FF+ 1.0 Calibre design kit release, the Calibre team has worked with TSMC to speed up DRC performance by 30% on average. In addition, TSMC and Mentor released new filling use models that will improve first-pass fill runs, making ECO changes easier and faster. The new fill methodology will also help ensure consistent cycle times during post fill verification.

“Because Mentor and TSMC work together from the earliest stages of design rule development for a new process node, we learn what the new design and verification challenges are right along with TSMC.” said Joseph Sawicki, vice president and general manager of the Design to Silicon division at Mentor Graphics. “This gives us the ability to have the most advanced capabilities in place for ecosystem early adopters, and to continue to optimize performance as the new process moves to full production status.”

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