Altera Jumps on TSMC’s CoWoS Process Offering
Altera Corp. became the latest company to jump on the 3D bandwagon, saying it is working with long-term manufacturing partner TSMC to develop heterogeneous 3D solutions that would combine an FPGA with a customer’s intellectual property, ranging from CPUs, ASICs, ASSPs, memory and optics.
The two companies have developed a heterogeneous 3D IC test vehicle, using TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process. That is the same 3D process that Xilinx is using to connect two FPGAs into single programmable logic devices, connected by through-silicon vias (TSVs) on an interposer.
Altera and TSMC have co-developed a 3D test vehicle. (Source: Altera)
Altera’s approach is to “move beyond Moore’s Law by stacking various technologies within a single device, including analog, logic and memory,” the company said. Customers can mix and match silicon IP based on their application requirements, “differentiating their applications by leveraging the flexibility of the FPGA.”
TSMC is providing the end-to-end CoWoS process, including the front-end manufacturing of the die and the back-end assembly and test of the bare die on an interposer with TSVs connecting the bare die. The approach offers multiple advantages in system performance and power, the partners said, as well as supporting a smaller form factor and reduced system cost.
While Xilinx can claim to be the first FPGA company to use a TSV interposer solution for a commercial product, Altera claims a broader vision, saying it is the first semiconductor company to develop and complete characterization of a heterogeneous test vehicle. The test vehicle will enable Altera to “quickly test the capabilities and reliability of 3D ICs to ensure they meet yield and performance targets,” the company said.
Bill Hata, senior vice president of worldwide operations and engineering at Altera, said, “Our partnerships with standards bodies like Imec and Sematech, and our use of TSMC’s leading-edge CoWoS manufacturing and assembly process, put us in an excellent position to execute on our strategy of delivering heterogeneous 3D devices to our customers at the right time and with the right set of features.”
Rick Cassidy, president of TSMC North America, said, “developing next-generation 3D ICs with Altera is a good example of how the two companies can work together to push semiconductor technology to another level.”
CoWoS is an integrated process technology that attaches device silicon chips to a wafer through a chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component. By attaching the device silicon to the original thick wafer silicon before it finishes the fabrication process, manufacturing-induced warping is avoided. TSMC has said it plans to offer CoWoS as a turnkey manufacturing service.
Altera is using TSMC's CoWoS integrated process technology. (Source: Altera)
March 26th, 2012 at 9:23 am
Foundries are looking at 2.5 D / 3 D as a way to bridge the gap with Intel who now leads them by 2 nodes. They make sense to Fabless co.s like Xilinx & Altera ( large dies in less cost driven small markets ) or IDMs who do not want to invest in latest nodes and wafer dia.s ( e,g. IBM ) but not for Smart Phones etc. as a MCM with Interposer ( 2.5 D ) would always be more expensive than a single chip from a leading edge Fab, which is why MCMs did not make any headway in the cost driven PC world. But on the other hand Intel has a ARM problem.