IBM Staying on SOI Technology for 14nm FinFETs
By David Lammers
Building on its successes with SOI technology, IBM will move to finFETs based on silicon-on-insulator wafers at the 14nm node.
Gary Patton, vice president of IBM’s Semiconductor Research & Development Center, said IBM will use SOI for all of its 14nm products, including the server processors it uses internally and the Asics it makes for itself and external customers, including SoCs made for video game vendors. Some of those chips will be made internally and others at external foundry partners, Patton said.
Speaking at the Common Platform Technology Forum, held in Santa Clara on March 14, Patton said SOI offers advantages which bulk silicon wafers do not have. The process complexity is reduced because the buried oxide layer “creates a built-in etch stop, which makes etching very simple. And the cost issues go away at the 14nm node,” he said, explaining that the cost of the SOI wafer is offset by the reduced number of process steps.
SOI also provides better soft error rate immunity than bulk. And since IBM has developed an embedded DRAM technology on its current SOI platform, he said carrying eDRAM forward to vertical transistors will be relatively straightforward.
The Fishkill Alliance of companies, including Samsung, GlobalFoundries, Toshiba, and others, will pursue bulk finFETs at the 14nm node, Patton added. IBM’s internal needs are a bit different from its alliance partners, in that the IBM server processors and other Asics “are very big chips, and the cost structure which servers can bear is higher.”
Besides embedded DRAM arrays, the IBM server ICs will have as many as 15 metal layers and various specialty circuits which IBM has created for its products.
IBM also is participating in a three-way alliance with STMicroelectronics and Leti to develop a planar SOI technology which offers fully depleted technology.
“SOI offers a couple of neat advantages, starting with the built-in etch stop. To create a fully depleted channel, we just need to deal with the incoming substrate and make sure it meets our specs. There is relatively little junction isolation compared with a bulk finFET, while in bulk you have to control the junction isolation. You don’t need well contacts. And anyone who does a cost analysis will conclude that the cost of isolation in bulk is comparable to the cost of the SOI wafer,” Patton said.
