News Stories

The Week In Review: May 20

Intel tries again; IC forecasts; Applied’s results; EUV/450mm challenges; building fab roads; switching to SOI

Manufacturing Bits: May 14

3D magnetic vortices; paper chips; flexible phones.

The Week In Review: May 13

EUV source vendor gives up; Atom vs. ARM; Obama visits Applied; R&D crunch; Cadence buys IP firm; Mentor’s cost assessment tool.

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Top Stories

Inside Leti’s Litho Lab

Directed self-assembly and multi-beam take on new importance as the future of EUV lithography remains in limbo.

Trickle Down Equipment Economics

Is the long downturn finally at an end for used equipment vendors? And what does that mean for everyone else?

3D NAND Market Heats Up

Planar approaches will have trouble scaling after 10nm due to floating gate issues; some companies may shift even sooner.

The Bumpy Road To 450mm

Progress has been made, but there’s still a lot of work to do over the next five years if the industry expects to meet its 2018 rollout schedule; economic benefits still being discussed.

3D Brings Test Into Fashion

Test is a big hurdle for stacking die. Technologies such as BiST are evolving to take up the slack.

New Foundry Gold Rush: RF SOI

Apple spearheads push to replace GaAS for RF front end, but how many foundries will the market support?

Experts At The Table: Issues In Metrology And Inspection

Last of three parts: Hybrid metrology; debate over directed self-assembly; new inspection tools; shrinking R&D dollars.

CMOS And SOI Invade RF Front End

Move to multi-mode, multi-band power amps makes material change more attractive, raises significant threat for GaAs suppliers.

Fixing DP Errors: Colors Or Rings

Double patterning is a necessity at 20nm, but it brings a number of new errors for the design team to deal with.

Waiting For 3D Metrology

While different parts of the semiconductor industry have embraced 3D transistors and die, there are still huge gaps on the tools side.

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Technology Features

Round Tables

Experts At The Table: Issues In Metrology And Inspection

First of three parts: What’s missing, what’s running out of steam, and best guesses for how to tackle issues at future process nodes.

Experts At The Table: Issues In Metrology And Inspection

Second of three parts: Litho challenges; thinner resists; overlay and process effects; finFETs; stacked die.

Experts At The Table: Issues In Metrology And Inspection

Last of three parts: Hybrid metrology; debate over directed self-assembly; new inspection tools; shrinking R&D dollars.

Experts At The Table: Issues In Lithography

Second of three parts: the future of e-beam and maskless; nanoimprint; DFM’s role in double patterning; a growing emphasis on collaboration.

Experts At The Table: Issues In Lithography

First of three parts: The future and current state of EUV, ArF, nanoimprint, DSA, and direct e-beam; how much will the next node cost; where will the development money come from.

Experts At The Table: Issues In Lithography

Last of three parts: EUV’s road map, venture capital, silicon photonics, directed self-assembly, and multipatterning.

Experts At The Table: IC Manufacturing Challenges

First of three parts: Process control, variability, lithography, materials, stacked die, Moore’s Law and 450mm wafers.

Experts At The Table: IC Manufacturing Challenges

Second of three parts: FinFET yields at different process nodes; controlling variance; differences between finFETs at 14nm and 10nm; SOI vs. bulk CMOS.

Experts At The Table: IC Manufacturing Challenges

Last of three parts: 450nm wafers; the effect of industry consolidation; TSVs; finFETs; stacked die; fully depleted SOI.

Experts At The Table: Stacked Die Reality Check

First of three parts: What’s done and what’s missing from the supply chain; how good are the tools; 2.5D vs. 3D; test issues; the role of standards and where they do and don’t exist; what will drive demand and when.

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Podcasts/Videos/Webcasts

FinFETs On SOI

What’s changing at the leading edge of Moore’s Law and why those changes are so important.

FinFETs, EUV And Moore’s Law

Progress and future problems with advanced processes—and where the solutions will come from.

Increasing Levels Of Risk

Double patterning, finFETs, design rules at advanced nodes are driving design for manufacturing into the stratosphere.

The Return Of RC Delay

It’s been talked about for years. Why is this issue suddenly so pressing?

Changes Ahead

One-on-one with GlobalFoundries EVP Mike Noonen.

Inflection Points

It’s the end of the line for planar transistors. Now what?

Looking Into The Future

The impact of multi patterning, new design rules and silicon photonics on semiconductor manufacturing in the future.

Future Foundry Issues

Semiconductor Manufacturing & Design talks with Luigi Capodieci, fellow at GlobalFoundries, about EUV, the challenges at 20nm and beyond, and the future of the foundry model.

The Future Of Manufacturing

A candid conversation with Randhir Thakur, general manager of Applied Materials’ Silicon Systems Group, about what’s changing in the foundries and the equipment needed to create ICs.

FinFETs And 3D ICs

The advent of an extra dimension in design could require some significant changes in materials and manufacturing.

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