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Top Stories — August 30, 2016
Fab Facilities Data and Defectivity
In-the-know attendees at SEMICON West at a Thursday morning working breakfast heard from executives representing the world's leading memory fabs discuss manufacturing challenges at the 4th annual Entegris Yield Forum.
Global Neon Demand Expected to Exceed Increasing Supply
Linde Electronics and Specialty Gases has made yet another investment to support its vertically integrated neon supply chain, by adding neon production capability to the company's largest US based atmospheric gases unit (ASU) in La Porte, Texas, which produces oxygen, nitrogen and argon for the petroleum and petrochemical markets in the Houston area.
Test Protocols for the IoT
The Internet-of-Things (IoT) will require components that can sense the world, process and store data, and communicate autonomously within a secured environment.
Applied Materials Intros High Res E-Beam Inspection System
Applied Materials, Inc. introduced its next-generation e-beam inspection system, PROVision, that offers resolution down to 1nm.
CMOS-Photonics Technology Challenges
imec and Mentor detail painstaking progress.
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News & Features
Final ITRS examines next 15 years of chip innovation
The Semiconductor Industry Association (SIA) announced the release of the 2015 International Technology Roadmap for Semiconductors (ITRS), a collaborative report that surveys the technological challenges and opportunities for the semiconductor industry through 2030. The current report marks the final installment of the ITRS.
Solid State Technology's Latest Issue
The July issue of SST features articles on the evolution of across-wafer uniformity control in plasma etch, Fan-Out Wafer Level Packaging (FOWLP), extending tungsten metallization for next-generation devices, ensuring safety in the sub-fab, and process control and production cycle time.
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Blogs/Twitter
Applied Innovation
eBeam Applications
eBeam technology is used in a variety of process control and monitoring applications to help optimize the quality ...
Chipworks
Soitec Bounces Back, Makes Gains in Mobile Phones, Automotive
July 11 - 15 was the week for the annual pilgrimage down to the SEMICON West show, though ...
Ed's Threads
Patterning with Films and Chemicals
Somewhere around 40nm is the limit on the smallest half-pitch feature that can be formed with a single-exposure ...
Insights From Leading Edge
IFTLE 300: ITRS 2.0 - It's the End of the World As We Know It
The 2015 International Technology Roadmap, was released earlier this summer by the SIA (Semiconductor Industry Association).
IC Design
Established Technology Nodes: The Most Popular Kid at the Dance
I remember back in the day at high school dances, always wanting to dance with the most popular ...
Pete's Posts Blog
Etch Abatement Needed at 200mm Fabs to Meet WSC Goals for 2020
The onus is on our industry to continue our efforts to reduce any adverse effects on the environment we all share.
Materials Matters
Transition to ISO 9001:2015: Starting the Journey
The revised ISO 9001 quality management system provides guidelines to help materials providers achieve stringent purity and process ...
Insights on Things
Tech Industry security highlighted by the iPhone access controversy
The confrontation between Apple and the FBI over the FBI's request for assistance in hacking a known terrorist's ...
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Videos/Podcasts
Edwards Vacuum on Safety Protocols in the Fab Environment
Pete Singer and Geoffrey Stoddart, Global Services Marketing Director, Edwards Vacuum, met up at SEMICON West 2016 to discuss ROI associated with safety investments in a fab setting, effective communication on fab safety topics, and raising awareness of safe wafer processing practices.
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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