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Top Stories — May 25, 2016
79 GHz CMOS RADAR Chips for Cars from Imec and Infineon
As unveiled at the annual Imec Technology Forum in Brussels, Infineon Technologies AG and imec are working on highly integrated CMOS-based 79 GHz sensor chips for automotive radar applications. Infineon and imec expect functional CMOS sensor chip samples in the third quarter of 2016.
How to Boost Verification Productivity with SystemVerilog/UVM and Emulation
Use of emulation for hardware-assisted testbench acceleration is growing as design verification teams find that simulation alone cannot deliver the coverage or performance needed to get large, complex designs to market on time. If your design requires millions of clock cycles to fully verify, you need both simulation and emulation.
Rhines Expounds on the Deconsolidation of the Semiconductor Industry
Wally Rhines, the Mentor CEO, challenged the conventional wisdom that the industry experienced unprecedented deal-making and combination in 2015. The number of deals involved, 30, wasn’t a record, he said. It was the "magnitude" of valuations in those transactions, with a number of multibillion-dollar acquisitions, he added.
IBM Achieves Storage Memory Breakthrough
For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM). PCM has attracted the industry's attention as a potential universal memory technology based on its combination of read/write speed, endurance, non-volatility and density.
Amkor and Cadence to Develop Packaging Assembly Design Kits for Amkor's SLIM and SWIFT Packaging Technologies
Amkor Technology, Inc., a outsourced semiconductor packaging and test service provider, announced the expansion of its collaboration with Cadence Design Systems, Inc. to streamline semiconductor package verification with the joint development of a package assembly design kit (PADK) for Amkor's SLIM and SWIFT advanced fan-out package technologies.
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News & Features
Smart City Devices to Top 1 Billion Units in 2025
Global unit shipments of smart city devices, which are internet-connected devices used in smart city projects, will increase from 115.4 million in 2015 to 1.2 billion in 2025, according to IHS Inc.
Solid State Technology's Latest Issue
The April issue of SST features articles on spintronic majority gates, China's new role in the semiconductor industry, mix-and-match lithography, post-etching silicon crystal defects on 300mm wafers as seen by AFM, and a report on monolithic Schottky diodes in ST F7 LV MOSFET technology.
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Blogs/Twitter
Applied Innovation
Examining Emerging Memory Technologies and 3D Architectures at IITC
Emerging memory technologies and the shift to 3D architectures have the potential to overcome current memory limitations in …
Insights on Things
Tech Industry security highlighted by the iPhone access controversy
The confrontation between Apple and the FBI over the FBI's request for assistance in hacking a known terrorist's …
Ed's Threads
Trefonas Earns 2016 Perkin Medal
The Society of Chemical Industry (SCI), America Group, announced on May 5, 2016 that Peter Trefonas, Ph.D., corporate …
Insights From Leading Edge
IFTLE 287 SMIC Ups the Ante on Packaging; IMAPS DPC 2016 part 4; SiP, Sputtered Cu Shielding and Si TF Caps
Following the lead of global foundry leader TSMC, SMIC, in two separate moves has put an additional $0.5B …
Materials Matters
Transition to ISO 9001:2015: Starting the Journey
The revised ISO 9001 quality management system provides guidelines to help materials providers achieve stringent purity and process …
IC Design
Collaborative SoC Verification
With the widespread use of system-on-chip (SoC) designs, efficient integrated circuit (IC) design and validation is now a …
Chipworks
What to Expect in 2016 in the Chipworld
It's the time in the media world that we see a frenzy of predictions for the coming year….
Pete's Posts Blog
10 Reasons to Attend The ConFab this June
The ConFab Conference and Networking Event will be held June 12-15. Presented by Solid State Technology, this executive-level …
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Videos/Podcasts
Solid State Watch: May 13-19, 2016
IBM scientists achieve storage memory breakthrough; Kateeva closes its Series E funding round with $88 million in new financing; Worldwide silicon wafer area shipments increased during the first quarter 2016 when compared to fourth quarter 2015 area shipments; New type of graphene-based transistor will increase the clock speed of processors.
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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