Join the Community Visit Website News Blogs Resource Center About Us
Top Stories — April 20, 2016
Controlling Variabilities When Integrating IC Fab Materials
The Critical Materials Conference 2016—to be held May 5-6 in Hillsboro, Oregon (—will explore best practices in the integration of novel materials into manufacturing
IoT Demands Part 1: EDA and Fab Nodes
To meet the anticipated needs of the different IoT application spaces, SemiMD asked leading companies within critical industry segments about the state of technology preparedness.
IoT Demands Part 2: Test and Packaging
To understand the state of technology preparedness to meet the anticipated needs of the different application spaces, experts from GLOBALFOUNDRIES, Cadence, Mentor Graphics and Presto Engineering gave detailed answers to questions about IoT chip needs in EDA and fab nodes.
Roll-to-Roll Coating Technology: It's a Different Ball of Wax
Manufacturing flexible electronics and coatings for a variety of products has some similarities to semiconductor manufacturing and some substantial differences, principally roll-to-roll fabrication, as opposed to making chips on silicon wafers and other rigid substrates. This interview is with Neil Morrison, senior manager, Roll-to-Roll Coating Products Division, Applied Materials.
The Future Is Flexible and Printed
Automotive electronics, the Internet of Things, wearable gadgets, and other emerging chip markets are also expected to provide growth for flexible electronics, which often share manufacturing processes and materials with semiconductors.
Functional Safety, Security for IoT Stressed at Cadence Event
The "big trends" in the electronics industry are social, mobility, the Internet of Things, and security, Lip-Bu Tan, the president and chief executive officer of Cadence Design Systems, said Tuesday (April 5) in his keynote address at the CDNLive Cadence User Conference in Santa Clara, Calif.
more top stories
News & Features
Intel Will Cut Up to 12,000 Jobs
Intel announced that it is embarking on an extended restructuring program, eliminating up to 12,000 positions around the world, a percent reduction in force of about 11 percent, by mid-2017. The cutbacks will include a consolidation of facilities with involuntary and voluntary departures by employees.
Solid State Technology's Latest Issue
The March issue of SST features articles on the impact of triboelectric charging from DI water on transistor gate damage, system-level MEMS design, the neon gas supply shortage, a look at how silicide processes have evolved, hazardous process exhaust management, a new class of MFCs, and trace metal contamination.
more news & features
Pete's Posts Blog
10 Reasons to Attend The ConFab this June
The ConFab Conference and Networking Event will be held June 12-15. Presented by Solid State Technology, this executive-level ...
IC Design
Collaborative SoC Verification
With the widespread use of system-on-chip (SoC) designs, efficient integrated circuit (IC) design and validation is now a ...
Ed's Threads
Andy Grove blessed us all
Andy Grove, the man who codified the commercial IC industry dynamic as “Only the Paranoid Survive” died yesterday ...
Insights From Leading Edge
IFTLE 283 Will Packaging Make the Difference for TSMC?
The Taipei Times headline on April 18th read “New packaging may spur TSMC growth” adding that despite its ...
Materials Matters
Transition to ISO 9001:2015: Starting the Journey
The revised ISO 9001 quality management system provides guidelines to help materials providers achieve stringent purity and process ...
Insights on Things
Tech Industry security highlighted by the iPhone access controversy
The confrontation between Apple and the FBI over the FBI's request for assistance in hacking a known terrorist's ...
What to Expect in 2016 in the Chipworld
It's the time in the media world that we see a frenzy of predictions for the coming year. ...
Viewpoints: SEMI
Update for exporters: Trade wins and delays
With trade policy dominating headlines in recent weeks, all eyes were on Maui in the waning days of ...
more blogs
Our Sponsors
Solid State Watch: March 6-12, 2015
Cypress and Spansion complete merger; Strong fab equipment spending forecast for 2015; 11 IC product categories to exceed total IC market growth in 2015; Global mobile phone display module shipments signal stronger competition among manufacturers
More Videos/Podcasts
White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
more white papers