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Top Stories — December 21, 2015
Packaging Conference Addresses Challenges, Opportunities in New Technologies
On the second day of the 12th annual 3D ASIP conference, the heavy hitters came out to talk. Attendees heard presentations from executives of Amkor Technology, the Defense Advanced Research Projects Agency (DARPA), Northrop Grumman, Taiwan Semiconductor Manufacturing, Teledyne Scientific & Imaging, and Xilinx, among other companies.
Dow, DuPont to Merge in Combination of Chemical Giants
In a deal with significant implications for high-tech chemicals and materials, The Dow Chemical Company and E. I. du Pont de Nemours and Company (DuPont) have agreed to merge, forming the second largest chemical company in the world, behind BASF SE.
IoT Will Enable 'Living Services,' Keynote Speaker Says
"It's not about the sensors," Nandini (Nan) Nayak, managing director of design strategy at Fjord, said Thursday morning (December 3) in a keynote address at the Designers of Things conference in San Jose, Calif.
Identifying the Prime Challenge of IoT Design
Low-cost IoT designs, which interface the edge of the real world to the Internet, mesh together several design domains. Individually, these design domains are challenging for today's engineers. Bringing them all together to create an IoT product can place extreme pressure on design teams.
Tallness Makes Reliable Spindt Tip Cold Cathodes
Vacuum nanowire arrays of cold cathodes for high frequency sources and amplifiers
IoT Security, Software Are Highlighted at ARM TechCon
Many people are aware of the Internet of Things concept. What they want to know now is how to secure the IoT and how to develop code for it.
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News & Features
Solid State Technology's Latest Issue
The December issue of SST features articles on how variation in build-up substrate layer thicknesses and its impact on FCBGA BLR performance, a new advanced lithography and electroplating approach to form high-aspect ratio copper pillars, practical limits for metallization scaling in fabs, feed-forward overlay control in lithography processes using CGS, and what happens when front-end-of-line and back-end-of-line reliability meet.
Advanced semiconductor packaging drives materials consumption through 2019
According to the newly released "Global Semiconductor Packaging Materials Outlook — 2015/2016 Edition," the $18 billion semiconductor packaging materials will undergo steady single-digit unit volume growth for many material segments through 2019, including laminate substrates, IC leadframes, underfill, and copper wire.
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Blogs/Twitter
Materials Matters
Transition to ISO 9001:2015: Starting the Journey
The revised ISO 9001 quality management system provides guidelines to help materials providers achieve stringent purity and process ...
IC Design
Electromigration and IC Reliability Risk
Electromigration (EM) is the transport of material caused by the gradual movement of the ions in a conductor, ...
Ed's Threads
Apple Fab Speculation
Apple Corp. recent purchased an old 200mm-diameter silicon wafer fab in San Jose capable of creating as small ...
Insights From Leading Edge
IFTLE 266 IMAPS Goes Searchable; GaTech Interposer Conf Part 3
Of upmost importance to researchers at Universities, Research Institutes and even Commercial Companies is the ability of others ...
Pete's Posts Blog
The First Degree - Ominous Threshold Reached
In light of the Paris climate talks going on this week, I'm delighted to turn this blog over to a guest blogger, Mike Czerniak.
MEMS Industry Group Blog
Check out the finalists for MEMS & Sensors Technology Showcase at MEMS Executive Congress 2015
The annual crowd-pleasing favorite, MEMS & Sensors Technology Showcase at the 11th annual MEMS Executive Congress US 2015, ...
Chipworks
Intel/Micron Detail Their 3D-NAND at IEDM
On the Monday afternoon at IEDM the key paper for me was the Intel/Micron talk on their 3D-NAND ...
ASN's All Things SOI
GF's 22nm FD-SOI Offering - Where to Get Lots of Excellent Info
A fast-growing body of information is now posted by GlobalFoundries on their new 22nm FD-SOI offering.
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Videos/Podcasts
Solid State Watch: December 4-10, 2015
Semiconductor fab equipment spending growth in 2015; NXP and Freescale complete merger; Atomically-flat tunnel transistor overcomes fundamental power challenge of electronics; Imec boosts performance of beyond-silicon devices
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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