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Top Stories — August 31, 2015
Managing Dis-Aggregated Data for SiP Yield Ramp
In general, there is an accelerating trend toward System-in-Package (SiP) chip designs including Package-On-Package (POP) and 3D/2.5D-stacks where complex mechanical forces—primarily driven by the many Coefficient of Thermal Expansion (CTE) mismatches within and between chips and packages—influence the electrical properties of ICs.
3D NAND Goes Mainstream
There is still much work to be done if 3D NAND applications like Samsung's 16TB drive are to make their way into the cost-sensitive consumer market. Brad Howard of Applied Materials writes about a panel discussion with colleagues from Cypress, Micron, Samsung and SK Hynix at the Flash Memory Summit 2015 in Santa Clara, California.
The Changing (and Challenging) IC Reliability Landscape
It seems that a laser focus on integrated circuit (IC) reliability is all around us now. Gone are the days when a little "over design," or additional design margin, could cover the reliability issues in a design layout. Designers now need to articulate to partners, both internal and external, just how well their designs function over time and within their intended environment.
Larger Fabs + Smaller Devices = More Gases
Semiconductor manufacturers are pushing the limits of physics and driving a constant need for new materials. The highly competitive mobile devices market is forcing fabs to ramp to higher volumes faster than ever before to meet market demands. 2014 saw a 10% upsurge worldwide in integrated circuits. Additionally, development costs for new technology can exceed $2B.
Neon Gas Supply Issues Dog the Semiconductor Industry
The armed conflict in Ukraine, where most of the world's supply of neon gas for semiconductor manufacturing and other industrial applications is produced, is leading lithography equipment vendors to offer ways to reduce use of neon, which is utilized as a buffer gas for argon fluoride and krypton fluoride gases employed in lasers for chip production. Jeff Dorsch reports.
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News & Features
Solid State Technology's Latest Issue
The July issue of SST features articles on SOI substrates for extending Moore and more than Moore; controlling measurements in WLP in high mix, high volume manufacturing; a summary of the OASIS mask standard, how ECAE improves sputtering target performance, and a report on how the emerging market for connected smart devices will bring more changes to the semiconductor sector.
Small Electronics Companies Spent $78.3B on Semiconductors in 2014
Startups and small electronics companies spent $78.3 billion on semiconductors in 2014, representing 23 percent of the total market, compelling semiconductor companies to revisit their sales strategy to focus on the large number of smaller organizations than relying on big deals from large customers, research firm Gartner said.
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Blogs/Twitter
Pete's Posts Blog
IoT Surveys Indicate Optimism, Confusion
Recent surveys indicate much optimism about how the IoT will benefit the semiconductor industry, but there's some confusion ...
Chipworks
Apple Watch and ASE Start New Era in SiP
Back in April the Apple watch appeared in our labs, and of course we pulled it apart to ...
Ed's Threads
Cross-point ReRAM Integration Claimed by Intel/Micron
The Intel/Micron joint-venture now claims to have successfully integrated a Resistive-RAM (ReRAM) made with an unannounced material in ...
Insights From Leading Edge
IFTLE 251 3DIC NAND vs 3D V-NAND
A few years ago in IFTLE 62, we laughed when EE Times reporters got confused and unknowingly compared ...
Viewpoints: SEMI
Update for exporters: Trade wins and delays
With trade policy dominating headlines in recent weeks, all eyes were on Maui in the waning days of ...
Applied Innovation
3D NAND Goes Mainstream
Earlier this month, I participated in a panel discussion with colleagues from Cypress, Micron, Samsung and SK Hynix ...
Materials Matters
Fabs Seeking Higher Quality Electronic Materials to Meet Technology Demands
IC technology step changes are driving electronic materials purity and analytical requirements. The bottom line? Materials suppliers must ...
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Videos/Podcasts
Solid State Technology: August 7-14, 2015
New research could enhance LEDs and displays; Intel to collaborate with Georgia Tech; imec extends its GaN R&D program; Strong silicon wafer area shipment growth reported in second quarter of 2015
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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