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Top Stories — January 27, 2015
Changes and challenges abound in multi-patterning lithography
Multi-patterning lithography is a fact of life for many chipmakers. Experts in the fields of electronic design automation and lithography address the issues associated with the technology. Providing responses are David Abercrombie, Design for Manufacturing Program Manager, Mentor Graphics; Gary Zhang, Vice President Marketing, ASML Brion; and Dr. Donis Flagello of Nikon Research Corporation of America.
Solid Doping for Bulk FinFETs
In another example of the old one-liner that "all that is old is new again," the old technique of solid-source doping is being used by Intel for a critical process step in so-called "14nm node" finFET manufacturing.
IEDM: Thanks for MEMS-ories
At the 60th annual International Electron Devices Meeting this week in San Francisco, there was much buzz about the 14-nanometer FinFET papers being presented by IBM and Intel. Those papers were the subject of a press release two months in advance.
3D ASIP: "It's Complicated"
The presentations at this week's 3D Architectures in Semiconductor Integration and Packaging conference could be summed up in a famous Facebook status.
Germanium Junctions for CMOS
Enabling NMOS using Ge channels for CMOS finFETs.
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News & Features
Blog review January 26, 2015
News blogs report on Scott McGregor's talk at ISS (where he said exponentially rising costs will bring major changes), robust design with IP, FinFET day at IEDM, multiferroic switches, the RAMI act, IEEE 3DIC conference, SOI at IEDM, and the CES show.
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Blogs/Twitter
Pete's Posts Blog
Exponentially Rising Costs Will Bring Changes
Scott McGregor, President and CEO of Broadcom, sees some major changes for the semiconductor industry moving forward, brought …
IC Design
This IP Will Work…I GUARANTEE It!
Intellectual property (IP) is usually bought from a 3rd party vendor or developed by a specialized internal IP …
Applied Innovation
What's in a Name? Innovation for Humanity
The project names Gooru, Nanoly, and Sanergy are intriguing. The fact these names represent efforts all over the …
Ed's Threads
Ferromagnetic Room Temperature Switching
Bismuth-ferrite could make spin-valves that use 1/10th the power of STT A research team led by folks at …
Materials Matters
Emerging Requirements for Electronic Materials Product Quality and Metrology
Technology changes in semiconductor processing and demands for higher-purity and better-characterized electronic materials have driven the need for …
ASN's All Things SOI
10nm FD-SOI, SOI FinFETs at IEDM 2014
FD-SOI at 10nm (and other nodes) as well as SOI FinFETs shared the spotlight at IEDM2014 (15-17 December …
Insights From Leading Edge
IFTLE 226 RTI ASIP Part 2: 3D Memory, Heterogeneous Integration, High Density Laminates, Embedded films
Let's continue our end of year look at presentations at the RTI ASIP Conference.
MEMS Industry Group Blog
Wearable Devices and the Search for the Holy Grail at 2015 International CES
Several years ago, I coined the phrase "MEMS frickin' everywhere." I shared my vision for MEMS enabling a …
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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