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Top Stories — October 27, 2014
RF and MEMS Technologies to Enable the IoT
Communications and energy-harvesting capabilities can be integrated into ubiquitous always-on smart nodes.
Are We At an Inflection Point with Silicon Scaling and Homogeneous ICs?
In the late 1940's, three physicists (Bardeen, Brattain and Shockley) invented the first transistor and were later awarded the Nobel Prize in 1956.
How Will Analog and Sensors Impact the IoT?
What challenges await designers and implementers on the monolithic mixed signal sensor side of the IoT equation? Several experts from the IoT ecosystem have differing viewpoints on these questions including Patrick Gill, Principal Research Scientist at Rambus; Ian Chen, Marketing, Systems, Applications, Software & Algorithms manager at Freescale; Pratul Sharma, Technical Marketing Manager for the IoT at ARM; and Diya Soubra, CPU Product Manager at ARM.
TSV Market Demand Now for Performance not Size
High-performance applications pull for premium packaging solutions.
GLOBALFOUNDRIES to Acquire IBM's Chip Operations
GLOBALFOUNDRIES will acquire IBM's global commercial semiconductor technology business, including IBM's intellectual property, technologists and technologies. IBM will pay GLOBALFOUNDRIES $1.5 billion in cash over the next three years to take the chip operations off its hands.
Intel and IBM to lay out 14nm FinFET strategies on competing substrates at IEDM 2014
In two late-news papers to be given at this December's IEEE International Electron Devices Meeting (IEDM), Intel and IBM will present dueling approaches to the development of FinFET technology for the 14nm technology node, the semiconductor industry's next big hurdle.
ARM Expands into Enterprise Servers and IoT
At the ARM TechCon earlier this month, Pete Hutton, president of ARM's products group, said that ARM was addressing the Internet of Things in many ways, from 64-bit chips for enterprise servers to microcontrollers for sensor-oriented applications.
Deeper Dive – Mentor Graphics Looks to the Future
There has been a great deal of handwringing and naysaying about the industry's progress to the 14/16-nanometer process node, along with wailing and gnashing of teeth about the slow progress of extreme-ultraviolet lithography, which was supposed to ease the production of 14nm or 16nm chips. Joseph Sawicki, vice president and general manager of Mentor's Design-to-Silicon Division, is having none of it.
Threshold voltage tuning for 10nm and beyond CMOS integration
A novel metal gate integration scheme to achieve precise threshold voltage (VT) control for multiple VTs is described.
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News & Features
Research Alert: October 14, 2014
Revving up fluorescence for super fast LEDs; Smallest world record has 'endless possibilities' for bio-nanotechnology; Printing in the hobby room: Paper-thin and touch-sensitive displays on various materials
Blog review October 20, 2014
New blogs delve in the challenges of IC verification for automotive electronics, the need for higher purity and better-characterized electronic materials, SEMI's recent Strategic Materials Conference, the IoT and need for security, IBM's work on graphene, the polymer dielectric market, a recent IMAPS workshop, the Nobel Prize in physics and FD-SOI at Semicon Europa.
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Blogs/Twitter
Insights From Leading Edge
IFTLE 214 Nanium's Mamouth WLCSP, IBM Deal Done; Cu WB at TI
Most of us know of Nanium as a contract assembly house in Portugal who licensed the Infineon eWLB ...
Materials Matters
Emerging Requirements for Electronic Materials Product Quality and Metrology
Technology changes in semiconductor processing and demands for higher-purity and better-characterized electronic materials have driven the need for ...
IC Design
My Design's Interconnect Has Enough Wire Width to Withstand ESD… Doesn't It?
While layout engineers are struggling to implement interconnect that meets chip area goals, they must also be concerned ...
Applied Innovation
What's in a Name? Innovation for Humanity
The project names Gooru, Nanoly, and Sanergy are intriguing. The fact these names represent efforts all over the ...
ASN's All Things SOI
FD-SOI Front and Center at Very Successful SEMICON Europa
Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm's interested in it for IoT. Yes, ST's got more amazing ...
Pete's Posts Blog
Don't Hack My Light Bulb, Bro
Many people believe that the lowly light bulb might be how the IoT makes it's way into your ...
Ed's Threads
Nakamura Co-Wins Nobel for Blue LEDs
The Nobel Prize in Physics 2014 was awarded jointly to Isamu Akasaki, Hiroshi Amano, and Shuji Nakamura “for ...
Viewpoints: SEMI
SEMICON Europa 2014 in Grenoble Expands by 40%: Increasing Opportunities as Supply Chain Complexity Grows
SEMICON Europa 2014, the industry's opportunity to network with customers, suppliers, partners and peers, opens today at ALPEXPO ...
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Videos/Podcasts
Solid State Watch: SEMICON Europa Special Edition
Pete Singer interviews new CEA-Leti CEO in Grenoble, France.
David Chu, Applied Materials
Pete Singer interviews David Chu, Strategic Marketing Director, Dielectric Systems and Modules Group, Applied Materials.
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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