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Top Stories — September 25, 2014
ASML on EUV: Available at 10nm
Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.
Design and Manufacturing Technology Development in Future IC Foundries
Virtual Roundtable provides perspective on the need for greater integration within the "fabless-foundry" ecosystem.
Process Watch: Sampling matters
In this article, it is assumed that the first two sampling components— sites per wafer and wafers per lot, are part of your capability strategy (addressed in the previous article), and that the word sampling refers simply to the percentage of the measured lots.
SPIE Photomask Technology Wrap-up
Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn't the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.
Foundry, EDA partnership eases move to advanced process nodes
Partnerships are the lifeblood of the semiconductor industry, and when moving to new advanced nodes, industry trends show closer partnerships and deeper collaborations between foundries, EDA vendors and design companies to ease the transition.
Intel Announces "New Interconnect" for 14nm
Intel has just announced that "Embedded Multi-die Interconnect Bridge (EMIB") packaging technology will be available to 14nm foundry customers.
SPIE panel tackles mask complexity issues
Photomasks that take two-and-a-half days to write. Mask data preparation that enters into Big Data territory. And what happens when extreme-ultraviolet lithography really, truly arrives?
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News & Features
Research Alert: September 9, 2014
GLOBALFOUNDRIES and SRC announce new scholarship for undergraduate engineering students; Layered graphene sandwich for next generation electronics; Doped graphene nanoribbons with potential
Blog review September 22, 2014
New blogs report on the recipients of Tech Awards from The Tech Museum of Innovation, why RF-SOI is good for more than integrating RF switches, the use of TSVs in Samsung's 64 GB DDR4, MEMS in Shanghai at MIG's event, the Revitalize American Manufacturing and Innovation (RAMI) Act, the growing complexity of fill in IC design, and a potential game-changer for 3D ICs.
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Blogs/Twitter
Insights From Leading Edge
IFTLE 210 IBM Global Foundries reaching closure?; Semicon Taiwan 2014 part 1: Hitachi Chem & SPIL
When last we discussed the soap opera that is called the IBM Global Foundries negotiations, I confirmed that ...
Materials Matters
Gas Applications in Lithography
This article provides an overview of existing gas applications in lithography and how Linde is addressing customer needs ...
IC Design
Automotive Opportunities Present New Challenges for IC Verification
The automotive electronic landscape is changing.
Applied Innovation
What's in a Name? Innovation for Humanity
The project names Gooru, Nanoly, and Sanergy are intriguing. The fact these names represent efforts all over the ...
ASN's All Things SOI
ST's Integrated RF-SOI For Front-End Modules: Why Designers Like It
RF-SOI is good for more than integrating RF switches. Other key functions typically found inside RF Front-End ...
Chipworks
The Second Shoe Drops - Now We Have the Samsung V-NAND Flash
Two weeks ago, we posted about the TSMC 20nm product that we had in-house; now after waiting for ...
Ed's Threads
Leti integrates everything
Now I know how wafers feel when moving through a fab. Leti in Grenoble, France does so much ...
Viewpoints: SEMI
SEMI Commends House Passage of Bi-Partisan Manufacturing Innovation Act
SEMI praised the bipartisan effort in the United States House of Representatives to pass H.R. 2996, the Revitalize ...
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Videos/Podcasts
Solid State Watch: September 12-18, 2014
EUV available at 10nm; Mentor Graphics appoints new VP of Embedded Systems; ProPlus expands operations in Europe; Rudolph releases new SONUS technology
Interview with David Chu, Applied Materials
Pete Singer interviews David Chu, Strategic Marketing Director, Dielectric Systems and Modules Group, Applied Materials.
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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