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Top Stories — July 31, 2014
An EDA view of semiconductor manufacturing
The concern that there is a significant break between tools used by designers targeting leading edge processes, those at 32 nm and smaller to be precise, and those used to target older processes was dispelled during the recent Design Automation Conference (DAC).
Moore’s Law is Dead
This four part series by Ed Korczynski, explains why we are past the era when the next chips will be simultaneously faster and smaller and cheaper and more functional. Ed says we have to accept the end of Dennard Scaling and the economic limits of optical lithography.
Sustainability through Materials Recovery
Recovering and reusing materials is becoming an increasingly essential consideration in order to ensure consistent quality, a stable supply of materials, and lower costs. On- and off-site options are reviewed for helium, argon, sulfuric acid and Xenon.
SoC Reliability Verification Doesn’t Just Happen, You Know
How do we verify multi-IP, multiple power domain SoCs? The Unified Power Format (UPF) enables a repeatable, comprehensive, and efficient design verification methodology, using industry standards, at the transistor level. It can help simplify multiple power domain verification by enabling a consistent description of the power intent throughout the design flow.
Fusion bonding for next-generation 3D-ICs
Recent developments in wafer bonding technology have demonstrated the ability to achieve improved bond alignment accuracy.
Cryogenic etching reduces plasma-induced damage of ultralow-k dielectrics
Reducing plasma-induced damage is key to advancing the scaling limits.
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News & Features
Research Alert: July 16, 2014
A nanosensor to identify vapors based on a Graphene/Silicon heterojunction Schottky diode; A cool approach to flexible electronics; Graphene grain boundaries reviewed
Blog review July 21, 2014
New blogs discuss the best way to verify multi-IP, multiple power domain SoCs, contemplate what TSMC may have changed in 20nm devices from the 28nm generation, what happens when we run out of room "at the bottom" around 4nm, the recent EUV lithography workshop, presentations from The ConFab last month, and Qualcomm's perspective on 3D integration.
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Applied Innovation
Applied Materials Recognized for Leading Green Power Use by EPA
In the U.S. Environmental Protection Agency's (EPA) Green Power Partnership report released this week, Applied ranked No. 82 ...
Materials Matters
Sustainability through Materials Recovery
Recovering and reusing materials is becoming an increasingly essential consideration in order to ensure consistent quality, a stable ...
Pete's Posts Blog
Can we take cost out of technology scaling?
At The ConFab, IBM's Gary Patton spoke about the future of scaling and concluded that it we will ...
Insights From Leading Edge
IFTLE 202 ConFab 2014: Novati, Lumileds; Chipworks; IEEE CPMT Packaging Panel
Dave Anderson, CEO of Novati talked about “More-than-Moore, Advanced Packaging and Creating Game-Changing Innovation.”
ASN's All Things SOI
The SOI Papers at VLSI 2014 (Part Two)
Last week, we posted Part 1 of our round-up of SOI papers at the VLSI Symposia - which ...
TSMC 20nm Arrives - The First Shoe Drops
For us at Chipworks interested in leading edge processes, 2014 so far has been the year of waiting ...
Ed's Threads
Moore's Law is Dead - (Part 4) Why?
We forgot Moore merely meant that IC performance would always improve (Part 4 of 4) IC marketing must ...
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Solid State Watch: June 27-July 3, 2014
Gigaphoton achieves 92W EUV light source output; New graphene substitute has HVM potential; SMIC and Qualcomm collaborate; Nanolab Technologies acquires Microtech
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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